 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 74ACT533 Octal Transparent Latch with 3-STATE Outputs August 1999 Revised March 2005 74ACT533 Octal Transparent Latch with 3-STATE Outputs General Description The ACT533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. Features s ICC and IOZ reduced by 50% s Eight latches in a single package s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s Inverted version of the ACT373 s TTL-compatible inputs Ordering Code: Order Number 74ACT533SC 74ACT533MTC 74ACT533PC Package Number M20B MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0-D7 LE OE O0-O7 Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs FACT is a trademark of Fairchild Semiconductor Corporation. (c) 2005 Fairchild Semiconductor Corporation DS500311 www.fairchildsemi.com 74ACT533 Functional Description The ACT533 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table Inputs LE X H H L H L Z X O0 Outputs Dn X L H X On Z H L O0 OE H L L L HIGH Voltage Level LOW Voltage Level High Impedance Immaterial Previous O0 before HIGH-to-LOW transition of Latch Enable Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74ACT533 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI 0.5V to 7.0V 20 mA 20 mA 0.5V to VCC 0.5V 20 mA 20 mA 0.5V to VCC 0.5V r 50 mA r 50 mA 65qC to 150qC r 300 mA 140qC Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate 'V/'t VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns 4.5V to 5.5V 0V to VCC 0V to VCC 0.5V VCC 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO 40qC to 85qC 0.5V VCC 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latchup Source or Sink Current Junction Temperature (TJ) PDIP Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 4.0 75 mA mA VOLD VOHD VIN or GND 1.65V Max 3.85V Min V CC 5.5 5.5 0.6 5.5 0.001 0.001 TA Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 25qC TA 40qC to 85qC 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 Guaranteed Limits Units V V V VOUT VOUT IOUT VIN V IOH IOH V IOUT VIN V IOL IOL VI VI VO Conditions 0.1V 0.1V or VCC 0.1V or VCC 0.1V 50 PA VIL or VIH 24 mA 24 mA (Note 2) 50 PA VIL or VIH 24 mA 24 mA (Note 2) VCC, GND VIL, VIH VCC, GND VI VCC 2.1V r0.1 r1.0 PA r0.25 r2.5 1.5 PA mA 75 40.0 PA Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74ACT533 AC Electrical Characteristics VCC Symbol Parameter (V) (Note 4) tPHL tPLH tPHL tPLH tPZL, tPZH tPHZ, tPLZ Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time Output Disable Time 5.0 5.0 2.0 1.0 7.0 8.0 9.0 10.0 2.0 1.0 9.5 10.5 ns ns 5.0 2.5 7.0 9.0 2.5 9.5 ns 5.0 Min 2.0 TA CL 25qC 50 pF Typ 6.0 Max 8.0 TA 40qC to 85qC CL Min 2.0 50 pF Max 8.5 ns Units Note 4: Voltage Range 5.0 is 5.0V r 0.5V. AC Operating Requirements VCC Symbol Parameter (V) (Note 5) tS tH tW Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH 5.0 2.0 4.0 4.0 ns Note 5: Voltage Range 5.0 is 5.0V r 0.5V. TA CL Typ 0 0 25qC 50 pF TA 40qC to 85qC CL 50 pF Units Guaranteed Minimum 3.0 1.5 3.0 1.5 ns ns 5.0 5.0 Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 40 Units pF pF VCC VCC OPEN 5.0V Conditions www.fairchildsemi.com 4 74ACT533 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74ACT533 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 74ACT533 Octal Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
Price & Availability of 74ACT533MTC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |