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IMAGE SENSOR SOLUTIONS
DEVICE PERFORMANCE SPECIFICATION
KODAK KAC-1310 Image Sensor
1280 (H) x 1024 (V) SXGA CMOS Image Sensor
November 7, 2002 Revision 4
KAC-1310 Rev. 4
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS TABLE OF CONTENTS
TABLE OF FIGURES........................................... 3 LIST OF TABLES................................................. 3 SUMMARY SPECIFICATION .............................. 5 PIN DEFINITIONS................................................ 6 RECOMMENDED HARDWARE FOR KAC-1310 SENSOR EVALUATION: ........................................ 7 DEVICE DESCRIPTION....................................... 8 PIXEL ARCHITECTURE ....................................... 10 COLOR FILTERS AND LENSLETS......................... 11 FRAME CAPTURE MODES.................................. 11 CONTINUOUS FRAME ROLLING SHUTTER CAPTURE MODE (CFRS) ................................................. 11 CFRS VIDEO ENCODED DATA STREAM ............. 12 SINGLE FRAME ROLLING SHUTTER CAPTURE MODE (SFRS) ........................................................... 12 WINDOW OF INTEREST (WOI) CONTROL............ 12 SUB-SAMPLING CONTROL (RESOLUTION) .......... 12 VIRTUAL FRAME (VF)........................................ 13 INTEGRATION TIME ........................................... 13 CFRS INTEGRATION TIME................................. 13 SFRS INTEGRATION TIME................................. 14 FRAME RATE .................................................... 14 CFRS FRAME RATE ......................................... 14 SFRS FRAME RATE ......................................... 15 ANALOG SIGNAL PROCESSING CHAIN..... 16 (ASP) .............................................................. 16 FRAME RATE CLAMP (FRC) .............................. 16 COLUMN DIGITAL OFFSET VOLTAGE ADJUST (CDOVA) ........................................................ 16 PROGRAMMABLE GAIN AMPLIFIER (PGA) .......... 17 GAIN MODES .................................................... 17 Raw Gain Mode: ........................................ 17 Lin1 Gain Mode:......................................... 17 Lin2 Gain Mode:......................................... 17 WHITE BALANCE CONTROL PGA (WB GAIN)..... 19 EXPOSURE GAIN PGA (EXP GAIN A/B) ............. 20 GLOBAL DIGITAL OFFSET VOLTAGE ADJUST (GDOVA) ........................................................ 20 ANALOG TO DIGITAL CONVERTER (ADC) ........... 20 PERFORMANCE................................................ 21 TEST CONDITIONS ............................................ 21 IMAGING PERFORMANCE ................................... 21 QUANTUM EFFICIENCY...................................... 23 DYNAMIC RANGE .............................................. 25 TEMPORAL NOISE............................................. 25 OPERATION ...................................................... 28 INITIALIZATION (STANDBY MODE)....................... 28 STANDBY MODE ............................................... 28 OUTPUT TRISTATE............................................ 28 READOUT ORDER ............................................. 28 READOUT SPEED.............................................. 29 INTERNAL BIAS CURRENT CONTROL .................. 30 TIMING ............................................................... 31 START OF ROW READOUT (SOF) ...................... 31 HORIZONTAL DATA SYNC (VCLK) ..................... 31 DATA VALID (HCLK)......................................... 31 STROBE SIGNAL ............................................... 33 Example Timing Summary:........................ 35 I2C-COMPATIBLE SERIAL INTERFACE.......... 36 KAC-1310 I2C BUS PROTOCOL ........................ 37 START SIGNAL................................................ 37 SLAVE ADDRESS TRANSMISSION ....................... 37 ACKNOWLEDGMENT .......................................... 37 DATA TRANSFER .............................................. 37 STOP SIGNAL ................................................... 37 REPEATED START SIGNAL............................... 38 I2C BUS CLOCKING AND SYNCHRONIZATION ....... 38 REGISTER WRITE ............................................. 38 REGISTER READ............................................... 38 REGISTER LIST REFERENCE ......................... 41 DETAILED REGISTER BLOCK ASSIGNMENTS ............................................................................ 44 COLOR GAIN REGISTERS 00H 03H.................. 44 REFERENCE VOLTAGE ADJUST REGISTERS (0AH, 0BH)................................................................. 46 POWER CONFIGURATION REGISTERS (0CH) ....... 47 RESET CONTROL REGISTER (0EH)..................... 48 EXPOSURE GAIN A REGISTER (10H) .................. 49 TRISTATE CONTROL REGISTER (12H)................. 49 COLUMN DOVA DC REGISTER (20H) ................ 51 EXPOSURE GAINB (21H) ................................... 52 PGA GAIN MODE (22H)..................................... 53 ADC DOVA (23H)............................................ 54 CAPTURE MODE CONTROL (40H) ....................... 55 SUB-SAMPLE CONTROL (41H) ............................ 56 TRIGGER AND STROBE CONTROL REGISTER (42H)................................................................ 57 PROGRAMMABLE WINDOW OF INTEREST (WOI) (45H-4CH)......................................................... 58 INTEGRATION TIME CONTROL (4EH 4FH) ........ 61 PROGRAMMABLE VIRTUAL FRAME (50H 53H) .. 62 SOF AND VCLK DELAY REGISTERS (54H AND 55H) ........................................................................ 64 SOF & VCLK WIDTH REGISTER (56H) .............. 65 READOUT DIRECTION REGISTER (57H)............... 66 INTERNAL TIMING CONTROL REGISTERS (5FH AND 60H) ................................................................. 67 CLAMP CONTROL AND HCLK DELAY REGISTER (64H)................................................................ 68 ENCODED SYNC REGISTER (65H)...................... 69 MOD64 COLUMN OFFSET CORRECTION REGISTER (80H-BFH)......................................................... 70 STORAGE AND HANDLING ............................. 71 MECHANICAL DRAWINGS .............................. 73
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QUALITY ASSURANCE AND RELIABILITY.... 75 ORDERING INFORMATION.............................. 76 AVAILABLE PART CONFIGURATIONS ................... 76 Table 3 continued. Electro-Optical Characteristics ............................................................................ 22 Table 4: Absolute Maximum Ratings.................. 26 Table 5: Recommended Operating Conditions .. 26 Table 6: DC Electrical Characteristics................ 27 Table 7: Power Dissipation................................. 27 Table 8: Pixel Data Bus and Sync Timing Specification ....................................................... 32 Table 9: I2C-compatible Serial Interface Timing Specification ....................................................... 40 Table 10. I2C Address Range Assignments ....... 41 Table 11: I2C Address Assignments (0h- 3Fh) .... 42 Table 12: I2C Address Assignments (40h - FFh) . 43 Table 13: PGA Color 1 Gain Register (00h)........ 44 Table 14: PGA Color 2 Gain Register (01h)........ 45 Table 15: PGA Color 3 Gain Register (02h)........ 45 Table 16: PGA Color 4 Gain Register (03h)........ 45 Table 17: Negative Voltage Reference Register (0Ah).................................................................... 46 Table 18: Positive Voltage Reference Register (0Bh).................................................................... 46 Table 19: Power Configuration Register (0Ch) ... 47 Table 20: Reset Control Register (0Eh) .............. 48 Table 21: A Exposure Gain A Register (10h)...... 49 Table 22: Tristate Control Register (12h)............ 50 Table 23: Column DOVA DC Offset (20h) .......... 51 Table 24: Exposure Gain B (21h)........................ 52 Table 25: PGA Gain Mode (22h)......................... 53 Table 26: ADC DOVA Register (23h).................. 54 Table 27: Capture Mode Register (40h).............. 55 Table 28: Sub-Sample Control Register (41h).... 56 Table 29: TRIGGER and STROBE Control Register (42h)...................................................... 57 Table 30: WOI Row Pointer MSB Register (45h) 58 Table 31: WOI Row Pointer LSB Register (46h). 58 Table 32: WOI Column Pointer MSB Register (49h) ............................................................................ 59 Table 33: WOI Column Pointer LSB Register (4Ah) ............................................................................ 59 Table 34: WOI Row Depth MSB Register (47h) . 59 Table 35: WOI Row Depth LSB Register (48h) .. 60 Table 36: WOI Column Width MSB Register (4Bh) ............................................................................ 60 Table 37: WOI Column Width LSB Register (4Ch) ............................................................................ 60 Table 38: Integration Time MSB Register (4Eh) . 61 Table 39: Integration Time LSB Register (4Fh) .. 61 Table 40: Virtual Frame Row Depth MSB (50h) . 62 Table 41: Virtual Frame Row Depth LSB (51h) .. 62 Table 42: Virtual Frame Column Width MSB (52h) ............................................................................ 63 Table 43: Virtual Frame Column Width LSB (53h) ............................................................................ 63 Table 44: SOF Delay Register (54h)................... 64 Table 45: VCLK Delay Register (55h)................. 64 Table 46: SOF & VCLK Width Register (56h)..... 65
TABLE OF FIGURES
Figure 1. Pinout Diagram...................................... 6 Figure 2: KAC-1310 Pin Connection Schematic .. 7 Figure 3: KAC-1310 Block Diagram ..................... 8 Figure 4: Optional Bayer RGB Pattern CFA....... 11 Figure 5: Optional Bayer CMY Pattern CFA....... 11 Figure 6: Increase of sensitivity due to microlenses ............................................................................ 11 Figure 7: WOI Definition ..................................... 12 Figure 8: Virtual Frame Definition....................... 13 Figure 9: RGB Bayer 1/2 x 1/2 Sub-sample Example. Sub-sample Control Register(41h) = xxx10101b . 13 Figure 10: Conceptual block diagram of CDS .... 16 Figure 11: FRC Conceptual Block Diagram ....... 16 Figure 12: PGA Gain Modes .............................. 18 Figure 13: Color Gain Register Selection........... 19 Figure 14: KAC-1310 Typical Monochrome Spectral Response ............................................. 23 Figure 15: KAC-1310 Typical Bayer RGB Spectral Response............................................................ 23 Figure 16: KAC-1310 Typical Bayer CMY Spectral Response............................................................ 24 Figure 17: Dynamic Range with respect to Mclk Frequency........................................................... 25 Figure 18: Temporal Noise Dependence on External Resistor ................................................ 25 Figure 19: Power Consumption Dependence on External Resistor ................................................ 30 Figure 20: CFRS Default Frame Sync Waveforms ............................................................................ 31 Figure 21: CFRS Default Row Sync Waveforms 32 Figure 22: Single Frame Capture Mode (SFRS) 32 Figure 23: Pixel Data Bus Timing Diagram ........ 33 Figure 24: STROBE Output Waveforms ............ 34 Figure 25: I2C Bus WRITE Cycle........................ 36 Figure 26: I2C Bus READ Cycle ......................... 39 Figure 27: I2C Bus Timing................................... 40 Figure 28: Recommended Reflow Soldering System Thermal Profile ...................................... 72 Figure 29: 48-Pin Terminal Ceramic Leadless Chip Carrier (Bottom View) ......................................... 73 Figure 30: CLCC-IB package vertical Dimensioning ...................................................... 74
LIST OF TABLES
Table 1: KAC-1310 Pin Definitions ....................... 6 Table 2. Video Encoded Signal Definitions ........ 12 Table 3. Electro-Optical Characteristics ............. 21
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Table 47: Readout Direction Register (57h)........ 66 Table 48: Internal Timing Control Register (5Fh) 67 Table 49: Internal Timing Control Register (60h) 67 Table 50: Clamp Control and HCLK Delay Register (64h)...................................................... 68 Table 51: Encoded Sync Register (65h) ............. 69 Table 52: Mod64 Column Offset Correction Register (80h-BFh)............................................... 70 Table 53: 48 Ceramic LCC - Matrix Format....... 74
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
SUMMARY SPECIFICATION
KODAK KAC-1310 SXGA CMOS IMAGE SENSOR 1280 (H) x 1024 (V)
Parameter
Total Number of Pixels Number of Effective Pixels Number of Active Pixels Pixel Size Imager Size Chip Size
Value
1296 (H) x 1046 (V) 1288 (H) x 1032 (V) 1280 (H) x 1024 (V) 6.0 m (H) x 6.0 m (V) 7.68 mm (H) x 6.14mm (V) (~1/2") 14.22 mm (H) x 14.22 mm (V) 40% mono / 64% color 5:4 40,000 electrons 46% peak CMY 1.2 V/Lux-sec peak CMY 70 e- rms 6250 e-/pixel/sec
o 9C
Features SUMMARY SPECIFICATION
* * * * * * * * * * * * * * * * * * * 5 *
Optical Fill-Factor Aspect Ratio Saturation Signal Quantum Efficiency Responsivity Total Dark Noise Dark Current Dark Current Doubling Temperature Dynamic Range
1/2" Color SXGA Advanced CMOS Image Sensor 1280 x 1024 active imaging pixels - progressive scan Monochrome or Bayer (RGB or CMY) Color Filters 6.0m pitch square pixels with microlenses Kodak patented pinned photodiode architecture; high blue QE, low dark current, lag free High sensitivity, quantum efficiency, and charge conversion efficiency True Correlated Double Sampling for low read noise Low fixed pattern noise and wide dynamic range Antiblooming control and Continuous variable speed rolling electronic shutter Single 3.3V power supply; Single master clock Digitally programmable via I2C-compatible interface
>54dB 200x
Pixel addressability to support `Window of Interest' Blooming Suppression windowing, resolution, and sub-sampling External sync signal for use with strobe flash On-chip 20x programmable gain for white balance and exposure gain 10-bit, pipelined algorithmic RSD ADC 15 fps full SXGA at 20MHz Master Clock Rate 48 pin CLCC package Dark reference pixels with automatic Frame Rate Dark Clamp Encoded Sync data stream Column offset correction circuitry
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS PIN DEFINITIONS
42 41 40 39 38 37 36 35 34 33 32 31 30
0.205" (5.21mm) Row 0 0.002" (52um) 0.280" (7.11mm)
43
0.205" (5.21mm)
Legend: P = VDD G = VSS I = Input O = Output D = Digital A = Analog
44
45
0.016" (400um)
46
47
48
Column 0 Die Center Die Placement position tolerance 100um (4mil)
(0,0)
6 7 8 9
10 11 12 13 14 15 16 17 18
Figure 1. Pinout Diagram
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 19 21 22 23 Pin Name INIT VDD VSS VSSA VDDA CFRCA CFRCB TST_VRO TST_VSO TST_VRI TST_VSI VSSA VDDA CVREFP CVAGA VAGRET CVAGB EXTRESA NC VSSA VDDA Analog Ground Analog Power Pixel Row 1046./1047 Inj Bbias In G P I A A 0V 3.3 V 3.3 V Description Sensor Initialize Digital Power Digital Ground Analog Ground Analog Power Frame Rate Clamp Capacitor A Frame Rate Clamp Capacitor B Analog Test Reference Output Analog Test Signal Output Analog Test Reference Input Analog Test Signal Input Analog Ground Analog Power ADC Bottom Bias Ref Capacitor ADC Top Bias Ref Capacitor Common Mode Capacitor Input Return for VAG external caps Common Mode Reference Capacitor External Bias Resistor External Bias Resistor Pin Power Type I P G G P O O O O I I G P O O O O O I I A A A A A A A A A 0.1F 39k 39k 0V 3.3 V 0.1F 0.1F 0.1F D D D A A A A 3.3 V 0V 0V 3.3 V 0.1F 0.1F Value Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name VDD_PIX VSSA VSS VDD SCLK SDATA PIX0 PIX1 PIX2 PIX3 PIX4 VDD VSS PIX5 PIX6 PIX7 PIX8 PIX9 MCLK VCLK HCLK TRIGGER STROBE SOF
2
Description Pixel Array Power Analog Ground Digital Ground Digital Power I2C Serial Clock Line I C Serial Data Line Output Bit 0=110 Weight Output Bit 1=210 Weight Output Bit 2=410 Weight Output Bit 3=810 Weight Output Bit 4=1610 Weight Digital Power Digital Ground Output Bit 5=3210 Weight Output Bit 6=6410 Weight Output Bit 7=12810 Weight Output Bit 8=25610 Weight Output Bit 9=51210 Weight Master Clock = Pixel Rate Line Sync Pixel Sync Sensor Trigger Signal External Sync for Strobe Flash Start of Frame Sync
Pin Power Type P G G P I/O I/O O O O O O P G O O O O O I O O I O O A A D D D D D D D D D D D D D D D D D D D D D D
19
20
5
21
4
0.280" (7.11mm)
22
3
23
2
24
1
25
Optical Center
26
27
28
29
Value 3.3 V 0V 0V 3.3 V 3.3k 3.3k
3.3 V 0V
14 CVREFM
20 EXTRESB
24 TST_INJ
Table 1: KAC-1310 Pin Definitions
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
ANALOG VDD
Ferrite
0.1uF 0.01uF 0.001uF 0.001uF 0.01uF 0.1uF
Ferrite
DIGITAL VDD
GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
INIT VDD VSS VSSA VDDA CFRCA CFRCB TST_VRO TST_VSO TST_VRI TST_VSI VSSA VDDA
SOF STROBE TRIGGER HCLK VCLK MCLK PIX9 PIX8 PIX7 PIX6 PIX5 VSS VDD PIX4 PIX3 PIX2 PIX1 PIX0 SDATA SCLK VDD VSS VSSA VDD_PIX
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
GND
0.1 uF 0.1 uF
0.1 uF 0.1 uF 0.1 uF 0.1 uF
39K ohm
CVREFM 15 CVREFP 16 CVAGA 17 VAGRET 18 CVAGB 19 EXTRESA 20 EXTRESB 21 TST_BGV 22 VSSA 23 VDDA 24 TST_INJ
GND
GND
Figure 2: KAC-1310 Pin Connection Schematic
Recommended Hardware for KAC-1310 Sensor Evaluation:
1. Kodak Evaluation Board and cable (for parts list and pricing contact our Sales Office @ http://www.kodak.com/go/imagers) 2. National Instruments Framegrabber PCI-1422 LVDS (http://www.ni.com) 3. Calibre I2C Adapter PCI93 LV (http://www.calibreuk.com) 4. Windows NT, 98 or 2000 Operating System.
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS DEVICE DESCRIPTION
TEST TEST TEST TEST TEST TEST
8
9
10
11
21
24
1296
2Dark + 4Isolation
SOF 48 VCLK 44 HCLK 45 STROBE 47 TRIGGER 46 INIT
Row Decoder and Drivers
Master Row Sequencer, Integration Control, and Timing Generator
4Dark + 4Isolation
1024
1
1046
SXGA ACI Image Sensor Array
1280
4Dark + 4Isolation
31 32
PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 PIX6 PIX7 PIX8 PIX9
MCLK 43
1 0
12Dark + 4Isolation
01
33 34 35 38 39 40
Column Sequencer & Drivers
Column Decode, Sensing, CDS, and Muxing
-
3.10 8.76 dB
-
6.38 17.49 dB
CFRCA CFRCB
6 7
Frame Rate Clamp
Column DOVA
1.5x 3.5dB
WB PGA 0.70 2.74x 6
Exposure PGA A&B 0.48 7.49x
41
Global Dova
2.0x 6dB
10 Bit RSD Pipelined ADC
42
CVREFM 14 CVREFP 15 EXTRESA
19
EXTRESB 20
Bandgap Reference and Bias Generation
6 6
Mux and Color Sequencer
6
6
6
6
6
I2C Serial Interface and Register Decode
30 SDATA 29 SCLK
16
CVAGA
17
VAGRET
18
CVAGB
3
VSS
4
VSSA
12
VSSA
22
VSSA
26
VSSA
27
VSS
37
VSS
36
VDD
28
VDD
2
VDD
5
VDDA
13
VDDA
23
VDDA
25
VDD_PIX
Figure 3: KAC-1310 Block Diagram
The KAC-1310 is a solid state CMOS Active CMOS Imager (ACITM) that integrates the functionality of complete analog image acquisition, digitizer, and digital signal processing system on a single chip. The image sensor comprises a SXGA format pixel array with 1280x1024 active elements. The image size is fully programmable to user-defined windows of interest. The pixels are on a 6.0m pitch. High sensitivity and low noise are a characteristic of the pinned photodiode2 architecture utilized in the pixels. The
sensor is available in a Monochrome version without microlenses, or Bayer (RGB or CMY) patterned Color Filter Arrays (CFAs) with standard microlenses to further enhance sensitivity. Integrated timing and programming controls allow video or still image capture progressive scan modes. Frame rates are programmable while keeping the Master Clock frequency constant. User programmable row and column start/stop allow windowing down to a 1x1 pixel window for
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
digital zoom of a panable viewport. Subsampling provides reduced resolution while maintaining constant field of view. The analog video output of the pixel array is processed by an on-chip analog signal pipeline. Correlated Double Sampling (CDS) eliminates the pixel reset temporal and pattern noise. The Frame Rate Clamp (FRC) enables real time optical black level calibration and offset correction. The programmable analog gain consists of exposure/global gain to map the signal swing to the ADC input range, and white balance gain to perform color balance in the analog domain. The ASP signal chain consists of (1) Column op-amp (1.5x fixed gain); (2) Column DOVA(1.5x fixed gain); (3) White Balance PGA (0.70 2.74x); (4) 7.50x); and (5) Global DOVA Global PGA (0.48 (2.0x fixed gain). These Digitally Programmable Amplifiers (DPGAs) allow real time color gain correction for Auto White Balance (AWB) as well as exposure gain adjustment. Offset calibration can be done on a per column basis and globally. This per-column offset correction can be applied by using stored values in the on chip registers. A 10-bit Redundant Signed Digit (RSD) ADC converts the analog data to a 10-bit digital word stream. The fully differential analog signal processing pipeline serves to improve noise immunity, signal to noise ratio, and system dynamic range. The sensor uses an industry standard two-line I2C-compatible serial interface. It operates with a single 3.3V power supply with no additional biases and requires only a single Master Clock for operation up to 20 MHz. It is housed in a 48 pin ceramic LCC package. The KAC-1310 is designed taking into consideration interfacing requirements to standard video encoders. In addition to the 10 bit Bayer (RGB or CMY) encoded data stream, the sensor outputs the valid frame, line, and pixel sync signals needed for encoding. The sensor interfaces with a variety of commercially available video image processors to allow encoding into various standard video formats. In addition, the 3 sync signals can be integrated into the video data stream eliminating the need of the 3 sync outputs The KAC-1310 is an elegant and extremely flexible single chip solution that simplifies a system designer's tasks of image sensing, processing, digital conversion, and digital signal processing to a high performance, low cost, low power IC. It supports a wide range of low-power, portable, consumer digital imaging applications.
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Pixel Architecture
The KAC-1310 sensor comprises a 1280x1024 active pixel array and supports progressive readout. The basic operation of the pixel relies on the photoelectric effect where, due to its physical properties, silicon is able to detect photons of light. The photons generate electron-hole pairs in direct proportion to the intensity and wavelength of the incident illumination. The application of an appropriate bias allows the user to collect the electrons and meter the charge in the form of a useful parameter such as voltage. The pixel architecture is based on a "four transistor" (4T) Advanced CMOS ImagerTM1 pixel which requires all pixels in a row to have common Reset, Transfer, and Row Select controls. In addition all pixels have common supply (VDD) and ground (VSS) connections. This optimized cell architecture provides enhancements such as noise reduction, fill factor maximization, and antiblooming. The use of pinned photodiodes2 and proprietary transfer gate devices in the photoelements enables enhanced sensitivity in the entire visual spectral range and a low lag operation. The nominal photo-responses of the KAC-1310 are shown in Figure 14 (monochrome sensor without microlenses), Figure 15 (Bayer RGB sensor with microlenses) and Figure 16 (Bayer CMY sensor with microlenses). In addition to the imaging pixels, there are additional pixels called dark and isolation pixels at the periphery of the imaging section (see Figure 3). The dark pixels are covered by a light blocking shield rendering the pixels underneath insensitive to photons. These pixels provide the sensor means to measure the dark level offset which is used downstream in the signal processing chain to perform auto black level calibration. The isolation pixels are provided at the array's periphery to eliminate inexact measurements due to light piping into the dark pixels adjacent to active pixels and for extra pixels needed for color interpolation algorithms. Electronic shuttering, also known as electronic exposure timing in photographic terms, is a standard feature. The pixel integration time can be widely varied from a small fraction of a given frame readout time to the entire frame time.
1 2
Advanced CMOS Imager (ACI) is a Kodak trademark Patents held jointly by Kodak and Motorola
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Color Filters and Lenslets
The KAC-1310 family is offered with the option of monolithic polymer color filter arrays (CFA's). The combination of an extremely planarized process and proprietary color filter technology results in CFA's with superior spectral and transmission properties. It is available in Bayer RGB (Figure 4) or CMY (Figure 5) patterns. The complimentary Bayer CMY array provides a 50% increase in sensitivity over primary RGB pattern and are often the best choice for low light applications. This is due to the higher quantum efficiency (QE) and larger wavelength spread per color. If the application is utilizing a color correction matrix, then this matrix will automatically convert the CMY to RGB. Other wise a simple matrix must be applied to affect the conversion from CMY to RGB space. lenslet arrays can improve the fill factor (aperture ratio) of the sensor by approximately 1.6x depending on the F-number of the lens used in the camera system. Microlenses yield the greatest benefits when the main lens has a high F-number or a highly telecentric design. The fill factor of the pixels without microlenses is ~40%.
Incident Light Microlenses
col row
0
G1 B G1 B
1
R G2 R G2
2
G1 B G1 B
3
R
Active Photodiode Area
Figure 6: Increase of sensitivity due to microlenses
0
Frame Capture Modes
G2 R G2
1
There are two frame capture modes: 1) Continuous Frame Rolling Shutter (CFRS) 2) Single Frame Rolling Shutter (SFRS) The sensor can be put into either one of these modes by writing either "1" or "0" to cms bit (bit 6) of Capture Mode Control Register (40h) (Table 47 on page 66).The KAC-1310 uses a progressive readout mode. Progressive scanning refers to non-interlaced or sequential row-by-row scanning of the entire sensor in a single pass. The image readout happens at one instant of time.
Figure 4: Optional Bayer RGB Pattern CFA
col row
3
2
0
C Y2 C Y2
1
Y1 M Y1 M
2
C Y2 C Y2
3
Y1 M Y1 M
0
Continuous Frame Rolling Shutter Capture Mode (CFRS)
The default mode of image capture is the Continuous Frame Rolling Shutter Capture Mode (CFRS). In this mode the TRIGGER input pin is ignored. This mode is most suitable for full motion video capture and will yield SXGA sized Frame Rates up to 15 FPS at 20 MHz MCLK and VGA frames at >30 FPS. In this mode the image integration and row readout take place in parallel. While a row of pixels is being readout, another row or rows are being integrated. Since the integration time (Tint) must be equal for all rows, the start of integration for rows is staggered.
Figure 5: Optional Bayer CMY Pattern CFA
Applications requiring higher sensitivity can benefit from the microlens arrays shown in Figure 6. The
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2
1
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS CFRS Video Encoded Data Stream
The Encoded Sync Control Register (65h ) (Table 51 on page 69) allows the user to select how the output pixel data stream in CFRS mode is encoded/formatted. In default mode, internally generated signals SOF, VCLK, HCLK etc. drive the integration and readout of the pixel data frames, but only the valid pixel data is readout of the sensor. When a "1" is written to bit 5, it causes the output pixel data to be encoded with four (4) 10-bit pixel codes at the beginning of each line for SOF, VCLK and End Of Frame (EOF) signals. Operation in this mode will allow a camera system to capture streaming video and re-construct the frame afterwards when the SOF, VCLK, and HCLK signals are no longer available. The Video Encoded Signal Definitions, (Table 2), defines the four (4) 10-bit pixel code data that represents the SOF, VCLK, and EOF signals.
Signal SOF Description Data
that can be found in register 42h, Table 29 on page 53. The TRIGGER signal can be generated internally by the sensor or be driven via Pin #46 of the sensor. To set whether the signal is generated internally or externally, along with other setting of this signal, refer to TRIGGER and STROBE Control register (42h), Table 29 on page 53.
Window of Interest (WOI) Control
The pixel data to be read out of the device is defined as a `Window of Interest' (WOI). The window of interest can be defined anywhere on the pixel array at any size. The user provides the upper-left pixel location and the size in both rows and columns to define the WOI. The WOI is defined using the WOI Pointer, WOI Depth, and WOI Width registers, (Table 30 on page 58 through Table 37 on page 60). Please refer to Figure 7 for a pictorial representation of the WOI within the active pixel array. Any pixels not included in the WOI will be skipped over and never readout (note: the minimum valid values are 2 for the WOI row pointer (wrp), and 0 for the WOI column pointer (wcp)). The first pixel readout will always be the first pixel of the WOI.
0 0 1295
Start of Row [3FF][3FF][3FF][3FF] readout (i.e. Readout of Row Note: 3FFh = 1023d 1) 000h = 0d Start of Row readout of Rows 2+ Readout of last Row complete [3FF][3FF][000][000]
VCLK
EOF
[000][000][000][000]
Table 2. Video Encoded Signal Definitions
ACTIVE PIXEL ARRAY
WOI Pointer (wcp,wrp)
Single Frame Rolling Shutter capture mode (SFRS)
In this mode of capture, the start of integration is triggered by the TRIGGER signal. Similar to the CFRS capture mode, readout of each row follows the integration of that row. The imager can be placed in SFRS capture mode using register 40h (see Table 27 on page 55). In this mode the imager will remain idle until the TRIGGER pin is pulled high. The imager then begins integration followed by image readout. If the TRIGGER input is still high when the SFRS Frame is finished reading out, then a second Frame is started. Detailed timing can be found in Figure 24 on page 34. There are additional controls for SFRS mode
Window of Interest (WOI)
WOI Column Depth (wcd)
1047
Figure 7: WOI Definition
Sub-Sampling Control (Resolution)
The WOI can be sub-sampled in either monochrome or color pixel space in both the horizontal and vertical direction independently.
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WOI Row Depth (wrd)
IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
The resolution of each axis can be set to four different sampling rates: full, 1/2, 1/4, or 1/8. Subsampling the imager by 1/4 in both horizontal and vertical directions results in only 1/16 of the pixels being readout. The frame readout rate can therefore be increased by 16x. The user controls the sub-sampling via the Sub-Sample Control Register (41h), Table 28 on page 56. An example of RGB Bayer space sub-sampling is shown in Figure 9. If the imager is set as a color imager then the sub-sampling is done by reading out two cols/rows and then skipping two. This prevents the sub-sampling from breaking up a color kernel. If the imager is set to Monochrome mode the subsampling will skip every other col/row performing a more uniform reduction is resolution. Activating Sub-Sampling alone will not increase the Frame Rate. The Frame Rate is controlled by the Virtual Frame (see "Virtual Frame (VF)"). For example, if Sub-Sampling is first turned on to 1/8 x 1/8 mode, the WOI will shrink by 1/64. To keep the Frame Rate constant, the KAC-1310 fills in the rest of the rows and columns with blanking pixels. The Virtual Frame can now be reduced by 1/8 x 1/8 to take advantage of the Sub-Sampled WOI. The Frame Rate will now have increased by 64x with no compromise to the field of view (in CFRS mode).
G B G B G B G B G B G B R G R G R G R G R G R G G B G B G B G B G B G B R G R G R G R G R G R G G B G B G B G B G B G B R G R G R G R G R G R G G B G B G B G B G B G B R G R G R G R G R G R G G B G B G B G B G B G B R G R G R G R G R G R G G B G B G B G B G B G B R G R G R G R G R G R G
vrd[13:0]
WOI Column Depth (wcd)
Virtual Frame (VF)
Changing the WOI does not change the Frame Rate of the imager. This is done by varying the size of a Virtual Frame surrounding the WOI. Refer to Figure 8 for a pictorial description of the Virtual Frame and its relationship to the WOI. The VF is a method for defining the horizontal and vertical blanking (over clocking) in Frame Readout. As the WOI is adjusted, the total Frame Size is set by the VF. To maintain constant Frame Rate, the KAC-1310 adjusts the number of blanking pixels to account for changes in the WOI. The VF can be set to any size. If the VF is greater than the WOI then the readout is padded with blanking pixels (invalid dark pixels). The WOI and the VF may both be larger than the actual imager size. In this case the WOI is also padded with blanking pixels (invalid dark pixels). Figure 8 illustrates a WOI smaller than the VF. If the WOI is set larger than the VF, then the WOI will be clipped by the VF and the Frame Rate will still be equal to the VF size.
0 0 WOI Pointer (wcp,wrp)
vcw[13:0]
Window of Interest (WOI)
Blanking Rows
Virtual Frame
Figure 8: Virtual Frame Definition
Integration Time
Figure 9: RGB Bayer 1/2 x 1/2 Sub-sample Example.
Sub-sample Control Register(41h) = xxx10101b
CFRS Integration Time
The Integration Time in CFRS is defined and quantized by the time to read out a single row. Once a Virtual Frame has been defined, the time to read out one row can be calculated. Any integer multiple of the Row Time (Trow) can be selected. The number of Row Times desired for integration time is programmed into the Integration Time
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Blanking Columns
WOI Row Depth (wrd)
IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Registers. The Integration Time is defined by a combination of the width of the VF and the Integration Time Registers (4Eh and 4Fh), (Table 38 and Table 39 on page 61); and can be expressed as: Integration Time (Tint) = (cintd + 1) * Trow where cintd is the number of virtual frame row times desired for integration time. Therefore, the integration time can be adjusted in steps of VF row times. Row Time (Trow) = (vcwd+shAd+shBd+19) * MCLKperiod If the integration time is programmed to be larger than the VF then it will be truncated to the number of rows in the VF. The VF must be increased before the Integration Time can be increased further. NOTE: The upd bit of Reg 4Eh is used to indicate a change to cint[13:0]. Since multiple I2C writes may be needed to complete desired frame to frame integration time changes, the upd bit signals that all desired programming has been completed, and to apply these changes to the next frame captured. This prevents undesirable changes in integration time that may result from I2C writes that span the "End of Frame" boundary. This upd bit has to be toggled from its previous state in order for the new value of cint[13:0] to be accepted/updated by the sensor and take effect. i.e. If its previous state is "0", when writing a new cint value, first write cint[7:0] to register 4Fh, then write both cint [13:8] and "1" to the upd bit to register 4Eh. The upd bit should be sent as close to the Start of Frame as possible to ensure a smooth transition from the old integration time to the new. where cintd is the number of virtual frame row times desired for integration time. Note: In CFRS operation, the integration time is limited (clipped) by the readout time (which is also the Frame Time). In SFRS mode, the Frame Time is expanded to include any programmed integration time. Thus in SFRS operation there is no boundary to the integration time.
Frame Rate
The Frame Rate can be defined as the time required to readout an entire frame of data plus the required blanking time. There is a different relationship between the Frame Rate and Virtual Frame for CFRS and SFRS mode operation.
CFRS Frame Rate
In CFRS, the Frame Rate of the imager is controlled by varying the size of the Virtual Frame surrounding the WOI, and is independent of Integration Time. Refer to Figure 8 for a pictorial description of the Virtual Frame (VF) and its relationship to the WOI. In CFRS operation, the Frame Rate (FR) (Frame Rate = 1/Frame Time) is defined by the VF size and clock speed (MCLK). The Frame Time (FT) and can be expressed as: FT =(vrdd +1) * Trow where vrdd defines the number of rows in the virtual frame. The user controls vrdd via the Virtual Frame Row Depth registers (Table 40 and Table 41 on page 62). If the VF width (vcwd) is <1296, then the timing block holds the two Frame Rate Clamp (FRC) rows to a length of 1296 even while all of the other rows are shorter. This is to ensure enough time for the clamping circuit. If the FRC is turned off (see Clamp Control and HCLK Delay Register (64h), it is recommended that the CFRCA and CFRCB pins be tied to ground directly (i.e. no 0.1 F capacitor). NOTE: The WOI and Integration Time will be clipped by the VF.
SFRS Integration Time
Just as with operation in CFRS mode, the integration time is defined by a number of Row Times. As before: Row Time (Trow) = (vcwd+shAd+shBd+19) * MCLKperiod where vcwd defines the number of columns in the virtual frame. The user controls vcwd via the Virtual Frame Column Width registers (Table 42 and Table 43 on page 63). Integration Time (Tint) = (cintd + 1) * Trow
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS SFRS Frame Rate
There are two main differences when running in SFRS mode versus CFRS mode. The first is that the Frame Rate is no longer the readout rate. In SFRS mode there is no overlap of the Integration and the readout. Therefore, at the top of each Frame, Integration must first occur then readout. The Frame Rate is now Integration plus readout. The second major difference is the length of readout. In CFRS mode, the only reason for making the VF length larger than the WOI length (vrd > wrd) is to add vertical blanking rows to control the time between frames. In SFRS mode, the time between frames is controlled by the TRIGGER input pin, and therefore vertical blanking serves no purpose. Rather than have the user change the VF depth (vrd), the imager uses the WOI depth (wrd). Therefore, the Frame Rate equations are: Frame Time (Tframe) = Integration Time (Tint)+ Readout Time (Trd) Where: Integration Time (Tint) = (cintd + 1) * Trow Readout Time (Trd) = Trow * (wrdd+1) Row Time (Trow) = (vcwd+shAd+shBd+19) * MCLKperiod Frame Rate = 1/Frame Time
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS ANALOG SIGNAL PROCESSING CHAIN (ASP)
The KAC-1310's analog signal processing (ASP) chain incorporates Correlated Double Sampling (CDS), Frame Rate Clamp (FRC), two Digitally Programmable Gain Amplifiers (DPGA), Offset Correction (DOVA), and a 10-bit Analog to Digital Converter (ADC). See Figure 3 for a block diagram of the ASP chain.
Cap FRCA 0.1F
CFRCA
VCM
+ FRCLMP +
FRCLMP
1x
FRCLMP
Previous Stage
-
BUF
VCM
+
-
Diff
FRCLMP
V+ V-
Correlated Double Sampling (CDS)
The uncertainty associated with the reset action of a capacitive node results in a reset noise which is proportional to kTC; `C' being the capacitance of the node, `T' the temperature, and `k' the Boltzmann constant. A common way of eliminating this noise source in all image sensors is to use Correlated Double Sampling. The output signal is sampled twice, once for its reset (reference) level and once for the actual video signal. These values are sampled and held while a difference amplifier subtracts the reference level from the signal output. Double sampling of the signal eliminates correlated noise sources.
S&H Reset
FRCLMP
1x
FRCLMP
-
BUF
VCM
Cap FRCB 0.1F
CFRCB
Figure 11: FRC Conceptual Block Diagram
Pixel Output
S&H Signal
+
-
Diff OpAmp
V+ V-
Figure 10: Conceptual block diagram of CDS
processed and held to establish pixel reference level at the CFRCA and CFRCB pins. During this period, the FRC's differential outputs (V+ and V- on the Diff Amp) shown in Figure 11 are clamped to Vcm. Together, these actions help to eliminate the dark level offset, simultaneously establishing the desired zero code at the ADC output. The user can disable the FRC via the Clamp Control and HCLK Delay Register (64h), (Table 50 on page 68) which allows the ASP chain to drift in offset. If the FRC is disabled, it is recommended that the CFRCA and CFRCB pins be grounded. Care should be exercised in choosing the capacitors for the CFRCA and CFRCB pins to reflect different Frame Rates. For small WOI or fast Frame Rates, a smaller capacitor may be used.
Frame Rate Clamp (FRC)
The FRC (Figure 11) is designed to provide a feed-forward dark level compensation. In the automatic FRC mode, the optical black level reference is reestablished each time that the image sensor begins a new frame. The KAC-1310 uses optical black (dark) pixels to establish this reference. The dark pixel sample period is automatically controlled internally and it is set to skip the first 3 dark rows and then sample the next 2 dark rows. When "dark clamping" is active, each dark pixel is
Column Digital Offset Voltage Adjust (CDOVA)
A programmable per-column offset adjustment is available on the KAC-1310. There are 64 registers that can be programmed with an offset that is added to each 64th column (Mod64 Column Offset Registers; Table 52 on page 70). Each register is 6 bits, (5 bits plus 1 sign bit), providing 32 register values. This set of 64 values is then repeatedly applied to each bank of 64 columns in the sensor via the column DOVA stage of the ASP chain. In addition to global column column. This the dark level the per-column offset, there is a offset that can be added to every is used to remove any variation of with respect to varying gain. The
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DC offset is loaded as a 6-bit value into the Column DOVA DC Offset Register, (Table 23 on page 51). The Column DOVA stage has only six bits of total range. The value in Register 20h and 80h-BFh are added together prior to application to the column. If the sum is greater than 31, it will be truncated to 31.
Programmable Gain Amplifier (PGA) Gain Modes
Three different gain modes are available when the sensor is performing White Balance and Exposure gain. The gain mode is set using Register 22h described in Table 25, page 53. The three gain modes are: 0 < Regd < 31 32 < Regd < 63 0 < Regd < 47 0 < Regd < 63 (0.0695x (1.3910x (0.695x (0.483x 1.36925x) 2.7395x) 2.7395x) 7.488x)
Raw Gain Mode (WB and Exposure) Gain 0.6950 + 0.02175 * Regd 1.3475 + 0.04350 * (Regd - 31) Lin1 Gain Mode (WB and Exposure) Gain 0.6950 + 0.04350 * Regd Lin2 Gain Mode (Exposure gain stage only) Gain 0.483 + 0.11119 * (Reg 10h)d
Raw Gain Mode:
The three gain stages are each designed as twopiece linear gain stages where the gain increment doubles for the second half of the programmable range. The gain increment is 0.02175 for the first 32 programmable steps, and precisely twice that (0.04350) for the last 32 programmable steps. step of the lower register is skipped, providing 16 uniform gain steps of 0.04350. As a result, the entire gain stage now appears to be a linear gain stage with 48 uniform steps of 0.04350.
Lin2 Gain Mode:
This mode is only available for the exposure gain mode. In this mode, both gain stages are automatically coordinated to affect a single gain stage. The gain step size of Lin2 Mode is almost, but not completely uniform. Any one step may deviate from the mean step size of 0.11119 by a small amount. This is due to the fact that Lin2 Mode actually varies two gain stages with fixed step sizes to make one equivalent gain step.
Lin1 Gain Mode:
Some applications do not need the finer gain increment provided by the Raw Gain Mode in the first 32 register values. In Lin1 mode, every other
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Gain of DPGA for Raw , Lin1, and Lin2 modes 8 7 6 Gain of DPGA Stage 5 4 3 2 1 0 0 5 10 15 Raw Mode (lower range) 20 25 30 35 40 45 50 55 60 Lin1 Raw Mode (upper range) Lin2
DPGA Register Value (Decimal)
Figure 12: PGA Gain Modes
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS White Balance Control PGA (WB Gain)
[For the purposes of illustration, the following discussion assumes a Bayer RGB color pattern; with the appropriate correlation (as shown in Figure 13), the CMY Bayer pattern may be substituted throughout.] The sensor produces three primary color outputs, Red, Green, and Blue. These are monochrome signals that represent luminance values in each of the primary colors. When added in equal amounts they mix to make neutral color. White balancing is a technique where the gain coefficients of the Green1, Red, Blue, and Green2 pixels comprising the Bayer RGB pattern are set so as to equalize their outputs for neutral gray color scenes. Since the sensitivity of the two green pixels in the Bayer pattern may not be equal, an individual color gain register is provided for each component of the Bayer pattern. Once all color gain registers are loaded with the desired gain coefficients, white balance is achieved in real time and in analog space. The appropriate values are selected and applied to the pixel output via a high speed path, the delay of which is much shorter than the pixel clock rate. Real time updates can be performed to any of the gain registers. However, latency associated with the I2C interface should be taken into consideration before changes occur. In most applications, users will be able to assign predefined settings such as daylight, fluorescent, tungsten, and halogen to cover a wide gamut of illumination conditions. Both DPGA designs use switched capacitors to minimize accumulated offset and improve measurement accuracy and dynamic range. The white balance gain registers are 6-bits and can be programmed to allow gain of 0.695x to 2.74x in varying steps depending on which gain mode is selected (RAW or LIN mode). The WB Gain Stage (PGA WB) is a two-segment piecewise Linear gain stage. In Raw Mode this stage produces smaller gain steps for the first half of its gain range, and larger gain steps for second half of its gain range. This allows fine adjustment for color ratios as well as a large gain swing. If the piecewise linear mode is difficult to manage and the fine steps are not required, this gain stage can be placed into Lin1 Mode. In this mode every other gain step is skipped for the first 1/3 of the gain range. This produces the same gain range but with uniform gain steps throughout the range.
C / G1 (0) Y1 / R (1) Y2 / B (2) M / G2 (3)
6 6 6 6
6
DPGA 0.7x- 2.7x
G1(0)
R(1)
C(0)
Y 1(1)
B(2)
G2(3)
Y 2(2)
M(3)
Figure 13: Color Gain Register Selection
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Exposure Gain PGA (Exp Gain A/B)
The Exposure (Global) Gain consists of two Gain stages (A and B) in series. Each of these gain stages has a Raw and Lin1 mode as described in the previous WB Gain section. Thus all colors can be amplified by the value in Exp GainA (reg 10h) and then again by Exp GainB (reg 21h) to compensate for varying exposure of the scene. The easiest way to implement this is to program Exp GainB at unity and then adjust Exp GainA until it is at its maximum of 2.7395x. Then increase the Exp GainB until the final exposure gain is reached. The gains of the two Exp Gain stages are controlled by Registers 10h and 21h, (Table 21 and Table 24 on pages 49 and 52). The Exp Gain Mode is defined in Register 22h, (Table 25 on page 53). The dual gain-stage implementation of the Exp Gain may cause difficulty in some auto-exposure routines; this can be avoided by setting the Exp Gain to Lin2 Mode. In Lin2 Mode, Reg 10h is used to set both gain stages in an attempt to give uniform gain steps across the entire 7.5x range of the two Exp Gain stages. Only one register is used to simplify user programming, and thus the gain step size is increased to ~0.11119 to allow the full range to be accessed by a single 6-bit register. Note that the gain step size is almost but not completely uniform. Any one step may deviate from the mean step size of 0.11119 by a small amount. algorithmic technique is used to yield an ADC with superior characteristics for imaging applications. Integral Noise Linearity (INL) and Differential Noise Linearity (DNL) performance is specified at 1.0 and 0.5, respectively, with no missing codes. The input dynamic range of the ADC is programmed via a Programmable Voltage Reference Generator. The positive reference voltage (VREFP) and negative reference voltages (VREFM) can be programmed from 2.5V to 1.25V and 0V to 1.25V respectively in steps of 5mV via the Reference Voltage Registers (Table 17 and Table 18 on page 46). This feature is used independently or in conjunction with the PGAs to maximize the system dynamic range based on incident illumination. The default input range for the ADC is 1.86V for VREFP and 0.59V for VREFM hence allowing a 10-bit digitization of a 1.3V peak-to-peak signal.
mV 2(V + - V - ) 2(1.86 - 0.59) mV = = = 2.48 10 dn 10dn 1024 1024
If the 20x gain provided by the PGAs is not sufficient, the ADC references can be used to apply additional gain to the ASP. To increase the gain the ADC references need to be moved closer to Vcm (1.25V). This should be used only after the PGAs have been used to their fullest since moving the ADC references too far will degrade the ADC performance. The effective gain of the ADC block will be:
Global Digital Offset Voltage Adjust (GDOVA)
A programmable global offset adjustment is available on the KAC-1310. A user defined offset value is loaded via a 6-bit signed magnitude programming code via the ADC DOVA Register, (Table 26 on page 54). Offset correction allows fine-tuning of the signal to remove any additional residual error, which may have accumulated in the analog signal path. This function is performed directly before analog to digital conversion and allows the user to set the `black' level in the ADC range.
Gain =
2.48
2(V + -V - ) 1024
Ex. If Reg 0Ah=Reg 0BhBAh then the ADC Gain = 2.
Gain =
2.48
2(1.57 - 0.93) 1024
= 1.98
Analog to Digital Converter (ADC)
The ADC is a fully differential, low power circuit. A pipe-lined, Redundant Signed Digit (RSD)
The user should connect 0.1 F capacitors to CVREFP (pin 15) and CVREFM (pin 14) (see Figure 2) to accurately hold the biases.
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS PERFORMANCE Test Conditions
Temperature Operating Frequency Light Source Operation Integration Time Bright Field Condition 25C 10 MHz MCLK White Light LED Nominal Voltages and Default Timing 70 ms 70% Saturation
Imaging Performance
Symbol Nsat QE Parameter Saturation Signal Peak Quantum Efficiency Monochrome no Lens @ 550nm Red Green Blue Cyan Magenta Yellow PRNU S Photoresponse Non-uniformity Responsivity w/Lens @ 650nm w/Lens @ 540nm w/Lens @ 460nm w/Lens @ 530nm w/Lens @ 650nm w/Lens @ 590nm Global Local Monochrome no Lens Red w/Lens Green w/Lens Blue w/Lens Cyan w/Lens Magenta w/Lens Yellow w/Lens Typ 40,000 34 38 37 20 46 45 46 4 1.5 1.11 59,800 0.5 27,100 0.6 32,200 0.32 17,500 1.04 55,800 0.81 43,600 1.2 64,700 Unit electrons % % % % % % % % rms % rms V/lux-sec e-/lux-sec V/lux-sec e-/lux-sec V/lux-sec e-/lux-sec V/lux-sec e-/lux-sec V/lux-sec e-/lux-sec V/lux-sec e-/lux-sec V/lux-sec e-/lux-sec Notes 1 1 1 1 1 1 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Table 3. Electro-Optical Characteristics Notes: 1. Refers to nominal spectral response values as provided in Figures 3, 4, and 5. QE range is +/- 20% 2. For a 100 x 100 pixel region under uniform illumination with output signal equal to 70% of saturation signal. 3. Measurements assume a 3200K source with Hoya CM500 filter. All values referenced at the floating diffusion node. To calculate values at the sensor outputs, on-chip gain stages should be linearly applied to the given values.
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Symbol Id Lag Xab ne- total DR fmax fnom A - X A - Y Parameter Photodiode Dark Current Pixel Charge Transfer Inefficiency Blooming Margin - shuttered light Total System (equivalent) Noise Floor System Dynamic Range Resolution Maximum MCLK Nominal MCLK Acceptance Angle in Horizontal direction Acceptance Angle in Vertical direction Image Array Size Pixel Size Frame Rate Fill Factor Typ 1/4 <1 200x 70 54 10 20 10 15 27 7.7 x 6.1 (~1/2") 6.0 x 6.0 0 - 15 40 / 64 Unit fA/pixel % X Vsat e rms dB bits MHz MHz Degrees Degrees mm m FPS % Notes 4 5 6 7 9, 12, 13 8 9 11 11
10
Table 3 continued. Electro-Optical Characteristics Notes: 4. Measured at sensor temperatures of 25 oC / 40 oC 5. Transfer inefficiency of photosite. 6. Xab represents the increase above the saturation-irradiance level (Vsat) that the device can be exposed to before blooming of the pixel will occur. 7. Includes amplifier noise, dark pattern noise and dark current shot noise at 10 MHz data rates. 8. All performance specs are not guanteed at this speed. 9. All Imager specs are held between 1 MHz and 10 MHz 10. Monochrome sensor without microlens / color sensor with microlens 11. Angle at which Responsivity is reduced by 3dB. 12. DR is defined as the standard deviation of temporal noise divided by the mean signal at saturation. 13. Saturation signal is defined as the maximum sensor output achieved while maintaining < 2% response nonlinearity.
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Quantum Efficiency
40 35 30 25 QE (%) 20 15 10 5 0 350
450
550
650
750
850
950
1050
Wavelength (nm)
Figure 14: KAC-1310 Typical Monochrome Spectral Response
40 35 30 25 20 15 10 5 0 350
BLUE GREEN RED
QE (%)
450
550
650
750
850
950
1050
Wavelength (nm)
Figure 15: KAC-1310 Typical Bayer RGB Spectral Response
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
50 45 40 35 30 QE(%) 25 20 15 10 5 0 350
MAGENTA CYAN YELLOW
450
550
650
750
850
950
1050
Wavelength (nm)
Figure 16: KAC-1310 Typical Bayer CMY Spectral Response
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Dynamic Range
10.0 60
9.5
57
9.0
54
DR wrt 950dnVsat (bits)
8.5
51
8.0
48
7.5
45
7.0
42
6.5
39
6.0 0 5
36
Freq (MHz)
10
15
20
Figure 17: Dynamic Range with respect to Mclk Frequency
Temporal Noise
Temporal Noise (RMS 10dn) 7 6 5 4 3 2 1 0 10 20 30 40 50 60
External Resistance (kOhms)
Figure 18: Temporal Noise Dependence on External Resistor
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dB
IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Symbol VDD Vin Vout IIO IDD DC Supply Voltage DC Input Voltage DC Output Voltage
Parameter
Value -0.5 to 3.8 -0.5 to (VDD + 0.5) -0.5 to (VDD + 0.5) 50 100 -65 to +150 300
Unit V V V mA mA C C
DC Current Drain per Pin, Any Single Input or Output DC Current Drain, VDD and VSS Pins
TSTG Storage Temperature Range TL Lead Temperature (10 second soldering)
Notes: - Voltages referenced to VSS - Maximum Ratings are those values beyond which damage to the device may occur. - VSS = AVSS = DVSS = VSSO (DVSS = VSS of Digital circuit, AVSS = VSS of Analog Circuit) VDD = AVDD = DVDD = VDDO (DVDD = VDD of Digital circuit, AVDD = VDD of Analog Circuit) Table 4: Absolute Maximum Ratings
Symbol VDD TA TJ
Parameter DC Supply Voltage, VDD = 3.3V (Nominal) Commercial Operating Temperature Junction Temperature
Min 3.0 0 0
Max 3.6 40 55
Unit V C C
Notes: * * *
All parameters are characterized for DC conditions after thermal equilibrium has been established. Unused inputs must always be tied to an appropriate logic level, e.g. either VSS or VDD For proper operation it is recommended that Vin and Vout be constrained to the range VSS<(Vin or Vout)< VDD Table 5: Recommended Operating Conditions
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Symbol VIH VIL Iin IOH IOL VOH VOL IOZ IDD
Characteristic Input High Voltage Input Low Voltage Input Leakage Current, No Pull-up Resistor Output High Current Output Low Current Output High Voltage Output Low Voltage 3-State Output Leakage Current Maximum Standby Supply Current
Condition
TA = 0 C to 40 C Min 2.0 -0.3 Max VDD + 0.3 0.8 5
Unit V V A mA mA V 0.2 V A mA
Vin = VDD or VSS VDD = Min, VOH Min = 0.8*VDD VDD = Min, VOL Max = 0.4V VDD =Min, IOH = -100mA VDD = Min, IOL = 100mA Output = High Impedance, Vout = VDD or VSS IOUT = 0mA, Vin = VDD or VSS
-5 -3 3 VDD - 0.2
-10 0
10 15
VDD = 3.3V + 0.3V; VDD referenced to VSS; Ta = 0 C to 40 C Table 6: DC Electrical Characteristics
Symbol PDYN PSTDBY PAVG
Parameter Dynamic Power Standby Power Average Power
Condition 13.5 MHz MCLK Clock frequency STDBY Pin Logic High 13.5 MHz Operation (using STDBY)
Typ 250 25 200
Unit mW mW mW
VDD = 3.0V, VDD referenced to VSS, 25 C
Table 7: Power Dissipation
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS OPERATION
The KAC-1310 includes initialization, standby modes, and external reference voltage outputs to afford the user additional application flexibility. sensor can also be put in the stand by mode via the sby bit ("0") on the Power Configuration Register (OCh) (Table 19, page 47). The registers retain their programmed values and are not reset to default when the power configuration register is used to enter/exit standby mode. The user may also reduce power consumption by placing the KAC-1310's outputs in the tri-state mode. This action may be accomplished by setting the dbt bit on the Power Configuration Register (0Ch). In addition, further power savings can be obtained by increasing the external resistance value (see section 4.6).
Initialization (Standby Mode)
The INIT input (pin 42) controls hardware reinitialization of the KAC-1310. This serves to assure controlled chip and system startup. The chip enters standby mode when INIT is asserted via a logic high input. This state must be held a minimum of 1 ms. The chip remains in low-power mode while in the INIT state. When INIT is removed (logic low), the chip begins initialization. An additional 1 ms "wait period" should be allowed after INIT goes low. This ensures that the start-up routines within the KAC1310 have run to completion, and that all holding and bypass capacitors, etc. have achieved their required steady-state values. Start-up tasks include resetting registers to their default values, resetting all internal counters and latches, and initializing the analog signal processing chain.
Output Tristate
The Tristate Control Register (12h), (Table 22 on page 50) is used to set the chip outputs into tristate. This functionality is useful if these outputs are on a buss that is being shared by other devices. When the tsctl bit is reset (ie "0") the SOF, VCLK, HCLK, and STROBE output pins are placed in tristate mode. The 10 ADC output pins can be tristated by resetting the tspix bit ("0").
Standby Mode
The standby mode option is implemented to allow the user to reduce system power consumption during periods that do not require operation of the KAC-1310. This feature allows the user to extend battery life in low power applications. By utilizing this mode, the user may reduce dynamic power consumption from 400mW (full power, full speed), to <50 mW in the standby mode (note that dynamic power consumption is also reduced in slower conversion speed applications). The standby mode is activated by applying an active high signal to the INIT pin (#42). The
Readout Order
Register 57h (Table 47 on page 66) allows the user to change the direction of readout of the columns or rows. This can be used to compensate for and orientation of the imager in the optical system. The rrc when enabled causes the column data to be readout in the reverse direction as compared to the normal readout direction. The rrr when enabled causes the row data to be readout in the reverse direction as compared to the normal readout direction. The normal readout direction of the imager is shown in Figure 2 on page 7 (ie. bottom-to-top; left-to-right).
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Readout Speed
The imager will hold all specifications from 1 MHz to 10 MHz. The nominal maximum speed is 10 MHz (10FPS). The imager will work well beyond this nominal maximum speed. As the speed increases beyond 10 MHz, the power consumption increases slightly, temporal noise rises linearly resulting in a decrease in dynamic range (see Figure 17), and ADC INL degrades. Severe degradation in sensor performance will occur when operating in excess of 20 MHz. When operating at speeds greater than 10 MHz, it is possible that horizontal banding might occur. This is due to one of the sample and hold stages not settling. If this condition is observed, it can be rectified by widening the SHA and SHB pulses in registers 5Fh (page 67) and 60h (page 67).
Note: this will change the Trow equation given on page 34. Further image improvements can also be obtained by increasing the power of the chip with the external resistor (see "Internal Bias Current Control"). Note: When increasing the SHA and SHB pulses, the SOF Delay ( Register 54h) will need to be increased as well in order to place the syncs back in the same position relative to the first WOI valid pixel.
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Internal Bias Current Control
The ASP chain has internally generated bias currents that result in an operating power consumption of nearly 400mW. By attaching a resistor between pin 19, EX-TRESA; and pin 20, EXTRESB; the user can reduce the power consumption of the device. This feature is enabled by writing a 1b to bit res of the Power Configuration Register (0Ch). Figure 19 depicts the power savings that can be achieved with an external resistor at nominal clock rate (10 MHz). An external resistance (Rext) of 39 k is recommended for optimal sensor performance. Additional power savings can be achieved at lower clock rates.
600 Power Consumption (mW) 500 400 300 200 100 0 10 15 20 25 30 35 40 45 50 55 60 External Resistance(kOhms)
Figure 19: Power Consumption Dependence on External Resistor
Internal Resistor
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS TIMING
The waveforms depicted on the following pages show the output data stream for the KAC-1310 under various operating conditions. The individual SOF, VCLK, and HCLK pulse positions and widths can be moved and inverted using registers 40h (Table 27, page 55), 54h (Table 44, page 63), 55h (Table 45, page 64), 56h (Table 46, page 65), and 64h (Table 50, page 68).
Horizontal Data Sync (VCLK)
This signal triggers the readout of the sequential rows of the frame. This signal is an output and can be read via Pin #44 of the sensor. The VCLK signal delay in relation to SOF, as well as its length can be set via the VCLK Delay Register (Table 45, page 64), and the SOF&VCLK Signal Length Control Register, (Table 46, page 65).
Start of Row Readout (SOF)
This signal triggers the start of the first row readout of the frame. This signal is an output and can be read via Pin #48 of the sensor. The SOF signal delay as well as its length can be set via the SOF Delay Register (Table 44, page 64), and the SOF & VCLK Signal Length Control Register, (Table 46, page 65).
Data Valid (HCLK)
This signal triggers a single active pixel data has been readout (example Column 2 of Row 5 data has been read out). This signal is an output and can be read via Pin #45 of the sensor. The HCLK signal delay can be set via the HCLK Delay Register (Table 50, page 68).
Frame Time = 1064 row times Row Time = 1338 MCLKs WOI = 1280 Columns x 1024 Rows starting at row 16, column 8
SOF VCLK HCLK
row 1037 row 1038 row 1039 row 1037 row 1038 row 1039 row 16 row 17 row 18 row 19 row 16 row 17 row 18 row 19
Figure 20: CFRS Default Frame Sync Waveforms
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
1 2 3 4 5 6 7 8 1 2 3
1 2 3
14 15 1 2 3
SOF
Row Time = vcwd + 39
VCLK HCLK
Pixel Array Values
row 16
105 106 row 17
31 32
MCLK
ADC[9:0]
Valid Pixel Data
Figure 21: CFRS Default Row Sync Waveforms
TRIGGER T = (cintd + 1)*Row Time SOF VCLK
Standard Frame Timing (Figure 18)
HCLK
row 16
row 17
row 18
row 19
row 1037
col 1286 col 1287
row 1038
col 8 col 9
Figure 22: Single Frame Capture Mode (SFRS) Symbol fmax thtrig tsutrig tdsof tdvclk tdrhclk tdfhclk tdadc tdblank Characteristic MCLK maximum frequency TRIGGER hold time w.r.t. MCLK TRIGGER setup time w.r.t. MCLK MCLK to SOF delay time MCLK to VCLK delay time Rising edge of MCLK to rising edge of HCLK delay time Falling edge of MCLK to falling edge of HCLK delay time MCLK to ADC[9:0] delay time MCLK to BLANK delay time Min 1 3.5 3.0 8 8.5 7.5 3 8 8 Typ 10 13 13.5 13 5 13 13 Max 20 9 8.5 21.5 22 22 10.5 21.5 21.5 Unit MHz ns ns ns ns ns ns ns ns
Table 8: Pixel Data Bus and Sync Timing Specification
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row 1039
IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
MCLK tsutrig TRIGGER tdsof thtrig
SOF tdvclk VCLK tdrhclk HCLK tdadc ADC[9:0] tdfhclk
Figure 23: Pixel Data Bus Timing Diagram
Strobe Signal
The Strobe signal is an output pin on the KAC1310 sensor. It can be activated by writing a "1" to vsg (bit 5) of the Trigger and Strobe Control Register (Table 29, page 57) while operating in SFRS mode. When activated, the Strobe signal goes high when all rows are integrating simultaneously and ends on row period (Trow) before the last row begins to integrate. The start of the strobe signal can also be set by the user. In default mode, when the strobe is activated, the signal fires two row periods before the first row begins to readout and lasts for a length of one Trow. A timing diagram for the Strobe signal is shown below in Figure 24.
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Tframe
TRIGGER 1st row of integration 2nd row of integration 3rd row of integration last row of integration SOF VCLK
Tint Tint Tint Tint
STROBE Trow
Tstrobe 2
Trow Tstrobe 1
Trow
Figure 24: STROBE Output Waveforms
To ensure that the Strobe signal fires, the integration time must be large enough to ensure that all rows are integrating simultaneously for at least 2 row periods (Trow) where Row Time (Trow) = (vcwd+shAd+shBd+19)* MCLKperiod To accomplish this , one must ensure that the integration time (cintd) is more than 2 row periods (Trow) larger than the active Window of Interest Row depth (wrdd). Therefore, minimum integration time: Tintmin = (cintdmin+1)* Trow where cintdmin = wrdd + 3. Tstrobe1 = Trow Tstrobe2 = Tintmin - (wrdd+1)*Trow An example of Strobe related calculations is provided below: Assumptions 1) Active Window of Interest = 1280 X 1024 ie. (wcwd) = 1279, (wrdd) = 1023 2) Virtual Column Width (vcwd) = 1290 3) Virtual Row Depth (vrdd)=1034
4) Sample & hold time (shAd) = 10 5) Sample & hold time (shBd) = 10 6) MCLK = 10 MHz Variables Integration Time (cintdmin) is the main variable used to control the time of the Strobe signals. Tintmin = (cintdmin+1)* Trow Calculations Trow= (vcwd + 10+10+19) * MCLKperiod = (1290 + 39) * 1e-7 = 132.9s Tintmin = (cintdmin+ 1) * Trow = (wrdd + 3 +1) * Trow = (1023 + 4) * 132.9s = 136.48 ms Tstrobe2 = Tintmin - (wrdd+1)*Trow = 136.48 ms - [(1023+1)* 132.9s] = 390.4 s TFrame = Tint + Trd = [(wrdd) +( cintd)+2] * Trow = (1023 + 1026 + 2) * 132.9s = 272.6 ms
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Example Timing Summary:
Signal Trow Tintmin Tstrobe1 Tstrobe2 TFrame Value 132.9 s 136.48 ms 132.9 s 390.4 s 272.6 ms
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS I2C-COMPATIBLE SERIAL INTERFACE
The I2C is an industry standard which is also compatible with the Motorola bus (called M-Bus) that is available on many microprocessor products. The I2C contains a serial two-wire halfduplex interface that features bi-directional operation, master or slave modes, and multimaster environment support. The clock frequency on the system is governed by the slowest device on the board. The SDATA and SCLK are the bidirectional data and clock pins, respectively. These pins are open drain and will require a pullup resistor to VDD of 1.5 to 10 (see Table 1). The I2C is used to write the required user system data into the Program Control Registers in the KAC-1310. The I2C bus can also read the data in the Program Control Register for verification or test considerations. The KAC-1310 is a slave only device that supports a maximum clock rate (SCLK) of 1/24th MCLK while reading or writing only one register address per I2C start/stop cycle. The following sections will be limited to the methods for writing and reading data into the KAC1310 register. For a complete reference to I2C, see "The I2C Bus from Theory to Practice" by Dominique Paret and Carll-Fenger, published by John Wiley & Sons, ISBN 0471962686 or refer to Philip Standard online at: http://www.us2.semiconductors.philips.com/i2c/.
MSB SCLK
1 2 3 4 5 6
LSB
7 8 9
MSB
1 2 3 4 5 6 7
LSB
8 9
SDATA
AD7 AD6 AD5 0 1 1
AD4 AD3 AD2 AD1 0 0 1 1
D7
D6
D5
D4
D3
D2
D1
D0
Start Signal
KAC-1310 I2C Bus Address
Write Ack Bit from KAC-1310
KAC-1310 Register Address
Ack Bit from KAC-1310
MSB SCLK
1 2 3 4 5 6 7
LSB
8 9
SDATA
D7
D6
D5
D4
D3
D2
D1
D0
Data to write KAC-1310 Register
Ack Bit Stop from Signal KAC-1310
Figure 25: I2C Bus WRITE Cycle
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS KAC-1310 I2C Bus Protocol
The KAC-1310 uses the I2C bus to write or read one register byte per start/stop I2C cycle as shown in Figure 25 and Figure 26. These figures will be used to describe the various parts of the I2C protocol communications as it applies to the KAC1310. KAC-1310 I2C bus communication is basically composed of following parts: START signal, KAC-1310 slave address (0110011b) transmission followed by a R/W bit, an acknowledgment signal from the slave, 8-bit data transfer followed by another acknowledgment signal, STOP signal, Repeated START signal, and clock synchronization. slaves in the system may have the same address. The KAC-1310 is configured to be a slave only.
Data Transfer
Once successful slave addressing is achieved, data transfer can proceed between the master and the selected slave in a direction specified by the R/W bit sent by the calling master. Note that for the first byte after a start signal (in Figure 25 and Figure 26), the R/W bit is always a "0" designating a write transfer. This is required since the next data transfer will contain the register address to be read or written. All transfers that come after a calling address cycle are referred to as data transfers, even if they carry sub-address information for the slave device. Each data byte is 8 bits long. Data may be changed only while SCLK is low and must be held stable while SCLK is high as shown in Figure 25. There is one clock pulse on SCLK for each data bit, the MSB being transferred first. Each data byte has to be followed by an acknowledge bit, which is signaled from the receiving device by pulling the SDATA low at the ninth clock. So one complete data byte transfer needs nine clock pulses. If the slave receiver does not acknowledge the master, the SDATA line must be left high by the slave. The master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the SDATA line for the master to generate STOP or START signal.
START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCLK and SDATA lines are at logical "1"), a master may initiate communication by sending a START signal. As shown in Figure 25 on page 36, a START signal is defined as a high-to-low transition of SDATA while SCLK is high. This signal denotes the beginning of a new data transfer and wakes up all the slaves on the bus.
Slave Address Transmission
The first byte of a data transfer, immediately after the START signal, is the slave address transmitted by the master. This is a 7-bit calling address followed by a R/W bit. The 7-bit address for the KAC-1310, starting with the MSB (AD7), is 0110011b. The transmitted calling address on the SDATA line may only be changed while SCLK is low as shown in Figure 25. The data on the SDATA line is valid on the High to Low signal transition on the SCLK line. The R/W bit following the 7-bits tells the slave the desired direction of data transfer: 1 = Read transfer, the slave transitions to a slave transmitter and sends the data to the master; 0 = Write transfer, the master transmits data to the slave.
Stop Signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called a Repeated START. A STOP signal is defined as a low-to-high transition of SDATA while SCLK is at logical "1" (see Figure 25). The master can generate a STOP even if the slave has generated an acknowledge bit at which point the slave must release the bus.
Acknowledgment
Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDATA line low at the 9th clock (see Figure 26 on page 39). If an acknowledgement is not received, many I2C master devices will assume that the slave device is not functioning. No two
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Repeated START Signal
A Repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. As shown in Figure 26, page 39, a Repeated START signal is being used during the read cycle and to redirect the data transfer from a write cycle (master transmits the register address to the slave) to a read cycle (slave transmits the data from the designated register to the slave).
* * * * *
I2C Bus Clocking and synchronization
Open drain outputs are used on the SCLK outputs of all master and slave devices so that the clock can be synchronized and stretched using wireAND logic. This means that the slowest device will keep the bus from going faster than it is capable of receiving or transmitting data. After the master has driven SCLK from High to Low, all the slaves drive SCLK Low for the required period that is needed by each slave device and then releases the SCLK bus. If the slave SCLK Low period is greater than the master SCLK Low period, the resulting SCLK bus signal Low period is stretched. Therefore, synchronized clocking occurs since the SCLK is held low by the device with the longest Low period. Also, this method can be used by the slaves to slow down the bit rate of a transfer. The master controls the length of time that the SCLK line is in the High state. The data on the SDATA line is valid when the master switches the SCLK line from a High to a Low. Slave devices may hold the SCLK low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCLK line.
*
KAC-1310 slave sends acknowledgment by forcing the SDATA Low during the 9th clock, if the Calling Address was received Master transmits the KAC-1310 Register Address KAC-1310 slave sends acknowledgment by forcing the SDATA Low during the 9th clock after receiving the Register Address Master transmits the data to be written into the register at the previously received Register Address KAC-1310 slave sends acknowledgment by forcing the SDATA Low during the 9th clock after receiving the data to be written into the Register Address The Master transmits STOP to end the write cycle
Register Read
Reading the KAC-1310 registers is accomplished with the following I2C transactions (see Figure 26, page 39): * Master transmits a START * Master transmits the KAC-1310 Slave Calling Address with "WRITE" indicated (BYTE=66h, 102d, 01100110b) * KAC-1310 slave sends acknowledgment by forcing the SDATA Low during the 9th clock, if the Calling Address was received * Master transmits the KAC-1310 Register Address * KAC-1310 slave sends acknowledgment by forcing the SDATA Low during the 9th clock after receiving the Register Address * Master transmits a Repeated START * Master transmits the KAC-1310 Slave Calling Address with "READ" indicated (BYTE = 67h, 103d, 01100111b) * KAC-1310 slave sends acknowledgment by forcing the SDATA Low during the 9th clock, if the Calling Address was received * At this point, the KAC-1310 transitions from a "Slave-Receiver" to a "Slave-Transmitter" * KAC-1310 sends the SCLK and the Register Data contained in the Register Address that was previously received from the master; KAC-1310 transitions to slave-receiver * Master does not send an acknowledgment (NAK) * Master transmits STOP to end the read cycle
Register Write
Writing the KAC-1310 registers is accomplished with the following I2C transactions (see Figure 25 page 36):
* *
Master transmits a START Master transmits the KAC-1310 Slave Calling Address with "WRITE" indicated (BYTE=66h, 102d, 01100110b)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
SCLK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
MSB SDATA
AD7 AD6 AD5 0 1 1
LSB
AD4 AD3 AD2 AD1 0 0 1 1
MSB
D7 D6 D5 D4 D3 D2 D1
LSB
D0 XX
Start Signal
KAC-1310 I2C Bus Address
Write Ack Bit from KAC-1310
KAC-1310 Register Address
Ack Bit from KAC-1310
Repeated Start Signal
SCLK
1
2
3
4
5
6
7
8
9
MSB SDATA
AD7 AD6 AD5 0 1 1
LSB
AD4 AD3 AD2 AD1 0 0 1 1
At this point the KAC-1310 transitions from a "SLAVE-receiver" to a "SLAVE-transmitter
KAC-1310 I2C Bus Address
Read Ack Bit from KAC-1310
SCLK
1
2
3
4
5
6
7
8
9
MSB SDATA
D7 D6 D5 D4 D3 D2
LSB
D1 D0
The KAC-1310 transitions from a "SLAVE-transmitter" to a "SLAVE-receiver" after the register data is sent
Data to write KAC-1310 Register No Ack Bit from MASTER terminates the transfer
Stop Signal from MASTER
Single Byte Transfer to Master
Figure 26: I2C Bus READ Cycle
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Symbol fmax M1 M2 M3 M4 M5 M6 M7 M8 M9 CI Cbus Rp
Characteristic SCLK maximum frequency Start condition SCLK hold time SCLK low period SCLK/SDATA rise time [from VIL = (0.2)*VDD to VIH = (0.8)*VDD] SDATA hold time SCLK/SDATA fall time (from Vh = 2.4V to VI = 0.5V) SCLK high period SDATA setup time Start / Repeated Start condition SCLK setup time Stop condition SCLK setup time Capacitive for each I/O pin Capacitive bus load for SCLK and SDATA Pull-up Resistor on SCLK and SDATA
Min 50 4 8 4 4 4 4 4 1.5
Max 1/24 MCLK 0.3 0.3 10 200 10
Unit KHz1 TMCLK
3
TMCLK s2 TMCLK s2 TMCLK TMCLK3 TMCLK TMCLK pF pF k4
3
2 Table 9: I C-compatible Serial Interface Timing Specification
Notes: 1. SCLK frequency maximum limit is 1/24 MCLK frequency. 2. The capaitive load is 200pF 4 3. The unit TMCLK is the period of the input master clock; the frequency of MCLK is assumed 10.0 MHz. A pull-up resistor to VDD is required on each of the SCLK and SDATA lines; for a maximum bus capacitive load of 200pF, the minimum value of Rp should be selected in order to meet specifications. I2C is a proprietary Philips interface bus.
M2 SCLK M1 SDATA M8
M6
M5
VIH VIL
M3
M4
M7
M8
M9
Figure 27: I2C Bus Timing
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS REGISTER LIST REFERENCE
Note: In each table where a suffix code is used; h = hex, b = binary, and d = decimal.
The I2C addressing is broken up into groups and assigned to a specific digital block. The designated block is responsible for driving the internal control bus, when the assigned range of addresses is present on the internal address bus. The grouping designation and assigned range are listed in Table 10. Each block contains registers that are loaded and read by the digital and analog blocks to provide configuration control via the I2C serial interface.
Address Range 00h - 2Fh 40h - 7Fh 80h - BFh Block Name Analog Register Interface Sensor Interface Column Offset Coefficients
2 Table 10. I C Address Range Assignments
Table 11 and Table 12 contain all the I2C address assignments. The table includes a column indicating whether the register values are shadowed with respect to the sensor interface. If the register is shadowed, the sensor interface will only be updated upon frame boundaries, thereby eliminating intraframe artifacts resulting from register changes.
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Hex Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 20h 21h 22h 23h 24h 3Fh 1Fh Register Function DPGA Color 1 Gain Register (Green1 or Cyan) DPGA Color 2 Gain Register (Red or Yellow1) DPGA Color 3 Gain Register (Blue or Yellow2) DPGA Color 4 Gain Register (Green2 or Magenta) Unused Factory Use Only Factory Use Only Factory Use Only Factory Use Only Factory Use Only Negative ADC Reference Register Positive ADC Reference Register Power Configuration Register Factory Use Only Reset Control Register Device Identification (read only) PGA Exposure (Global) Gain A Register Unused Tristate Control Register Factory Use Only Unused Column DOVA DC Register PGA Exposure Global Gain B Register PGA Gain Mode Register ADC DOVA Register Unused
2 Table 11: I C Address Assignments (0h- 3Fh)
Ref Default 0Eh 0Eh 0Eh 0Eh Table Table 13, pg 44 Table 14, pg 45 Table 15, pg 45 Table 16, pg 45 Shadowed? Yes Yes Yes Yes
76h 80h 00h
Table 17, pg 46 Table 18, pg 46 Table 19, pg 47
No No No
00h 50h 0Eh
Table 20, pg 48
No No
Table 21, pg 49
Yes
03h
Table 22, pg 50
00h 0Eh 00h 00h
Table 23, pg 51 Table 24, pg 52 Table 25, pg 53 Table 26, pg 54
No Yes No No
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Hex Address 40h 41h 42h 43h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 60h 61h 64h 65h 66h 67h 69h 80h C0h 68h 7Fh BFh FFh 63h 5Eh 5Fh 44h Register Function Capture Mode Register Sub-Sample Control Register TRIGGER and Strobe Control Register Unused WOI Row Pointer MSB Register WOI Row Pointer LSB Register WOI Row Depth MSB Register WOI Row Depth LSB Register WOI Column Pointer MSB Register WOI Column Pointer LSB Register WOI Column Width MSB Register WOI Column Width LSB Register Unused Integration Time MSB Register Integration Time LSB Register Virtual Frame Row Depth MSB Register Virtual Frame Row Depth LSB Register Virtual Frame Column Width MSB Register Virtual Frame Column Width LSB Register SOF Delay Register VCLK Delay Register SOF & VLCK Width Register Readout Direction Control Register Unused Internal Timing Control Register (SHA) Internal Timing Control Register (SHB) Factory Use Only Clamp Control and HCLK Delay Register Encoded Sync Register Unused Factory Use Only Unused Mod64 Col Offset Registers Unused 00h Table 52, pg 70 5Ch 00h Table 50, pg 68 Table 51, pg 69 Yes 0Ah 0Ah Table 48, pg 67 Table 49, pg 67 Yes Yes 04h FFh 04h 27h 05h 13h 4Ch 02h 0Eh 04h Table 38, pg 61 Table 39, pg 61 Table 40, pg 62 Table 41, pg 63 Table 42, pg 63 Table 43, pg 63 Table 44, pg 64 Table 45, pg 64 Table 46, pg 65 Table 47, pg 66 Yes Yes Yes Yes Yes Yes No No No No 00h 10h 03h FFh 00h 08h 04h FFh Table 30, pg 58 Table 31, pg 58 Table 34, pg 59 Table 35, pg 60 Table 32, pg 59 Table 33, pg 59 Table 36, pg 60 Table 37, pg 60 Yes Yes Yes Yes Yes Yes Yes Yes Default 2Ah 10h 02h Ref Table Table 27, pg 55 Table 28, pg 56 Table 29, pg 57 Shadowed? Yes Yes Yes
Table 12: I2C Address Assignments (40h - FFh)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS DETAILED REGISTER BLOCK ASSIGNMENTS
This section describes in further detail the functional operation of the various KAC-1310 programmable registers. register is programmable given the gain function defined in the table. The user programs these registers to account for changing light conditions to assure a white balanced output. The default value in each register provides for a unity gain for the default Raw Mode. In addition, the default CFA pattern color is listed in the title of each register. The Gain Mode is set by Register 22h, Table 25 on page 53.
Color Gain Registers 00h
03h
The four Color Gain Registers, Color Tile Configuration Register, and four Color Tile Row definitions define how white balance is achieved on the device. Six-bit gain codes can be selected for four separate colors: Table 13, Table 14, Table 15, and Table 16. Gain for each individual color
Raw Gain Mode (WB and Exposure) Gain 0.6950 + 0.02175 * Regd 1.3475 + 0.04350 * (Regd - 31) Lin1 Gain Mode (WB and Exposure) Gain 0.6950 + 0.04350 * Regd Lin2 Gain Mode (Exposure gain stage only) Gain 0.483 + 0.11119 * (Reg 10h)d
0 < Regd < 31 32 < Regd < 63 0 < Regd < 47 0 < Regd < 63
(0.0695x (1.3910x (0.695x (0.483x
1.36925x) 2.7395x) 2.7395x) 7.488x)
Address 00h 7 (msb) x Bit Number 7-6 5-0 Unused Unused Gain 6 x 5
PGA Color 1 Gain Code
Green1 or Cyan 4 cg1[4] 3 cg1[3] 2 cg1[2] 1 cg1[1]
Default 0Eh 0 (lsb) cg1[0] Reset State xxb 001110b
cg1[5]
Function Description
See Gain Equation Default Gain in Raw mode = 1.0 Default Gain in Lin1 Mode = 1.3 Table 13: PGA Color 1 Gain Register (00h)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Address 01h 7 (msb) x Bit Number 7-6 5-0 Unused Unused Gain See Gain Equation Default Gain in Raw mode = 1.0 Default Gain in Lin1 Mode = 1.3 Table 14: PGA Color 2 Gain Register (01h) 6 x 5 cg2[5]
PGA Color 2 Gain Code
Red or Yellow1 4 cg2[4] 3 cg2[3] 2 cg2[2] 1 cg2[1]
Default 0Eh 0 (lsb) cg2[0] Reset State xxb 001110b
Function Description
Address 02h 7 (msb) x Bit Number 7-6 5-0 Unused Unused Gain 6 x 5
PGA Color 3 Gain Code
Blue or Yellow2 4 cg3[4] 3 cg3[3] 2 cg3[2] 1 cg3[1]
Default 0Eh 0 (lsb) cg3[0] Reset State xxb 001110b
cg3[5]
Function Description
See Gain Equation Default Gain in Raw mode = 1.0 Default Gain in Lin1 Mode = 1.3 Table 15: PGA Color 3 Gain Register (02h)
Address 03h 7 (msb) x Bit Number 7-6 5-0 Unused Unused Gain 6 x 5
PGA Color 4 Gain Code
Green2 or Magenta 4 cg4[4] 3 cg4[3] 2 cg4[2] 1 cg4[1]
Default 0Eh 0 (lsb) cg4[0] Reset State xxb 001110b
cg4[5]
Function Description
See Gain Equation Default Gain in Raw mode = 1.0 Default Gain in Lin1 Mode = 1.3 Table 16: PGA Color 4 Gain Register (03h)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Reference Voltage Adjust Registers (0Ah, 0Bh)
The analog register block allows programming the input voltage range of the analog to digital converter to match the saturation voltage of the pixel array (this effectively sets the mV/dn conversion ratio). The voltage reference generator can be programmed via two registers; "positive" ADC reference voltage (prv) (2.5V to 1.25V) in Table 18, and "negative" ADC reference voltage (nrv) (0 to 1.25V) in Table 17, in 5mV steps. The default settings for prv produce a 1.86V positive reference. The default settings for nrv produce a 0.59V negative reference. These two references define the ADC analog input range. When adjusting these values, the user should keep the voltage range centered at 1.25V. These ADC references can be adjusted to mV/DN of the ADC. This effectively acts as another gain stage just before the ADC. Excessive adjustment of these values from their default can result in increased power consumption and increased image artifacts. The following equation defines the mV/DN at the input to the ADC: If the 20x gain provided by the PGAs is not sufficient, the ADC references can be used to
mV 2(V + - V - ) 2(1.86 - 0.59) mV = = = 2.48 10dn 10dn 1024 1024
apply additional gain to the ASP. To increase the gain the ADC references need to be moved closer to Vcm (1.25V). This should be used only after the PGAs have been used to their fullest since moving the ADC references too far will degrade the ADC performance. The effective gain of the ADC block will be:
Gain =
2.48
2(V + -V - ) 1024
Address 0Ah 7 (msb) nrv[7] Bit Number 6 nrv[6] Function
"Negative" ADC Reference Voltage
5 nrv[5] Description 4 nrv[4] 3 nrv[3] 2 nrv[2] 1 nrv[1]
Default 76h 0 (lsb) nrv[0] Reset State
Table 17: Negative Voltage Reference Register (0Ah)
Address 0Bh 7 (msb) prv[7] Bit Number 7-0 Reference 6 prv[6] Function
"Positive" ADC Reference Voltage
5 prv[5] Description 4 prv[4] 3 prv[3] 2 prv[2] 1 prv[1]
Default 80h 0 (lsb) prv[0] Reset State
Voltage = 2.5 - (5mV * prcd)
10000000b (1.86V)
Table 18: Positive Voltage Reference Register (0Bh)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Power Configuration Registers (0Ch)
The Power Configuration Register controls the internal analog functionality that directly affects power consumption of the device. A pair of external precision resistor pins are available on the KAC-1310 that may be used to more accurately regulate the internal current sources. This serves to minimize variations in power consumption that are caused by variations in internal resistor values as well as offer a method to reduce the power consumption of the device. The default for this control uses the internally provided resistor which is nominally 12.5k. This feature is enabled by setting the res bit of the Power Configuration Register and placing a resistor between the EXTRESA and EXTRESB pins. Figure 19 on page 30 depicts the power savings that can be achieved with an external resistor at the nominal clock rate of 10 MHz. Power is further reduced at lower clock rates. Figure 18 shows how the noise of the system is affected by the EXTRES. It is recommended that the External Resistor be kept at 39k at nominal speed. The optimal EXTRES value will change based on system needs and chip frequency. The KAC-1310 is put into a standby mode via the I2C interface by setting the sby bit of the Power Configuration Register. While the imager is in this mode the power consumption is reduced considerably (see Table 19). Also, the I2C continues to work and any number of registers can be programmed. Upon leaving standby state the imager will remember all register settings and apply them to the first imager captured.
Address 0Ch 7 (msb) x Bit Number 7-5 4 3 Unused FUO Int/Ext Resistor 2-1 0 FUO Software Standby Unused Factory Use Only 6 x Function 5 x Description
Power Configuration
4 fuo 3 res 2 fuo 1 fuo
Default 00h 0 (lsb) sby Reset State xxxb 0b 0b
0b = Internal Resistor 1b = External Resistor Factory Use Only 0b = Soft Standby Inactive 1b = Soft Standby Active Table 19: Power Configuration Register (0Ch)
00b 0b
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Reset Control Register (0Eh)
Setting the asr, ssr, par, and sir bits of this register will reset all the non-user programmable registers to a known reset state. All programmable registers will retain their values. This is useful in situations when control of the KAC-1310 has been lost due to system interrupts and the device needs only be restarted using the earlier user programmed values. Setting the sit bit allows the user to completely reset the KAC1310 to the default state via the serial control interface. All user programmable registers will revert to default values. For each of these reset bits a value of 0 must be sent to register 0Eh after use to take the imager back out of reset mode. Typically only the first two bits are needed. Bit 1 (ssr) resets all state machines and internal registers, but leaves the programmable registers intact. Bit 0 (sit) resets all registers, internal and user programmable to default values.
Address 0Eh 7 (msb) x Bit Number 7-5 4 Unused Unused 6 x Function 5 x Description 4 asr
Reset Control
3 par 2 sir 1 ssr
Default 00h 0 (lsb) sit Reset State xxxb 0b
ASP(A2D) 0b = Normal Mode Reset 1b = Reset registers in the ASP and ADC (state machine reset) Post ADC 0b = Normal Mode Reset 1b = Reset non-programmable POST ADC internal registers to init state Sensor Interface Reset State Reset 0b = Normal Mode 1b = Reset non-programmable Sensor Interface registers (state machines) to init state 0b = Normal Mode 1b = Reset all non-programmable registers to default state 0b = Normal Mode 1b = Reset all registers to default state (all programmed regs>default) Table 20: Reset Control Register (0Eh)
3
0b
2
0b
1
0b
0
Soft Reset
0b
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Exposure Gain A Register (10h)
The PGA Exposure (Global) Gain Register allows the user to set one of the global gains via a 6-bit register. This is applied universally to all the pixel outputs. This enables the user to account for varying light conditions. The gain range depends on the Exposure Gain Mode setting (Register 22h, Table 25 on page 53). In Raw or Lin1 mode both Exposure Gain A (10h) and Exposure Gain B (21h) are programmed as successive gains stages. If Lin2 Mode is selected then Register 10h is used to Raw Gain Mode (WB and Exposure) Gain 0.6950 + 0.02175 * Regd 1.3475 + 0.04350 * (Regd - 31) Lin1 Gain Mode (WB and Exposure) Gain 0.6950 + 0.04350 * Regd Lin2 Gain Mode (Exposure gain stage only) Gain 0.483 + 0.11119 * (Reg 10h)d program both Exposure gain stages as if they were one linear gain stage. Further discussion of the Gain stages can be found the Programmable Gain Amplifier section on page 17, and in the Global Digital Offset Adjustment section on page 20. If register 10h is increased to its maximum and still more gain is needed, Exposure Gain B can then be increased, via Register 21h, Table 24 on page 52. The gain equations of each gain mode are:
0 < Regd < 31 32 < Regd < 63 0 < Regd < 47 0 < Regd < 63
(0.0695x (1.3910x (0.695x (0.483x
1.36925x) 2.7395x) 2.7395x) 7.488x)
NOTE: the gain step size of Lin2 Mode is almost, but not completely uniform. Any one step may deviate from the mean step size of 0.11119 by a small amount. This is due to the fact that Lin2 Mode actually varies two gain stages with fixed step sizes to make one equivalent gain step.
Address 10h 7 (msb) x Bit Number 7-6 5-0 Unused Gain Unused Gain equation depends on Gain Mode: Raw, Lin1, or Lin2 (Default is unity gain for Raw mode) Table 21: A Exposure Gain A Register (10h) 6 x Function 5 gg1[5] Description 4 gg1[4] 3 gg1[3] 2 gg1[2] 1 gg1[1]
Global Gain A
Default 0Eh 0 (lsb) gg1[0] Reset State xxb 001110b
Tristate Control Register (12h)
The Tristate Control Register is used to set the chip outputs into tristate. This functionality is useful if these outputs are on a bus that is being shared by other devices. When the tsctl bit is reset (ie "0") the SOF, VCLK, HCLK, and STROBE output pins are placed in tristate mode. The 10 ADC output pins can be tristated by resetting the tspix bit ("0").
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Address 12h 7 (msb) FUO Bit Number 7-2 1 FUO Factory Use Only 6 FUO Function Description 5 FUO 4 FUO 3 FUO 2 FUO 1 tsctl
Tristate Control
Default 03h 0 (lsb) tspix Reset State 000000b 1b
Sync Tristate 0b = HCLK, SOF, VCLK, and Strobe sync pins tristated 1b = Sync pins driven
0
ADC Tristate 0b = ADC outputs pins tristated 1b = ADC output pins driven Table 22: Tristate Control Register (12h)
1b
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Column DOVA DC Register (20h)
Offset adjustments for the KAC-1310 are done in separate sections of the ASP to facilitate FPN removal and final image black level set. The primary purpose of the Column DOVA DC Register is to compensate for pre-gain offset. If this register is set to zero the user may find that the dark level of some chips may move with different programmed gain values. In addition the white balance gain stage can result in different effective dark levels for different colors. These effects MAY cause distortion with certain post image signal processing. In these cases the Column DOVA DC Register can be programmed such that the dark pixel level is independent of programmed gain values. The simplest method for setting this register is to place the imager in the dark and record the mean value for the dark pixels. Then increase the global gain register (10h) to the maximum gain to be used in the application. Adjust register 20h until the dark level has returned to the level previously recorded with unity gain. This process can be repeated again for greater accuracy since the dark level at unity gain will now have shifted slightly. For many applications, this register can be left in its default state of 00h. If during the calibration of this register the value of any pixels are observed to be clipping at zero counts, it is then necessary to temporarily increase the ADC DOVA (reg 23h) to avoid clipping. Register 20h should not be used to adjust the code value of the dark level for the ADC, this should always be done with the ADC DOVA (reg 23h) The Column DOVA stage is also used to correct for patterned column noise. This is done pre-gain. The column pattern correction offsets are defined in Reg 80h BFh, see Table 52 on page 70. The Column DOVA stage has only six bits of programmability. Registers 20h is added to the value in 80h BFh for that column. The final sum is clipped to 32d.
Default 00h 6 x Function 5 cdd[5] Description 4 cdd[4] 3 cdd[3] 2 cdd[2] 1 cdd[1] 0 (lsb) cdd[0] Reset State Unused Sign Unused 0b = Positive Offset 1b = Negative Offset 4-0 Column DC Offset Offset = 2.6 * cddd (64 steps @ 2.6 mV/step) 00000b xxb 0b
Address 20h 7 (msb) x Bit Number 7-6 5
Column DOVA DC
Table 23: Column DOVA DC Offset (20h)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Exposure GainB (21h)
The PGA Exposure (Global) Gain Register allows the user to set one of the global gains via a 6 bit register. This is applied universally to all the pixel outputs. This enables the user to account for varying light conditions. The gain range depends on the Exposure Gain Mode setting (Register 22h, Table 25 on page 53). In Raw or Lin1 mode both Exposure Gain A(10h) and Exposure Gain B(21h) Raw Gain Mode (WB and Exposure) Gain 0.6950 + 0.02175 * Regd 1.3475 + 0.04350 * (Regd - 31) Lin1 Gain Mode (WB and Exposure) Gain 0.6950 + 0.04350 * Regd Lin2 Gain Mode This register is not used in this mode. See Exposure Gain A, Table 21 on page 45 for programming this mode.
Address 21h 7 (msb) x Bit Number 7-6 5-0 Unused Gain Unused Gain equation depends on Gain Mode: Raw, Lin1, or Lin2 (Default is unity gain for Raw mode) Table 24: Exposure Gain B (21h) 6 x Function 5 gg2[5] Description 4 gg2[4] 3 gg2[3] 2 gg2[2] 1 gg2[1]
are programmed as successive gains stages. If Lin2 Mode is selected then Register 10h is used to program both Exposure gain stages as if they were one linear gain stage. Further discussion of the Gain stages can be found in "Programmable Gain Amplifier" on page 17, and "Global Digital Offset Adjust" on page 20. The gain equations of each gain mode are:
0 < Regd < 31 32 < Regd < 63 0 < Regd < 47
(0.0695x (1.3910x (0.695x
1.36925x) 2.7395x) 2.7395x)
Exposure Gain B
Default 0Eh 0 (lsb) gg2[0] Reset State xxb 001110b
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS PGA Gain Mode (22h)
There exist three different gain modes that are available when the sensor is performing White Balance and Exposure gain. Plots of the three Raw Gain Mode (WB and Exposure) Gain 0.6950 + 0.02175 * Regd 1.3475 + 0.04350 * (Regd - 31) Lin1 Gain Mode (WB and Exposure) Gain 0.6950 + 0.04350 * Regd Lin2 Gain Mode (Exposure gain stage only) Gain 0.483 + 0.11119 * (Reg 10h)d gain modes are illustrated in Figure 12 on page 18. The three gain modes are:
0 < Regd < 31 32 < Regd < 63 0 < Regd < 47 0 < Regd < 63
(0.0695x (1.3910x (0.695x (0.483x
1.36925x) 2.7395x) 2.7395x) 7.488x)
NOTE: the gain step size of Lin2 Mode is almost, but not completely uniform. Any one step may deviate from the mean step size of 0.11119 by a small amount. This is due to the fact that Lin2 Mode actually varies two gain stages with fixed step sizes to make one equivalent gain step.
The wbm bit sets the gain mode for the WB gain (Register 0h-3h, pages 44 and 45). The egm bits set the gain mode for the Exposure Gains Registers (10h page 49 and 21h page 52.)
Address 22h 7 (msb) x Bit Number 7-3 2 6 x 5 x Default 00h 2 wbm 1 egm[1] 0 (lsb) egm[0] Reset State xxxxxb 0b
PGA Gain Mode
4 x 3 x
Function Description Unused Unused
WB Gain 0b = Raw Gain Mode Mode 1b = Lin1 Gain Mode 00b = Raw Gain Mode Exposure 01b = Lin1 Gain Mode Gain Mode 1xb = Lin2 Gain Mode
1-0
00b
Table 25: PGA Gain Mode (22h)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS ADC DOVA (23h)
The Global DOVA Register performs a final offset adjustment in analog space just prior to the ADC. The 6-bit register uses its MSB to indicate positive or negative offset. Each register value changes the offset by 4 LSB code levels hence giving an offset range of 124 dn. As an example, to program an offset of +92 dn, the value of 010111b (23d, 17h) should be loaded. This offset is used to place the dark level within the ADC range.
Address 23h 7 (msb) x Bit Number 7-6 5 Unused Sign Unused 0b = Positive Offset 6 x Function 5 gd[5] Description
ADC DOVA
4 gd[4] 3 gd[3] 2 gd[2] 1 gd[1]
Default 00h 0 (lsb) gd[0] Reset State xxb 0b
1b = Negative Offset 4-0 Column DC Offset Offset (mV) = 12 * gdd (64 steps @ 12 mV/step) Table 26: ADC DOVA Register (23h) 00000b
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Capture Mode Control (40h)
The Capture Mode Control Register defines how the data is captured and how the data is to be provided at the output. Setting the cms bit will stop the current CFRS output data stream at the end of the current frame and place the imager in Single Frame Capture Mode (SFRS). While the cms bit is set (SFRS), the output of frames can be paused with the TRIGGER input pin. When the TRIGGER pin is low (VSS) the output of frames is suspended. When the TRIGGER pin is high (VDD) frames are continuous. The default for cms is 0 (CFRS). In CFRS the frames are continuously output and the TRIGGER pin is ignored. The Frame Rate is slightly reduced when the cms is set (SFRS) because care is taken in the startup such that the first frame output is valid. This causes a slight delay at the start of each frame. See Figure 22 on page 32 for a timing diagram for SFRS mode. With the cms low(=0), the Frame Rate is faster, but the first frame will be invalid (wrong integration time). When the hm bit is set, the HCLK sync is high whenever valid WOI pixel data is being clocked out and low during the other blanking intervals. The HCLK does NOT toggle at the MCLK rate when the hm bit is set. When hm is set the HCLK will go high once at the beginning of the valid pixel data and remain high until the last WOI pixel has been clocked out. When the hm bit is set the he bit is ignored. The sp bit is used to define whether SOF is active high or low. SOF is active high by default. The ve bit is used to determine whether VCLK is output at the beginning of the virtual frame rows or only for the WOI rows. The ve bit defaults to VCLK on WOI rows only. The vp bit is used to define whether VCLK is active high(the default) or active low. The he bit is used to determine whether HCLK is output continuously (needed for some frame grabbers) or only for pixels within the WOI (default). The hp bit is used to define whether HCLK is active high (default) or low.
Address 40h 7 (msb) FUO Bit Number 7 6 5 4 3 2 1 0 FUO RSCM Mode SOF Phase VCLK Enable VCLK Phase HCLK Enable HCLK Phase HCLK Mode 6 cms Function 5 sp Description
Capture Mode Control
4 ve 3 vp 2 he 1 hp
Default 2Ah 0 (lsb) hm Reset State 0b 0b 1b 0b 1b 0b 1b 0b
Factory Use Only 0b = Continuous Frame Rolling Shutter (CFRS) 1b = Single Frame Rolling Shutter (SFRS) 0b = SOF sync active low 1b = SOF sync active high 0b = VCLK Sync on WOI rows only 1b = VCLK Sync on WOI and Virtual Rows 0b = Active low 1b = Active high 0b = Pixel sync on WOI pixels only 1b = Continuous pixel sync 0b = Active low 1b = Active high 0b = Toggles - Toggles at MCLK rates defined by (he) bit 1b = Continuous - Pixel Valid Envelope Table 27: Capture Mode Register (40h)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Sub-sample Control (41h)
The sub-sample Control Register is used to define what pixels of the WOI are read and the method they are output. See "Sub-Sampling Control (Resolution)" on page 12 for details on the readout modes. Sub-sampled frames readout faster than the full frame image. Any pixel not selected in the sub-sample mode is ignored, thereby not slowing the Frame Rate. Bit cm can be cleared for monochrome imagers. This allows the imager to skip single columns and rows improving uniformity of sub-sampled MTF. In color mode sub-sampling is done in column and row pairs to conserve color integrity. The degree of sub-sample is defined by rf [1:0] for the rows, while the column sub-sample is independently defined by cf [1:0]. Row binning (even/odd row summing) is activated with the bn bit.
Default 10h 6 FUO Function 5 bn Description 4 cm 3 rf[1] 2 rf[0] 1 cf[1] 0 (lsb) cf[0] Reset State Unused FUO Binning Unused Factory Use Only 0b = Full WOI readout 1b = Even/Odd Row Summing 4 Color Mode 3-2 0b = Monochrome Pattern Sampling (kernel=1) 1b = Bayer Pattern Sampling (kernel=2) 00b 1b xb 0b 0b
Address 41h 7 (msb) x Bit Number 7 6 5
Capture Mode Control
Row Sub- 00b = Full WOI readout Sampling 01b = Read one kernel, skip one (1/2 sampled) Mode 10b = Read one kernel, skip three (1/4 sampled) 11b = Read one kernel, skip seven (1/8 sampled)
1-0
Column
00b = Full WOI readout 10b = Read one kernel, skip three (1/4 sampled) 11b = Read one kernel, skip seven (1/8 sampled)
00b
Sub-Sampling 01b = Read one kernel, skip one (1/2 sampled) Mode
Table 28: Sub-Sample Control Register (41h)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS TRIGGER and STROBE Control Register (42h)
The saw bit allows the user to select how long the STROBE signal is going to be on. If the bit is set to 1, the STROBE output will go high when all lines are concurrently integrating and will go low when the integration time has completed and readout has begun. It is during this period while STROBE is high that a mechanical shutter must open and close and/or flash must fire and quench if these devices are being used with the imager. If the shutter or flash operate at any other time image artifacts can result. Note the integration time must be greater than a frame readout time for this output to be useful. The sae bit when enabled will enable the STROBE signal to be generated automatically by the sensor. This will only work in Single Frame Rolling Shutter (SFRS) mode. The se bit, when enabled, will allow for an external signal to drive the trigger signal via the TRIGGER pin on the chip. Enabling the sa bit forces the trigger signal high until this bit is disabled. This causes continuous frame processing in SFRS mode. The sr bit, when enabled, causes the TRIGGER signal to go high for exactly one clock cycle, and then returns to a low. It remains low until the sr bit is enabled again. This is used to trigger a single frame capture via I2C rather than the TRIGGER pin.
Address 42h 7 (msb) x Bit Number 7-6 5 4 Unused Unused 6 x Function 5 sso
TRIGGER and STROBE Control
Default 02h
4 saw
3 sae
2 se
1 sa
0 (lsb) sr Reset State xxb 0b 0b
Description
Factory Use Only Strobe Width 0b = 1 line time 1b = Pulse width is high while all rows are simultaneously integrating
3
STROBE Enable
0b = STROBE pin Disabled 1b = STROBE pin Enabled
0b
2
TRIGGER 0b = External TRIGGER input pin Disabled (ignored) Enable 1b = External TRIGGER input pin Enabled TRIGGER 0b = No effect Always On 1b = TRIGGER input is internally held HIGH, TRIGGER input pin is ignored Software 0b = No effect TRIGGER 1b = Triggers a single frame capture via I2C Table 29: TRIGGER and STROBE Control Register (42h)
0b
1
1b
0
0b
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Programmable Window of Interest (WOI) (45h-4Ch)
The WOI is defined by a set of registers that indicate the upper-left starting point for the window and another set of registers that define the size of the window. Refer to Figure 7 on page 12 for a pictorial representation of the WOI within the active pixel array. The WOI Row Pointer, wrp[8:0], and the WOI Column Pointer, wcp[9:0], mark the upper-left starting point for the WOI. The
Address 45h 7 (msb) x Bit Number 7-3 2-0 Unused Unused 6 x Function 5 x Description 4 x 3 x 2 wrp[10] 1 wrp[9]
WOI Row Depth, wrd[9:0] and the WOI Column Depth, wcw[10:0] indicate the size of the WOI. The user must be careful to create a WOI that is completely confined within the Virtual Frame. There is no logic in the sensor interface to prevent the user from defining a WOI that addresses nonexistent pixels.
WOI Row Pointer MSB
Default 00h 0 (lsb) wrp[8] Reset State xxxxxb 000b
WOI Row In conjunction with the WOI Row Pointer LSB Register, forms the Pointer 11-bit WOI Row Pointer wrp[10:0] Table 30: WOI Row Pointer MSB Register (45h)
Address 46h 7 (msb) wrp[7] Bit Number 7-0 6 wrp[6] Function 5 wrp[5] Description
WOI Row Pointer LSB
4 wrp[4] 3 wrp[3] 2 wrp[2] 1 wrp[1]
Default 10h 0 (lsb) wrp[0] Reset State
WOI Row In conjunction with the WOI Row Pointer MSB Register, forms the 11 bit WOI Row Pointer wrp[10:0] Pointer Table 31: WOI Row Pointer LSB Register (46h)
00010000b (16d)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Address 49h 7 (msb) x Bit Number 7-3 2-0 Unused Unused 6 x Function 5 x Description 4 x 3 x 2 wcp[10] 1 wcp[9]
WOI Column Pointer MSB
Default 00h 0 (lsb) wcp[8] Reset State xxxxxb 000b
WOI Column In conjunction with the WOI Column Pointer LSB Register, Pointer forms the 11-bit WOI Column Pointer wcp[10:0]
Table 32: WOI Column Pointer MSB Register (49h) Address 4Ah 7 (msb) wcp[7] Bit Number 7-0 WOI Column In conjunction with the WOI Column Pointer MSB Register, Pointer forms the 11-bit WOI Column Pointer wcp[10:0] 6 wcp[6] Function 5 wcp[5] Description 4 wcp[4] 3 wcp[3] 2 wcp[2] 1 wcp[1]
WOI Column Pointer LSB
Default 08h 0 (lsb) wcp[0] Reset State 00001000b (8d)
Table 33: WOI Column Pointer LSB Register (4Ah)
Address 47h 7 (msb) x Bit Number 7-3 2-0 Unused Unused 6 x 5 x
WOI Row Depth MSB
4 x 3 x 2 wrd[10] 1 wrd[9]
Default 03h 0 (lsb) wrd[8] Reset State xxxxxb 011b
Function Description
WOI Row In conjunction with the WOI Row Depth LSB Register, forms the 11-bit WOI Row Depth wrd[10:0] Depth
Table 34: WOI Row Depth MSB Register (47h)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Address 48h 7 (msb) wrd[7] Bit Number 7-0 WOI Row In conjunction with the WOI Row Depth MSB Register, forms Depth the 11-bit WOI Row Depth wrd[10:0] Desired = wrdd+1 6 wrd[6] Function 5 wrd[5] Description 4 wrd[4] 3 wrd[3] 2 wrd[2] 1 wrd[1]
WOI Row Depth LSB
Default FFh 0 (lsb) wrd[0] Reset State 11111111b 1024 Rows
Table 35: WOI Row Depth LSB Register (48h)
Address 4Bh 7 (msb) x Bit Number 7-3 2-0 Unused Unused 6 x 5 x
WOI Column Width MSB
4 x 3 x 2 wcw[10] 1 wcw[9]
Default 04h 0 (lsb) wcw[8] Reset State xxxxxxb 100b
Function Description
WOI Column In conjunction with the WOI Column Width LSB Register, forms Width the 11-bit WOI Column Width wcw[10:0]
Table 36: WOI Column Width MSB Register (4Bh)
Address 4Ch 7 (msb) wcw[7] Bit Number 7-0 6 wcw[6] Function 5 wcw[5]
WOI Column Width LSB
4 wcw[4] 3 wcw[3] 2 wcw[2] 1 wcw[1]
Default FFh 0 (lsb) wcw[0] Reset State
Description
WOI Column In conjunction with the WOI Column Width MSB Register, forms the Width 11-bit WOI Column Width wcw[10:0] Desired = wcwd +1 Table 37: WOI Column Width LSB Register (4Ch)
11111111b 1280 Columns
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Integration Time Control (4Eh 4Fh)
which the user controls the integration time and frame time for the output data stream. By adding additional rows or columns as `blanking' to the WOI to form the Virtual Frame, the user can control the amount of blanking in both horizontal and vertical space.
The integration Time registers control the integration time for the pixel array. Integration time is measured in Virtual Row times. Refer to Figure 8 on page 13 for a pictorial description of the Virtual Frame and its relationship to the WOI Frame. A Virtual Frame is the mechanism by
NOTE: The upd bit of Reg 4Eh is used to indicate a change to cint[13:0]. Since multiple I2C writes may be needed to complete desired frame to frame integration time changes, the upd bit signals that all desired programming has been completed, and to apply these changes to the next frame captured. This prevents undesirable changes in integration 2 time that may result from I C writes that span the "End of Frame" boundary. This upd bit has to be toggled from its previous state in order for the new value of cint[13:0] to be accepted/updated by the sensor and take effect. i.e. If its previous state is "0", when writing a new cint value, first write cint[7:0] to register 4Fh, then write both cint [13:8] and "1" to the upd bit to register 4Eh. Integration Time = (cintd + 1) * (vcwd + shAd +shBd +19) * MCLKperiod where vcwd is defined in registers 52h and 53h, Table 35 and Table 36 on page 60.
(NOTE ABOVE LEFT IN SINGLE COLUMN FORMAT FOR CONSISTENCY WITH OTHER "NOTES")
Address 4Eh 7 (msb) x Bit Number 7 6 5-0 6 upd 5 cint[13]
Integration Time MSB
4 cint[12] 3 cint[11] 2 cint[10] 1 cint[97]
Default 04h 0 (lsb) cint[8] Reset State xb 0b 000100b
Function Description Unused Unused Update This bit must be toggled from its previous state to apply cint to the integration time counter.
Integration In conjuction with the Integration Time LSB Register, forms the 14-bit Integration Time cint[13:0]. Time Table 38: Integration Time MSB Register (4Eh)
Address 4Fh 7 (msb) cint[7] Bit Number 7-0 6 cint[6] 5
Integration Time LSB
4 cint[4] 3 cint[3] 2 cint[2] 1 cint[1]
Default FFh 0 (lsb) cint[0] Reset State
cint[5]
Function Description
In conjuction with the Integration Time MSB Register, forms Integration 11111111b the 14-bit Integration Time cint[13:0]. Time 1280 Rows Integration Time = (cintd +1) * Trow
Table 39: Integration Time LSB Register (4Fh)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Programmable Virtual Frame (50h 53h)
than are in the Virtual Frame then the integration time will be clipped to the number of rows in the virtual frame. The user should be careful to create a Virtual Frame that is larger than the WOI. There is no logic in the sensor interface to prevent the user from defining a Virtual Frame smaller than the WOI. Therefore, pixel data may be lost. The Virtual Frame must be at least 1 row and 118 columns larger than the WOI.
A Virtual Frame is the mechanism by which the user controls the integration time and frame time for the output data stream. By adding additional rows or columns as `blanking' to the WOI to form the Virtual Frame, the user can control the amount of blanking in both horizontal and vertical space. Both the Virtual Frame Row Depth, vrd[13:0], and the Virtual Frame Column Width, vcw[13:0], have a range of 0d to 16384d. The Virtual Frame defines the maximum integration time. If the integration register is programmed with more rows
Address 52h 7 (msb) x Bit Number 7-6 5-0 6 x
Virtual Frame Column Width MSB
5 vcw[13] Description Unused 4 vcw[12] 3 vcw[11] 2 vcw[10] 1 vcw[9]
Default 05h 0 (lsb) vcw[8] Reset State xxb 000101b
Function Unused
In conjunction with the Virtual Frame Column Width Virtual Column LSB Register, forms the 14-bit Virtual Frame Column Width Width vcw[13:0]. Table 40: Virtual Frame Row Depth MSB (50h)
Address 53h 7 (msb) vcw[7] Bit Number 6
Virtual Frame Column Width LSB
5 vcw[5] Description 4 vcw[4] 3 vcw[3] 2 vcw[2] 1 vcw[1]
Default 13h 0 (lsb) vcw[0] Reset State
vcw[6] Function
7-0
Virtual Column Width
In conjunction with the Virtual Frame Column Width MSB Register, forms the 14-bit Virtual Frame 00010011b 1300 Column Width vcw[13:0]. WOI is always top-left justified in Virtual Frame. Columns vcwd minimim = wcwd +11
Table 41: Virtual Frame Row Depth LSB (51h)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
Address 52h 7 (msb) x Bit Number 7-6 5-0 6 x
Virtual Frame Column Width MSB
5 vcw[13] Description Unused 4 vcw[12] 3 vcw[11] 2 vcw[10] 1 vcw[9]
Default 05h 0 (lsb) vcw[8] Reset State xxb 000101b
Function Unused
In conjunction with the Virtual Frame Column Width Virtual Column LSB Register, forms the 14-bit Virtual Frame Width Column Width vcw[13:0]. Table 42: Virtual Frame Column Width MSB (52h)
Address 53h 7 (msb) vcw[7] Bit Number 6
Virtual Frame Column Width LSB
5 vcw[5] 4 vcw[4] 3 vcw[3] Description In conjunction with the Virtual Frame Column Width MSB Register, forms the 14-bit Virtual Frame Column Width vcw[13:0]. WOI is always top-left justified in Virtual Frame. vcwd minimim = wcwd +11 2 vcw[2] 1 vcw[1]
Default 13h 0 (lsb) vcw[0] Reset State 00010011b 1300 Columns
vcw[6] Function
7-0
Virtual Column Width
Table 43: Virtual Frame Column Width LSB (53h)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS SOF and VCLK Delay Registers (54h and 55h)
This adjust can be used to vary the sync positions (rising and falling edges) relative to valid pixel data. In this way an acquisition system that uses the sync pulses for display can be shifted to add or avoid image borders. Adjusting the position or length of the SOF or VCLK sync does NOT alter the Frame Rate, the sync signal is simply shifted and overlaps the valid line and pixel data. Moving
Address 54h 7 (msb) sofd[7] Bit Number 7-0 SOF Delay Delay = sofdd * 0.5 MCLK's Table 44: SOF Delay Register (54h) 6 sofd[6] Function 5 sofd[5] Description 4 sofd[4] 3 sofd[3] 2 sofd[2] 1 sofd[1]
the rising edge of the SOF will also move the rising edge of the VCLK. This is so that the VCLK sync does not occur before the SOF pulse. The delay adjust is in 1/2 cycles, it takes two programmed counts to delay the rising edge by one image pixel. These delays are measured from the change of the row address, which is not directly observable except to set the delay to 0.
Default 4Ch 0 (lsb) sofd[0] Reset State 01001100b
SOF Delay
Address 55h 7 (msb) vckd[7] Bit Number 7-0 6 vckd[6] Function 5 vckd[5] Description
VCLK Delay
4 vckd[4] 3 vckd[3] 2 vckd[2] 1 vckd[1]
Default 02h 0 (lsb) vckd[0] Reset State
VCLK Delay Delay = vckdd * 0.5 MCLK's Table 45: VCLK Delay Register (55h)
00000010b
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS SOF & VCLK Width Register (56h)
The SOF & VCLK register moves the falling edge of the sync pulses. The widths can be adjusted for maximum compatibility with the frame capture
Address 56h 7 (msb) x Bit Number 7-4 3-2 Unused Unused 6 x 5 x 4 x 3 sofw[1] 2 sofw[0] 1 vckw[1]
device. The sofw bit adjusts the width of the SOF sync and vckw adjusts the width of the VCLK pulse.
Default 0Eh 0 (lsb) Vckw(0) Reset State xxxxb
SOF & VCLK Width
Function Description
SOF Contro 00b = 1 MCLK Wide 01b = 8 MCLKs Wide 10b = 64 MCLKs Wide 11b = Full Row Wide 11b
1-0
VCLK Control
00b = 1 MCLK Wide 01b = 8 MCLKs Wide 10b = 64 MCLKs Wide 11b = Full Row Wide Table 46: SOF & VCLK Width Register (56h) 10b
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Readout Direction Register (57h)
This register allows the user to change the direction of readout of the columns or rows. This can be used to compensate for and orientation of the imager in the optical system. The rrc when enabled causes the column data to be readout in the reverse direction as compared to the normal readout direction. The rrr when enabled causes the row data to be readout in the reverse direction as compared to the normal readout direction. The normal readout direction of the imager is shown in Figure 2 on page 7.
Address 57h 7 (msb) x Bit Number 7-4 3-2 1 Unused FUO Reverse Unused 6 x Function 5 x Description
Readout Direction
4 x 3 FUO 2 FUO 1 rrr
Default 04h 0 (lsb) rrc Reset State xxxxb 01b 0b
Factory Use Only 0b = Normal Readout (Bottom to Top)
Readout Row 1b = Rows Readout in reverse order (Top to Bottom) 0 Reverse Readout Col 0b = Normal Readout (Left to Right) 1b = Cols readout in reverse order (Right to Left) Table 47: Readout Direction Register (57h) 0b
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Internal Timing Control Registers (5Fh and 60h)
These registers are used to define the size of internal timing pulse widths shA (sample & hold sample) and shB (sample & hold reset). In default, both are 10 MCLKs wide. A maximum of 64 MCLKs can be programmed for the shA delay and another 64 MCLKs for the shB delay. Writing 00h to either register will provide the maximum timing delay of 64 MCLKs.
Address 5Fh 7 (msb) x Bit Number 7-6 5-0 Unused shA Unused 6 x 5
Internal Timing Control
4 shA[4] 3 shA[3] 2 shA[2] 1 shA[1]
Default 0Ah 0 (lsb) shA[0] Reset State xxxxb 001010b
shA[5]
Function Description
shA[5:0]=000000b=64 MCLKs Wide shs[5:0]=000001b=1d MCLKs Wide shA[5:0]=000001b=1d MCLKs Wide shA[5:0]=000010b=2d MCLKs Wide shA[5:0]=000011b=3d MCLKs Wide | | shA[5:0]=111111b=63d MCLKs Wide
Table 48: Internal Timing Control Register (5Fh) Address 60h 7 (msb) x Bit Number 7-6 5-0 Unused shB Unused shB[5:0]=000000b=64 MCLKs Wide shs[5:0]=000001b=1d MCLKs Wide shB[5:0]=000001b=1d MCLKs Wide shB[5:0]=000010b=2d MCLKs Wide shB[5:0]=000011b=3d MCLKs Wide | 6 x Function 5 shB[5] Description 4 shB[4] 3 shB[3] 2 shB[2] 1 shB[1]
Internal Timing Control
Default 0Ah 0 (lsb) shB[0] Reset State xxxxb 001010b
Table 49: Internal Timing Control Register (60h)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Clamp Control and HCLK Delay Register (64h)
This register is used to delay the position of the first HCLK, which corresponds to the first valid pixel in each row. The delay is only useful when the HCLK is not continuous. This delay can be used to compensate for any latency in the user's capture device. In addition, this register also allows one to disable the Frame Clamp if desired for specific applications (see "Frame Rate Clamp (FRC)"on page 16).
Address 64h 7 (msb) x Bit Number 7 6 Unused 6 fce[6] Function
Clamp Control and HCLK Delay
5 FUO Description 4 FUO 3 FUO 2 hckd[2] 1 hckd[1]
Default 5Ch 0 (lsb) hckd[0] Reset State
Unused
xb 1b
Frame Clamp 0b = Clamp Disabled Enable 1b = Clamp Enabled FUO FUO
5-3 2-0
011b 100b
HCLK Delay Syncs rising edge of HCLK to valid data from ADC Delay = ((hckd[d]-4) x 0.5) - 16 MCLKs
Table 50: Clamp Control and HCLK Delay Register (64h)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Encoded Sync Register (65h)
It is possible to capture the image data without the SOF, VCLK, or HCLK syncs. Once the encoded Syncs are enabled, 4 10bit words are placed into the data stream adding 4 pixel times per row. The inserted codes tells the user when the row starts and what type of row it is. Figure 24 on page 34 illustrates the encoded syncs in a data stream. The vcb bit allows the user to force all the Blanking data coming out of the ADC to be 0. The vcg bit allows the user to enable/disable encoded sync data in the output stream (see Table 2 on page 12). The vcc bit allows the user to clip the output active pixel data to lie between 1 and 1022 to avoid confusion with the encoded sync data in the output stream.
Address 65h 7 (msb) x Bit Number 7 6 Unused Blanking Unused 6 vcb Function 5 vsg Description
Encoded Sync Control
4 vcc 3 FUO 2 FUO 1 FUO
Default 00h 0 (lsb) FUO Reset State xb 0b
0b = Dark Pixels Used for Blanking 1b = H-Blanking and V-Blanking are forced to Dout=0
5
Encoded Sync 0b = Normal Readout Enable 1b = Enable Encoded Syncs in Data Stream Data Clipping 0b = Normal Readout 1b = Pixel Data of 0 and 1023 will be clipped to 1 and 1022
0b
4
0b
3-0
FUO
Factory Use Only Table 51: Encoded Sync Register (65h)
0000b
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS Mod64 Column Offset Correction Register (80h-BFh)
The Mod64 Column Offset registers are used to reduce/eliminate collimated fixed pattern noise (FPN). There are 64 registers that can be programmed with individual offset values. They will be applied to all the columns on a single image frame on a Modular 64 basis. i.e. Register 80h Column offset will be applied to Column 0 , 64, 128..., Register 81h Column offset will be applied to Column 1, 65, 129..., Register BFh Column offset will be applied to Column 63, 127, 191...etc. The Column DOVA stage has only six bits of programmability. Registers 20h is added to the value in 80h BFh for that column. The final sum is truncated to 32d.
Address 80-BFh 7 (msb) x Bit Number 7-6 5 Unused Sign 6 x Function
Mod64 Column Offset Correction
5 mdd[5] Description 4 mdd[4] 3 mdd[3] 2 mdd[2] 1 mdd[1]
Default 00h 0 (lsb) mdd[0] Reset State
Unused 0b = Positive Offset 1b = Negative Offset
xxb 0b
4-0
Column Offset
Offset = 2.6 * mddd (64 step @ 2.6mV/step)
00000b
Table 52: Mod64 Column Offset Correction Register (80h-BFh)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS STORAGE AND HANDLING Storage Conditions
Description Temperature Humidity Notes: 1. 2. Minimum -55 ---Maximum +70 95+/-5 Units Conditions @10%+/5%RH @49+/-2C Temp. Notes 1,2 1,2
C
%RH
The tolerance on all relative humidity values is provided due to limitations in measurement instrument accuracy. The image sensor shall meet the specifications of this document after storage for 15 days at the specified conditions.
Caution: This device contains limited protection against Electrostatic Discharge (ESD) Devices should be handled in accordance with strict ESD protection procedures for Class 2 devices (JESD22 Human Body Model) or Class B (Machine Model). Refer to Application Note MTD/PS-0224, "Electrostatic Discharge Control" Caution: Improper cleaning of the cover glass may damage these devices. Refer to Application Note MTD/PS-0237, "Cover Glass Cleaning for Image Sensors"
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS REFLOW SOLDERING RECOMMENDATIONS
When using a reflow soldering system, the thermal profile shown in Figure 28 below is the maximum thermal stress conditions recommended. If the temperature and/or time of the soldering process exceeds that of the recommended profile, there is a possibility of damaging the sensor due to thermal stress.
225oC Peak Temperature < 3o/sec 215oC 20 - 30 sec max
Package Temperature
Pre-heat 150oC +/- 10oC
60 to 100 sec
< 3o/sec
Time
Figure 28: Recommended Reflow Soldering System Thermal Profile
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
MECHANICAL DRAWINGS
A C B 0.0 1 0 M A B M C M
B 4X R 48X D 0 .0 0 6 M A B C
47X
H
0. 0 1 0 M A B M C M
48 1
K
J
C E 48X R1 REF 44X G A
F
Dimension A B C D E F G H J K R R1
Minimum (inches) 0.555 0.525 --0.016 0.055 0.075
Nominal (inches) 0.56 0.54 --0.02 0.061 0.085 0.04 BSC
Maximum (inches) 0.572 0.545 0.094 0.024 0.067 0.095
0.033 0.555 0.525
0.04 0.56 0.54 0.008 REF 0.028 REF
0.047 0.572 0.545
Figure 29: 48-Pin Terminal Ceramic Leadless Chip Carrier (Bottom View)
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS
48 Ceramic LCC - Matrix Format
Metric (mm) Dimension A B C D E F G H J Description Glass (Thickness) Cavity (Depth) Die - Si (Thickness) Bottom Layer (Thickness) Die Attach - bondline (Thickness) Glass Attach - bondline (Thickness) Imager to Lid - outer surface (d) Imager to Lid - inner surface (d) Imager to seating plane - of pkg Min 0.5 0.9906 0.705 0.381 0.0127 0.00635 0.70115 0.20115 1.0987 1.87795 1.397 Nominal 0.55 1.1176 0.725 0.4318 0.0254 0.0254 0.9426 0.3926 1.1822 2.1248 1.5494 Max 0.6 1.2446 0.745 0.4826 0.0508 0.0508 1.1777 0.5777 1.2784 2.378 1.7018 Min. 19.69 39.00 27.76 15.00 0.50 0.25 27.60 7.92 43.26 73.93 55.00 English (mils) Nominal 21.65 44.00 28.54 17.00 1.00 1.00 37.11 15.46 46.54 83.65 61.00 Max 23.62 49.00 29.33 19.00 2.00 2.00 46.37 22.74 50.33 93.62 67.00
A+B+F+D Pkg (Th - total) B+D Base (Th)
Reference Notes: 1 mil = 25.4m 1 mm = 39.37 mil Table 53: 48 Ceramic LCC - Matrix Format
A
F - Lid Seal thickness
G B J
H
D E - Die Attach thickness C - Die
Figure 30: CLCC-IB package vertical Dimensioning
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IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS QUALITY ASSURANCE AND RELIABILITY
Quality Strategy: All image sensors will conform to the specifications stated in this document. This will be accomplished through a combination of statistical process control and inspection at key points of the production process. Typical specification limits are not guaranteed but provided as a design target. For further information refer to ISS Application Note MTD/PS0292, Quality and Reliability. Replacement: All devices are warranted against failure in accordance with the terms of Terms of Sale. This does not include failure due to mechanical and electrical causes defined as the liability of the customer below. Liability of the Supplier: A reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the customer. Liability of the Customer: Damage from mechanical (scratches or breakage), electrostatic discharge (ESD) damage, or other electrical misuse of the device beyond the stated absolute maximum ratings, which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer. Cleanliness: Devices are shipped free of mobile contamination inside the package cavity. Immovable particles and scratches that are within the imager pixel area and the corresponding cover glass region directly above the pixel sites are also not allowed. The cover glass is highly susceptible to particles and other contamination. Touching the cover glass must be avoided. See ISS Application Note MTD/PS-0237, Cover Glass Cleaning, for further information. ESD Precautions: Devices are shipped in staticsafe containers and should only be handled at static-safe workstations. See ISS Application Note MTD/PS-0224, Electrostatic Discharge Control for handling recommendations. Reliability: Information concerning the quality assurance and reliability testing procedures and results are available from the Image Sensor Solutions and can be supplied upon request. For further information refer to ISS Application Note MTD/PS-0292, Quality and Reliability. Test Data Retention: Image sensors shall have an identifying number traceable to a test data file. Test data shall be kept for a period of 2 years after date of delivery. Mechanical: The device assembly drawing is provided as a reference. The device will conform to the published package tolerances.
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Email: imagers@kodak.com
IMAGE SENSOR SOLUTIONS IMAGE SENSOR SOLUTIONS ORDERING INFORMATION Available Part Configurations
Type KAC-1310 KAC-1310 Description RGB with microlens CMY with microlens Glass Configuration Sealed Sealed
Please contact Image Sensor Solutions for available part numbers. Address all inquiries and purchase orders to: Image Sensor Solutions Eastman Kodak Company Rochester, New York 14650-2010 Phone: (585) 722-4385 Fax: (585) 477-4947 E-mail: imagers@kodak.com Kodak reserves the right to change any information contained herein without notice. All information furnished by Kodak is believed to be accurate. WARNING: LIFE SUPPORT APPLICATIONS POLICY Kodak image sensors are not authorized for and should not be used within Life Support Systems without the specific written consent of the Eastman Kodak Company. Product warranty is limited to replacement of defective components and does not cover injury or property or other consequential damages.
Revision Changes
No. 4 Date 11/6/02 Description of Revision Updated to new format. Page 71: Revised ESD statements. Page 75: Updated Cover Glass Cleaning Application Note document reference number.
76
KAC-1310 Rev 4
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www.kodak.com/go/imagers
585-722-4385
Email: imagers@kodak.com

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