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| EliteMT DRAM M11L416256SA 256 K x 16 DRAM EDO PAGE MODE FEATURES X16 organization EDO (Extended Data-Output) access mode 2 CAS Byte/Word Read/Write operation Single 3.3V ( 10%) power supply LVTTL-compatible inputs and outputs 512-cycle refresh in 8ms Refresh modes : RAS only, CAS BEFORE RAS (CBR) and HIDDEN capabilities Self-refresh capability JEDEC standard pinout Key AC Parameter tRAC -35 35 tCAC 10 tRC 65 tPC 14 ORDERING INFORMATION - PACKAGE 40-pin 400mil SOJ 44 / 40-pin 400mil TSOP (Type II) PRODUCT NO. PACKING TYPE COMMENTS M11L416256SASOJ/TSOPII 35 TG M11L416256SA35 JP Pb-free GENERAL DESCRIPTION The M11L416256 series is a randomly accessed solid state memory, organized as 262,144 x 16 bits device. It offers Extended Data-Output , 3.3V( 10%) single power supply. Access time (-35) , self-refresh and package type (SOJ, TSOP II) are optional features of this family. All these family have CAS - before - RAS , RAS -only refresh and Hidden refresh capabilities. Two access modes are supported by this device: Byte access and Word access. Use only one of the two CAS and leave the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used. CASL transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH transiting low will output or input data into the upper byte (IO8~15). PIN ASSIGNMENT SOJ Top View VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RA S NC A0 A1 A2 A3 VCC TSOP (TypeII) Top View VS S I/O1 5 I/O1 4 I/O1 3 I/O1 2 VS S I/O1 1 I/O1 0 I/O9 I/O8 NC CASL CASH OE A8 A7 A6 A5 A4 VS S VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RA S NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VS S I/O1 5 I/O1 4 I/O1 3 I/O1 2 VS S I/O1 1 I/O1 0 I/O 9 I/O 8 NC CASL CASH OE A8 A7 A6 A5 A4 VS S Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 1/16 EliteMT FUNCTIONAL BLOCK DIAGRAM M11L416256SA WE RAS CASL CASH CONTROL LOGIC DATA-IN BUFFER 16 IO0 : IO15 CLOCK GENERATOR DATA-OUT BUFFER 9 COLUMN DECODER 512 16 OE 16 9 A0 A1 A2 A3 COLUMN ADDRESS BUFFER REFRESH CONTROLER SENSE AMPLIFIERS I/O GATING 8 512 x 16 A4 A5 A6 A7 A8 9 99 ROW. ADDRESS BUFFERS(9) 9 ROW DECODER 512 x 512 x 16 MEMORY ARRAY REFRESH COUNTER 512 VBB GENERATOR VCC VSS PIN DESCRIPTIONS PIN NO. 16~19,22~26 14 28 29 13 PIN NAME A0~A8 RAS CASH CASL TYPE Input Input Input Input DESCRIPTION Address Input Row Address : A0~A8 Column Address : A0~A8 Row Address Strobe Column Address Strobe / Upper Byte Control Column Address Strobe / Lower Byte Control WE OE Input Input Input / Output Supply Ground - Write Enable Output Enable Data Input / Output Power, 3.3V Ground No Connect 27 2~5,7~10,31~34,36~39 1,6,20 21,35,40 11,12,15,30 I/O0 ~ I/O15 VCC VSS NC Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 2/16 EliteMT ABSOLUTE MAXIMUM RATINGS Voltage on Any pin Relative to Vss ... ......-0.5V to +4.6V Operating Temperature, TA (ambient) ....0 C to +70 C Storage Temperature (plastic) ..........-55 C to +150 C Power Dissipation .......................................0.8W Short Circuit Output Current ........................50mA M11L416256SA Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation of the device above those conditions indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (0 C TA 70 C ; VCC = 3.3V 10% unless otherwise noted) PARAMETER CONDITIONS SYMBOL MIN MAX UNITS NOTES Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Note : 1.All Voltages referenced to VSS 0V VIN VIH(max) 0V VOUT VCC Output(s) disable IOH = -2 mA IOL = 2 mA VCC VSS VIH VIL ILI ILO VOH VOL 3.0 0 2.0 -0.3 -10 -10 2.4 - 3.6 0 VCC +0.3 0.8 10 10 0.4 V V V V A A 1 1 1 V V PARAMETER CONDITIONS RAS , CAS cycling , tRC =min SYMBOL MAX -35 UNITS NOTES Operating Current ICC1 150 4 2 mA mA mA mA mA mA mA A 1,2 Standby Current TTL interface , RAS , CAS = VIH , DOUT =High-Z CMOS interface, RAS , CAS VCC-0.2V ICC2 RAS only refresh Current tRC = min tPC = min RAS =VIH, CAS = VIL ICC3 ICC4 ICC5 ICC6 150 150 5 150 2 1,3 1 EDO Page Mode Current Standby Current CAS Before RAS Refresh Current tRC = min RAS , CAS 0.2V, DOUT = High-Z, CMOS interface RAS = CAS = VIL, Battery Backup Current (S-ver. only) Self Refresh Current (S-ver. only) ICC7 400 WE = OE = A0~A8 = VCC -0.2 or 0.2V DQ0~DQ15 = VCC -0.2, 0.2V or open ICC8 400 A Note : 1. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS =VIL . 3. Address can be changed once or less while CAS =VIH . Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 3/16 EliteMT CAPACITANCE (Ta = 25 C , VCC = 3.3V 10%) PARAMETER SYMBOL TYP MAX M11L416256SA UNIT Input Capacitance (address) Input Capacitance ( RAS , CASH , CASL , WE , OE ) Output capacitance (I/O0~I/O15) CI1 CI2 CI / O - 5 7 10 pF pF pF AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70 C , VCC =3.3V 10%, VSS = 0V) (note 14) Test Conditions Input timing reference levels : 0.8V, 2.0V Output reference level : VOL= 0.8V, VOH=2.0V Output Load : 2TTL gate + CL (50pF) Assumed tT = 2ns PARAMETER Read or Write Cycle Time Read Write Cycle Time EDO-Page-Mode Read or Write Cycle Time EDO-Page-Mode Read-Write Cycle Time Access Time From RAS Access Time From CAS Access Time From OE Access Time From Column Address Access Time From CAS Precharge SYMBOL MIN -35 MAX UNIT NOTES tRC tRWC tPC tPCM tRAC tCAC tOAC tAA tACP tRAS tRASC tRSH tRP tCAS tCSH tCP tRCD tCRP tASR tRAH tRAD tASC tCAH tAR tRAL tRCS 65 95 14 42 35 10 10 18 20 35 35 10 25 5 30 5 10 5 0 5 8 0 5 30 18 0 17 25 10K 10K 100K ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15,18 22 22 4 5,20 13,20 20 RAS Pulse Width RAS Pulse Width (EDO Page Mode) RAS Hold Time RAS Precharge Time CAS Pulse Width CAS Hold Time CAS Precharge Time RAS to CAS Delay Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time 25 24 19 6,23 7,18 19 RAS to Column Address Delay Time Column Address Setup Time Column Address Hold Time Column Address Hold Time (Reference to RAS ) Column Address to RAS Lead Time Read Command Setup Time 8 18 18 Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 4/16 EliteMT (Continued) PARAMETER Read Command Hold Time Reference to CAS Read Command Hold Time Reference to RAS SYMBOL MIN M11L416256SA -35 MAX ns ns ns 9,15,19 9 20 10,17,20 17,26 11,15,18 15,25 15 15 15 15,19 12,20 12,20 UNIT NOTES tRCH tRRH tCLZ tOFF1 tOFF2 tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tRWD tAWD tCWD tT tREF tRPC tCSR tCHR tOEH tOES tOEHC tOEP tORD tCLCH tCOH tWHZ tRASS tRPS tCHS 0 0 3 3 15 8 0 5 30 5 9 7 0 5 30 51 34 26 2.5 10 10 10 4 4 2 2 0 5 3 3 100 65 -50 7 50 8 CAS to Output in Low-Z Output Buffer Turn-off Delay From CAS or RAS Output Buffer Turn-off to OE Write Command Setup Time Write Command Hold Time Write Command Hold Time(Reference to RAS ) Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference to RAS ) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns RAS to WE Delay Time Column Address to WE Delay Time 11 11 11,18 2,3 CAS to WE Delay Time Transition Time (rise or fall) Refresh Period (512 cycles) RAS to CAS Precharge Time CAS Setup Time(CBR REFRESH) CAS Hold Time(CBR REFRESH) OE Hold Time From WE During Read-Mode-Write Cycle OE Low to CAS High Setup Time OE High Hold Time From CAS High OE Precharge Time OE Setup Prior to RAS During Hidden Refresh Cycle Last CAS Going Low to First CAS Returning High Data Output Hold After CAS Returning Low Output Disable Delay From WE Self Refresh RAS Low Pulse width Self Refresh RAS High Precharge Time Self Refresh CAS Hold Time 1,18 1,19 16 ns ns ns 21 s ns ns 27,28 27,28 27,28 Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 5/16 EliteMT Notes : M11L416256SA 1. 2. Enables on-chip refresh and address counters. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. Assume that tRCD tRCD (max) If CAS is low at the falling edge of RAS , data-out will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS and RAS must be pulsed high. Operation within the tRCD limit ensures that tRCD (max) can be met, tRCD (max) is specified as a reference point only ; if tRCD is greater than the specified tRCD (max) limit, access time is controlled by tCAC. Operation within the tRAD limit ensures that tRAD(max) can be met. tRAD(max) is specified as a reference point only ; if tRAD is greater than the specified tRAD (max) limit, access time is controlled by tAA. Either tRCH or tRRH must be satisfied for a READ cycle. tOFF1(max) defines the time at which the output achieves the open circuit condition ; it is not a reference to VOH or VOL. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS tWCS(min) , the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD(min) , tAWD tAWD(min) and tCWD tCWD(min) , the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH ) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE -controlled) cycle. 12. Those parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY- WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFY-WRITE operation is not possible. 14. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 15. WRITE command is defined as WE going low. 16. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. 17. The I/Os open during READ cycles once tOFF1 or tOFF2 occur. 18. Referenced to the earlier CAS falling edge. 19. Referenced to the latter CAS rising edge. 20. Output parameter (I/O) is referenced to corresponding CAS input, IO0~7 by CASL and IO8~15 by CASH . 21. Last falling CAS edge to first rising CAS edge. 22. Last rising CAS edge to next cycle's last rising CAS edge. 23. Last rising CAS edge to first falling CAS edge. 24. Each CAS must meet minimum pulse width. 25. Referenced to the latter CAS falling edge. 26. All IOs controlled by OE , regardless CASL and CASH . 27. Self refresh mode is initiated by performing a CBR refresh cycle and holding RAS low for the specified tRASS. Self refresh mode is terminated by rising RAS high for a minimum time of tRPS. 28. For all of the refresh mode expect the distributed CBR refresh mode, all rows must be refreshed within the refresh rate before and after self refresh. 3. 4. 5. 6. 7. 8. 9. 10. 11. Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 6/16 EliteMT TRUTH TABLE ADDRESSES M11L416256SA FUNCTION RAS H L L L L L CASL CASH HX L L H L L HX L H L L H WE X H H H L L OE X L L L X X DQS High-Z Data-Out Lower Byte, Data-Out Upper Byte, Data-Out Data-In Lower Byte, Data-In , Upper Byte, High-Z Lower Byte, High-Z , Upper Byte, Data-In Data-Out, Data-In Data-Out Data-Out Data-Out NOTES ROW X ROW ROW ROW ROW ROW COL X COL COL COL COL COL Standby Read : Word Read : Lower Byte Read : Upper Byte Write : Word (Early Write) Write : Lower Byte (Early) Write : Upper Byte (Early) Read-Write 1st Cycle EDO-Page-Mode 2nd Cycle Read Any Cycle EDO-Page-Mode 1st Cycle Write 2nd Cycle EDO-Page-Mode 1st Cycle Read-Write 2nd Cycle Hidden Refresh RAS -Only Refresh L L L L L L L L L LHL L HL HL H L HL HL LH HL HL HL HL L H L L L L HL HL LH HL HL HL HL L H L L L X ROW ROW ROW COL COL COL COL HLLH H H H L L L L L X X 1, 2 2 2 2 1 1 1, 2 1, 2 2 ROW COL COL Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out High-Z HLLH HLLH H X H H L X X X ROW COL COL ROW ROW X X COL CBR Refresh Self-Refresh X X High-Z High-Z 3 3 *Note : 1. These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active). 2. These READ cycles may also be BYTE READ cycles (either CASL or CASH active). 3. Only one CAS must be active ( CASL or CASH ). Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 7/16 EliteMT READ CYCLE tRC tRAS VIH RAS VIL M11L416256SA tRP tCSH tCRP CA SL ,C AS H VIH VIL tRCD tRSH tCAS tRRH tCLCH tAR tASR ADDR VIH VIL ROW tRAD tRAH tASC tRAL tCAH COLUMN ROW tRCS WE VIH VIL tRCH tAA tRAC tCAC tCLZ I/O VO H VO L OPEN NO TE1 tOFF1 VAL ID DATA OPE N tO AC OE VIH VIL tOFF2 EARLY WRITE CYCLE tRC tRAS RAS VIH VIL tRP tCRP CASL ,C ASH VIH VIL tRCD tCSH tRSH tCAS tCLCH tAR tASR ADDR VIH VIL ROW tRAD tRAH tASC COLUMN tRAL tCAH ROW tWCS tCWL tRWL tWCR tWCH tWP WE VIH VIL tDS I/O VIH VIL VIH VIL tDHR tDH VAL ID DATA OE DON'T CARE UNDEFINED Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 8/16 EliteMT READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) tRWC t RAS RAS VIH VIL M11L416256SA tRP tCRP CASL,CASH VIH VIL tRCD tCSH tRS H tCAS,tCLCH tASR ADDR VIH VIL ROW tAR tRAD tRAH tASC COLUMN t RAL t CAH ROW tRCS VIH VIL tRWD tCWD tAWD tCWL tRWL tWP WE tAA tRAC tCAC tCLZ I/O VI/O H VI/O L OPEN VAL ID DO UT tDS tDH VALI D DIN tO AC OE VIH VIL tOFF 2 tOEH EDO-PAGE-MODE READ CYCLE tRASC RAS VIH VIL tRP tCRP CASL ,C AS H VIH VIL tCSH tRCD tPC tCAS , tCLCH tCP (NOTE2) tCAS,tCLCH tCP tRSH tCAS, t CLCH tCP tAR t RAD tASR tRAH ADDR VIH VIL ROW tRAL tASC tCAH tASC t CAH tASC tCAH ROW COLUMN COLUMN COLUMN tRCS WE VIH VIL tRCH tRRH tAA tRAC tCAC tCLZ VO H I/O VO L OPEN tAA t ACP tCAC tCOH VAL ID D ATA VALID DATA tAA tACP tCAC tCLZ tOEHC tO AC tOFF 2 tOES tOEP VAL ID D ATA NO TE1 tOFF 1 OPEN tO AC tOES OE VIH VIL tOFF 2 DON'T CARE UNDEFINED *NOTE : 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of CAS . Both measurements must meet the tPC specification. Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 9/16 EliteMT EDO-PAGE-MODE EARLY-WRITE CYCLE tRASC RAS VIH VIL M11L416256SA tRP tCSH tCRP CASL ,CASH VIH VIL tRCD tCAS,tCLCH tPC (NOTE1) tCAS, tCLCH tCP tCP tRSH tCAS,tCLCH tCP tAR tRAD tASR ADDR VIH VIL tRAH tASC tCAH tASC tCAH tASC tRAL tCAH ROW ROW COLUMN COLUMN COLUMN tCWL tWCS tWCH tWP tWCS tCWL tWCH tWP tWCS tCWL tWCH tWP WE VIH VIL tDS I/O VIH VIL tWCR tDHR tDH tRWL tDS tDH tDS tDH VAL ID DATA VAL ID DATA VAL ID DATA OE VIH VIL EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) tRASC RAS VIH VIL tRP tCSH tCRP CASL ,CASH VIH VIL tRCD tCAS,tCLCH tCP tPCM tCAS, tCLCH tRSH tCP tCAS,tCLCH tCP tAR tRAD tASR ADDR VIH VIL tRAH tASC tCAH tASC tCAH COLUMN tASC tRAL tCAH ROW ROW COLUMN COLUMN tRWD tRCS tCWL tWP tCWL tWP tAWD tCWD tAWD tCWD tRWL tCWL tWP tAWD tCWD WE VIH VIL tAA tRAC tCAC tCLZ I/O VI/O H VI/O L VALI D VALI D DOUT DIN tAA tDH tDS tACP tCAC tCLZ VALI D VALI D DOUT D IN tAA tDH tDS tACP tCAC tCLZ VALID VALI D DOUT DIN tDH tDS tOFF2 tO AC OE VIH VIL tOFF tO AC 2 tO AC tOFF2 tOEH DON'T CARE UNDEFINED Note : 1. tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of CAS . Both measurements must meet the tPC specification. Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 10/16 EliteMT EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY-WRITE) tRASC RAS VIH VIL M11L416256SA tRP tCSH tCRP CASL ,C AS H VIH VIL tRCD tPC tCAS tCP tCP tCAS tCP tRSH tCAS tCP tAR tRAD tASR tRAH ADDR VIH VIL ROW tRAL tCAH tAS C tCAH tASC tCAH ROW tASC COLUMN(A) COLUMN(B) COLUMN(N) tRCS WE VIH VIL tRCH tWCS tWCH tAA tRAC tCAC tACP tAA tWHZ tCAC tCOH VA L ID DATA( A) VALID DATA(B ) tDS tDH I/O VI/OH VI/OL OPEN VALID DATA IN tO AC OE VIH VIL RAS ONLY REFRESH CYCLE (ADDR = A0~A8 ; OE , WE = DON'T CARE) tRC tRAS RAS VIH VIL tRP tCRP CASL,CASH VIH VIL tRPC tASR ADDR VIH VIL ROW tRAH ROW I/O VO H VO L OPE N DON'T CARE UNDEFINED Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 11/16 EliteMT CBR REFRESH CYCLE (A0~A8 ; OE = DON'T CARE) tRP RAS VIH VIL M11L416256SA tRAS tRP tRAS tRPC tCP CASL ,C AS H VIH VIL tCSR tCHR tRPC tCSR tCHR I/O OPEN tRCH WE VIH VIL HIDDEN REFRESH CYCLE ( WE = HIGH ; OE = LOW) (READ) (REF RESH) tRAS RAS VIH VIL tRP tRAS tCRP CASL ,C AS H VIH VIL tRCD tRSH tCHR tAR tRAD tASR ADDR VIH VIL ROW tRAH tASC tRAL tCAH COLUMN tAA tRAC tCAC tCLZ I/O VO H VO L OPEN VALID DATA NO TE1 tOFF1 OPEN OE VIH VIL tO AC tORD tOFF2 DON'T CARE UNDEFINED Note : 1. tOFF1 is reference from the rising edge of RAS or CAS , whichever occurs last. Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 12/16 EliteMT SELF REFRESH CYCLE ( OE = DON'T CARE) tRP RAS VIH VIL M11L416256SA tRASS tRPS tRPC CASL ,CASH VIH VIL tCSR tRPC tCHS tCRP tCP tASR ADDR VIH VIL I/O VO H VO L OPEN tRCH WE VIH VIL DON'T CARE UNDEFINED Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 13/16 EliteMT PACKING 40-LEAD SECTION 40 M11L416256SA DIMENSIONS SOJ(400mil) I D 21 0.050" Max. b 2 E1 E b Detail "A" 1 20 c A2 Seating Plain Detail "A" e 0.024" Min. A A1 1 E R 2 1 SECTION 40 II D 21 0.050" Max. b 2 E1 E b Detail "A" 1 20 c A2 Seating Plain Detail "A" e 0.024" Min. A A1 1 E R 2 1 Symbol A A1 A2 b b2 c e Dimension in mm Min Norm Max 3.250 3.510 3.760 2.080 2.790 REF 0.380 0.460 0.560 0.635 REF 0.180 0.250 0.360 1.270 BSC Dimension in inch Symbol Dimension in mm Min Norm Max Min Norm Max 0.128 0.138 0.148 E 10.920 11.176 11.430 0.082 E1 10.030 10.160 10.290 0.110 REF E2 9.40 BSC 0.015 0.018 0.022 R1 0.760 0.890 1.020 0.025 REF 1 0 10 0.007 0.010 0.014 0.050 BSC D 25.91 26.040 26.290 Dimension in inch Min Norm Max 0.430 0.440 0.450 0.395 0.400 0.405 0.370 BSC 0.030 0.035 0.040 0 1.02 1.025 10 1.035 Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 14/16 EliteMT PACKING 40 / 44-LEAD DIMENSIONS TSOP(II) DRAM(400mil) M11L416256SA Symbol A A1 A2 b b1 c c1 D ZD E E1 L L1 e Dimension in mm Min 0.05 0.95 0.30 0.30 0.12 0.10 18.28 11.56 10.03 0.40 18.41 0.805 REF 11.96 10.29 0.69 11.76 10.16 0.59 0.80 REF 0.80 BSC O ~ 7 REF 0.35 1.00 Norm Max 1.20 0.15 1.05 0.45 0.40 0.21 0.16 18.54 Dimension in inch Min 0.002 0.037 0.012 0.012 0.005 0.004 0.720 0.455 0.395 0.016 0.725 0.0317 REF 0.463 0.400 0.023 0.031 REF 0.0315 BSC O ~ 7 REF 0.471 0.4 0.027 0.014 0.039 Norm Max 0.047 0.006 0.042 0.018 0.016 0.008 0.006 0.730 Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 15/16 EliteMT Important Notice All rights reserved. M11L416256SA No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of EliteMT. The contents contained in this document are believed to be accurate at the time of publication. EliteMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by EliteMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of EliteMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. EliteMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 16/16 |
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