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HANBit
HMD4M144D9WG
64Mbyte(4Mx144) 200-pin ECC Mode 4K Ref. DIMM Design 5V Part No. HMD4M144D9WG GENERAL DESCRIPTION
The HMD4M144D9WG is a 4Mbit x 144bit dynamic RAM high-density memory module. The module consists of eight CMOS 4Mx16bit DRAMs in 50-pin TSOP packages and one CMOS 4M x 16bit DRAM in 50pin TSOP package mounted on a 200-pin, double-sided, FR-4-printed circuit board. A 0.1uF or 4.7uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a dual In-line memory module with edge connections and is intended for mounting in to 200-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
FEATURES
w Access times : 50, 60 ns w High -density 64MByte design w Part identification - HMD4M144D9WG (4K Cycles/64ms Ref, Gold) w Single +5V 0.5V power supply w JEDEC Standard pinout w ECC mode operation w TTL compatible inputs and output
OPTIONS w Timing 50ns access 60ns access w Packages 200-pin DIMM
MARKING -5 -6 D
PERFORMANCE RANGE
Speed -5 -6 tRAC 50ns 60ns tCAC 13ns 15ns tRC 90ns 110ns tPC 35ns 40ns
PIN NAMES
Pin Name BA0-BA11 DQ0-DQ143 BWE Function Address Input Data In/Out Read/Write Enable Pin Name BRAS BCAS1,BCAS2 Vcc Function Row Address Strobe Column Address Strobe Power(+5V) Pin Name Vss NC Function Ground No Connection
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HMD4M144D9WG
PIN ASSIGNMENT
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol Vss Vss DQ0 DQ36 DQ1 DQ37 DQ2 DQ38 DQ3 DQ39 DQ4 DQ40 DQ5 DQ41 DQ6 DQ42 Vcc Vcc DQ7 DQ43 DQ8 DQ44 DQ9 DQ45 DQ10 DQ46 DQ11 DQ47 DQ12 DQ48 DQ13 DQ49 Vss Vss PIN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Symbol DQ14 DQ50 DQ15 DQ51 DQ16 DQ52 DQ17 DQ53 DQ18 DQ54 DQ19 DQ55 DQ20 DQ56 Vcc Vcc DQ21 DQ57 DQ22 DQ58 DQ23 DQ59 DQ24 DQ60 DQ25 DQ61 DQ26 DQ62 DQ27 DQ63 Vss Vss DQ28 DQ64 PIN 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol DQ29 DQ65 DQ30 DQ66 DQ31 DQ67 DQ32 DQ68 DQ33 DQ69 DQ34 DQ70 Vcc Vcc DQ35 DQ71 /BCAS1 /BCAS2 /BRAS NC NC NC NC NC BA0 BA1 BA2 BA3 BA4 BA5 Vss Vss PIN 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 Symbol Vss Vss BA6 BA7 BA8 BA9 BA10 BA11 NC /BWE NC NC Vss Vss Vss Vss DQ72 DQ108 Vcc Vcc DQ73 DQ109 DQ74 DQ110 DQ75 DQ111 DQ76 DQ112 DQ77 DQ113 DQ78 DQ114 DQ79 DQ115 PIN 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol Vss Vss DQ80 DQ116 DQ81 DQ117 DQ82 DQ118 DQ83 DQ119 DQ84 DQ120 DQ85 DQ121 DQ86 DQ122 Vcc Vcc DQ87 DQ123 DQ88 DQ124 DQ89 DQ125 DQ90 DQ126 DQ91 DQ127 DQ92 DQ128 DQ93 DQ129 Vss Vss PIN 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Symbol DQ94 DQ130 DQ95 DQ131 DQ96 DQ132 DQ97 DQ133 DQ98 DQ134 DQ99 DQ135 DQ100 DQ136 Vcc Vcc DQ101 DQ137 DQ102 DQ138 DQ103 DQ139 DQ104 DQ140 DQ105 DQ141 DQ106 DQ142 DQ107 DQ143 Vss Vss
200PIN DIMM TOP VIEW
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FUNCTIONAL BLOCK DIAGRAM U1
DQ0-15 A0-A11
HMD4M144D9WG
/CAS2 /RAS
/CAS /RAS /OE W
DQ0-DQ15
/CAS /RAS /OE W
U2
DQ16-32 A0-A11 DQ16-DQ31
/CAS /RAS /OE W
U10
DQ32-47 A0-A11 DQ32-DQ47
/CAS /RAS /OE W
U9
DQ48-63 A0-A11 DQ48-DQ63
/CAS1 /CAS2 /RAS /OE W
U3
DQ63-79 A0-A11 DQ64-DQ79
/CAS1
/CAS /RAS /OE W
U4
DQ80-95 A0-A11 DQ80-DQ95
/CAS /RAS /OE W
U5
DQ96-111 A0-A11 DQ96-DQ111
/CAS /RAS /OE W
U7
DQ112-127 A0-A11 DQ112-DQ127
/CAS /RAS /OE W /WE A0-A11
U6
DQ128-143 A0-A11
DQ128-DQ143
Vcc Vss
0.1uF or 4.7uF Capacitor for each DRAM
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HMD4M144D9WG
A /RAS /CAS1 /CAS2 /WE
74FCT162244
/BA /BRAS /BCAS1 /BCAS2 /BWE
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG RATING -1V to 7.0V -1V to 7.0V 9W -55oC to 150oC
Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 4.5 0 2.4 -1.0 TYP. 5.0 0 MAX 5.5 0 Vcc+1 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS
SYMBOL ICC1 SPEED -5 -6 ICC2 ICC3 Don't care -5 -6 ICC4 -5 -6 ICC5 ICC6 Don't care -5 -6
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MIN -
MAX 396 366 12 396 366 396 366 6 990 900
UNITS mA mA mA mA mA mA mA mA mA mA
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Il(L) IO(L) VOH VOL -60 -5 2.4 -
HMD4M144D9WG
40 5 0.4 A A V V
ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.) ICC2 : Standby Current (/RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min ) ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V VIN 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V VOUT 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA ) * NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
o
CAPACITANCE
( TA=25 C, Vcc = 5V, f = 1Mz ) SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1
o
DESCRIPTION Input Capacitance (A0-A11) Input Capacitance (/WE) Input Capacitance (/RAS0) Input Capacitance (/CAS1-/CAS2) Input/Output Capacitance (DQ0-31)
MIN -
MAX 65 80 50 40 20
UNITS pF pF pF pF pF
AC CHARACTERISTICS
( 0 C TA 70oC , Vcc = 5V10%, See notes 1,2.) -5 -6 UNIT MIN MAX MIN 130 50 15 30 0 0 3 15 50 0 0 3 20 50 60 20 35 MAX ns ns ns ns ns ns ns SYMBOL
STANDARD OPERATION
Random read or write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall)
tRC tRAC tCAC tAA tCLZ tOFF tT
110
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/RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time /RAS to column address delay time /CAS to /RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address hold referenced to /RAS Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command hold referenced to /RAS Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Data-in hold referenced to /RAS Refresh period Write command set-up time /CAS setup time (C-B-R refresh) tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tREF tWCS tCSR 0 10 40 60 15 60 15 20 15 5 0 10 0 15 50 30 0 0 0 15 50 15 15 15 0 15 50
HMD4M144D9WG
50 10K 70 20 70 10K 45 30 20 20 15 5 0 10 0 15 55 35 0 0 0 15 55 15 20 20 0 15 55 16 0 10 16 10K 50 35 10K ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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/CAS hold time (C-B-R refresh) /RAS precharge to /CAS hold time Access time from /CAS precharge Fast page mode cycle time /CAS precharge time (Fast page) /RAS pulse width (Fast page ) /W to /RAS precharge time (C-B-R refresh) /W to /RAS hold time (C-B-R refresh) /CAS precharge(C-B-R counter test) NOTES tCHR tRPC tCPA tPC tCP tRASP tWRP tWRH tCPT 40 10 60 10 10 20 15 5
HMD4M144D9WG
15 5 35 45 10 100K 70 10 10 30 100K 40 ns ns ns ns ns ns ns ns ns
1.An initial pause of 200s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 2TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that tRCD tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 8. tWCS, tRWD, tCWD anf tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
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PACKAGING INFORMATION
HMD4M144D9WG
143.60 mm 136.70 mm 3.45 mm R1.57 mm R3.18051
18.52mm 6.45 mm 2.05 6.39mm 6.35 mm 130.81 R1.5710 mm
10.25 mm
7.68mm MAX
0.25 mm MAX
2.54 mm MIN
Gold : 1.040.10 mm 1.27 Solder:0.9140.10mm 1.290.08 mm
ORDERING INFORMATION
Part Number Density Org. Package Component Number 9EA 9EA Vcc MODE SPEED
HMD4M144D9WG-5 HMD4M144D9WG-6
64MByte 64MByte
x 144 x 144
200 Pin-DMM 200 Pin-DIMM
5V 5V
ECC ECC
50ns 60ns
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