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JULY 2004
XRT83D10
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
GENERAL DESCRIPTION
The XRT83D10 is a fully integrated, single channel, Line Interface Unit (Transceiver) for 75 or 120 E1 (2.048 Mbps) and 100 DS1 (1.544 Mbps) applications. The LIU consists of a receiver with adaptive data slicer for accurate data and clock recovery and a transmitter which accepts dual-rail digital inputs for signal transmission to the line using a low- impedance differential line driver. The LIU also includes a crystal-less jitter attenuator for clock and data smoothing which, depending on system requirements, can be selected in either the transmit or receive path. The XRT83D10 uses the transformer coupling on both the Receiver and Transmitter sides, and supports both 120 balanced,75 unbalanced and 100 interfaces. FEATURES * Complete E1 (CEPT) and DS1 Line Interface Unit * Generates transmit output pulses that are compliant with the ITU-T G.703 Pulse Template for 2.048Mbps (E1) rates FIGURE 1. BLOCK DIAGRAM OF THE XRT83D10
* On-Chip Pulse Shaping for both 75 ,120 and 100 Line Drivers * Clock Recovery and Selectable Crystal-less Jitter attenuator * Compliant with ETS300166 Return Loss * Compliant with the ITU-T G.823 Jitter Tolerance Requirements * Remote, Local and Digital Loop backs * Declares and Clears LOS per ITU-T G.775 * -40C to 85C Temperature Range * Low Power Dissipation * +5V or +3.3V Supply Operation
* Pin Compatible with AGERE T7290A and T5290A
APPLICATIONS * PDH Multiplexers * SDH Multiplexers * Digital Cross-Connect Systems * DECT (Digital European Cordless Telephone) Base Stations * CSU/DSU Equipment
R LO S
A LO S R TIP
R eceive D ata
D LO S
R R IN G
P ea k D ete ctor D a ta S lice r
D LO S
D ata & Tim in g R e co very
2
MODE1 MODE2 2
Loca l L oop ba ck LP1
2
D igital Lo opb ack LP 3
2
R PD AT A RNDATA R C LK FOFS
E XC LK
Tim in g G en erato r
Jitter A tten uato r
2
S C LK
T TIP
T ransm it D ata
T x Line D river
P ulse E qu alizer
2 2
2
2
T R IN G
R e m o te Loo back LP2
E XC LK
TAOS EC1 EC2 EC3 M O D E1 M O D E2
TPDATA TNDATA
T C LK E X C LK TAOS EC1 EC2 EC3 M O D E1 M O D E2 LO O P A LO O P B CS V DDA, G N D A V DDD, G N D D
+
Transm it M o nitor
TSC
Loss o f C lo ck
TA O S
TA O S
MODE2
E XC LK IC T C LK LO S JA C lock Local R em ote D igital
P Inte rface
D ecod e
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Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT83D10
REV. 1.0.3
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
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PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRT83D10IW PACKAGE TYPE 28 Lead 300 Mil Jedec SOJ OPERATING TEMPERATURE RANGE -40C to +85C
FIGURE 2. PIN OUT OF THE XRT83D10
EC1 ICT AVDD AGND RRING RTIP MODE2 MODE1 LOOPB LOOPA TAOS RLOS FOFS CLKLOS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18
EC2 EC3 DGND TRING DVDD TTIP RNDATA RPDATA RCLK TNDATA TPDATA TCLK EXCLK CS
17 16 15
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SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
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XRT83D10
REV. 1.0.3
PIN DESCRIPTIONS
MICROPROCESSOR
PIN # 15 NAME CS TYPE I DESCRIPTION Microprocessor Interface Select (Active Low) CS loads the data into the device on its falling edge and latches the data on its rising edge. For Hardware mode, CS is left open or connected to GND. NOTE: Internally pulled down 1 EC1 I Transmit Equalization Control. The three inputs, EC1,EC2 and EC3 are used for selecting transmit equalization. NOTE: Internally Pulled down. 27 EC3 I Transmit Equalization Control NOTE: Internally Pulled down. 28 EC2 I Transmit Equalization Control NOTE: Internally Pulled down. 7 MODE2 I Mode Select Mode 1 and Mode 2 select the clock and data paths through the jitter attenuator. NOTE: Internally Pulled down. 8 MODE1 I Mode Select NOTE: Internally Pulled down. 9 LOOPB I Loopback control. LOOPB along with LOOPA are used for selecting different loopbacks.
LOOPA 0 0 1 1
NOTE: Internally Pulled down. 10 LOOPA I
LOOPB 0 1 0 1
Loopback Mode Normal Operation Digital Remote Local
Loopback control. LOOPB along with LOOPA are used for selecting different loopbacks. NOTE: Internally Pulled down.
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XRT83D10
REV. 1.0.3
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
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RECEIVER SECTION
PIN #
6 5 20
NAME
RTIP RRING RCLK
TYPE
I I O
DESCRIPTION
Receive positive bipolar data Input Receive negative bipolar data Input Receive Clock Output Recovered receive clock for the terminal equipment. Receive positive NRZ data: Recovered positive data DS1 (1.544Mbits/s) or CEPT (2.048 Mbits/s) Receive negative data Recovered negative NRZ data DS1 (1.544Mbits/s) or CEPT (2.048 Mbits/s) Receive Loss of Signal: This pin is set "High" if analog loss-of-signal at the receiver input is detected or if digital loss-of-signal of the recovered data is detected.RLOS will remain "High" until the loss of signal condition clears.
21
RPDATA
O
22
RNDATA
O
12
RLOS
O
TRANSMITTER SECTION
PIN #
17
NAME
TCLK
TYPE
I
DESCRIPTION Transmit Clock DS1 Clock Signal. (1.544 MHz 130 ppm) or CEPT clock signal (2.048 MHz 80 ppm). Transmit Positive Data DS1 (1.544 Mbits/s) or CEPT (2.048 Mbits/s) positive bipolar data Transmit Negative Data DS1 (1.544 Mbits/s) or CEPT (2.048 Mbits/s) negative bipolar data Transmit Tip Output Positive bipolar transmit data Transmit Differential Ring Output Negative bipolar transmit data Loss of Clock Signal: This pin is set "High" when either the transmit clock (TCLK) or the clock output from the jitter attenuator is absent.
18 19 23 25 14
TPDATA TNDATA TTIP TRING CLKLOS
I I O O O
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SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
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XRT83D10
REV. 1.0.3
CONTROL FUNCTION
PIN #
2
NAME
ICT
TYPE
I
DESCRIPTION In Circuit Testing When this pin is tied "Low" all output pins are forced to high-impedance state for in-circuit testing.
NOTE: Internally pulled up.
16
ExCLK
I
External Clock Input: DS1 (1.544 MHz 130 ppm) or CEPT E1 (2.048 MHz 80 ppm) clock signal is provided. ExCLK must be an independent clock to guarantee device performance for all specifications. This clock must be continuously active (ungapped or unswitched) and void of jitter for the device to operate properly. Transmit All Ones: With this pin tied "High", an AMI encoded all "1's" signal sent to the transmit output using ExCLK as the timing reference. A remote loop back has higher priority over TAOS request.
NOTE: Internally pulled down.
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TAOS
I
9
LOOPB
I
Loopback control. LOOPB along with LOOPA is used for selecting different loopbacks.
LOOPA 0 0 1 1
NOTE: Internally Pulled down. 10 LOOPA I
LOOPB 0 1 0 1
Loopback Mode Normal Operation Digital Remote Local
Loopback control. LOOPB along with LOOPA is used for selecting different loopbacks.
NOTE: Internally Pulled down.
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FOFS
O
FIFO Overflow Signal: This pin is set "High" if the phase jitter of the incoming signal exceeds the tolerance of the jitter attenuator's buffer. This may result in loss of data and Jitter Attenuator is no longer attenuating jitter.
POWER AND GROUND
PIN #
3 4 24 26
NAME
AVDD AGND DVDD DGND
TYPE
**** **** **** ****
DESCRIPTION
Analog Supply: 5V 5% or 3.3V 5% Analog GND. Digital Supply: 5V 5% or 3.3V 5% Digital GND
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XRT83D10
REV. 1.0.3
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT TABLE 1: DC ELECTRICAL CHARACTERISTICS
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Ta = -40C to 85C, Vdd = 5V 5% or 3.3V 5% unless otherwise specified
PARAMETER
Input High Voltage Input Low Voltage Output High Voltage @IOH=5mA (See Note) VDD=5.0v VDD=3.3v Output Low Voltage @ IOL=5mA (See Note) VDD=5.0v VDD=3.3v Input Leakage Current (except input pins with pull-up resistors) Input Capacitance Output Load Capacitance
SYMBOL
VIH VIL VOH
MIN
2.0 0.5 2.4
TYP
5.0 0 -
MAX
5.5 0.8 VDD V V V
UNIT
VOL IL CI CO 0 0 5 0.4 10 20 20
V
uA pF pF
ELECTRICAL CHARACTERISTICS- POWER SPECIFICATIONS
PARAMETER Power Dissipation: With Jitter Attenuator DS1 (EC1=0,EC2=1,EC3=1) CEPT (75 ) CEPT (120 ) SYMBOL
PD 275 275 275 350 350 350 mW mW mW
MIN TYP MAX UNIT
NOTE: Power consumption measurement conditions with 50% 1s on the Transmit and Receive, TA = 250 C, VDD = 5V
TABLE 2: RECEIVER CHARACTERISTICS
TA = -40C to 85C, VDD = 5V 5% or 3.3V 5% Unless otherwise specified
PARAMETER
Receiver Sensitivity DS11 CEPT2 Recovered Clock Jitter Transfer Corner Frequency Jitter Attenuator Corner Frequency (-3dB curve) Return Loss in E1 (CEPT) Mode 51kHz-102kHz 102kHz-2048kHz 2048kHz-3072kHz
MIN.
10 9 12 18 14
TYP.
MAX
UNIT
dB
20 3
kHz Hz dB dB dB
NOTES: 1. 2. Measured at 772 KHz. 0dB is the Reference to 3.0Vp. Measured at 1024 KHz (both for 75 and 120). 0dB is the Reference to 2.37Vp (75) and 3.0Vp (120)
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SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
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XRT83D10
REV. 1.0.3
TABLE 3: TRANSMITTER CHARACTERISTICS
TA = -40C to 85C, VDD = 5V 5% or 3.3V 5% Unless otherwise specified
PARAMETER
AMI Output Pulse Amplitude DS1 (at DSX) 75 Application 120 Application Output Pulse Width DS1 CEPT Output Power Levels: DS1 (2kHz band at 772 kHz) DS1 (2 kHz band at 1544 kHz) Output Return Loss:( CEPT only) 51kHz -102kHz 102kHz-2048kHz 2048kHz-3072kHz
MIN.
2.4 2.13 2.70 330 224 12 -29 8 8 8
TYP.
3.0 2.37 3.00 350 244 16.7 -35 -
MAX
3.6 2.60 3.30 370 264 17.9 -
UNIT
V V V ns ns dBm dB dB dB dB
TABLE 4: INTERFACE DATA TIMING (SEE FIGURES 3 AND 4)
TA = -40 to +85 C, VDD = 5V 5% or 3.3V 5% Unless otherwise specified
PARAMETER
Transmit Clock Period DS11 CEPT2 TClk Duty Cycle Transmit Data Setup Time Transmit Data Hold Time TClk Rise Time (10% /90%) TClk Fall Time (90% / 10%) Receive Data Setup Time Receive Data Hold Time Receive Propagation Delay NOTE: 1. Tolerance of 130 ppm
SYMBOL
TClk
MIN.
-
TYP
647.7 488
MAX
ns ns 60 40 40
-
UNITS
TCLK tTSU tTHO tr tf tRSU tRHO tPD 2. Tolerance of 80 ppm.
40 50 40 140 180
50 -
% ns ns ns ns ns ns ns
40
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XRT83D10
REV. 1.0.3
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
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FIGURE 3. INTERFACE TIMING DIAGRAM - TRANSMIT
TCLK TCLK TTSU TPDATA or TNDATA
TR
TF TTHO .
FIGURE 4. INTERFACE TIMING DIAGRAM - RECEIVE
tPD RCLK RPDATA or RNDATA tRSU
tRHO
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SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT FIGURE 5. MICROPROCESSOR INTERFACE TIMING
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XRT83D10
REV. 1.0.3
t1
CS MODE 1 MODE 2 EC1 EC2 EC3 LOOPA LLOPB
t2
t3
t4
t5
TABLE 5: MICROPROCESSOR INTERFACE TIMING
SYMBOL
t1 t2 t3 t4 t5
PARAMETER
Control Signal Rise Time (10% - 90%) Control Signal Rise Time (10% - 90%) Control Signal Pulse Width Time Control SIgnal Setup Time Control Signal Hold Time
MIN
MAX
40 40
UNIT
ns ns ns ns ns
40 50 40
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XRT83D10 SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
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1.0 1.1
SYSTEM DESCRIPTION:
RECEIVER:
The XRT83D10, a single channel DS1/CEPT Line Interface Unit is a fully integrated transceiver that provides an electrical interface for DS1 carrier rate (1.544 Mbits/s) or CEPT rate (2.048 Mbits/s) applications.The bipolar input signals at RTIP and RRING are applied to the peak detector and slicer.Timing recovery is performed by the Clock and Data Recovery block. EC1,EC2 and EC3 rate control inputs must be set appropriately for DS1 or CEPT operation. The digital representation of the AMI signals goes to the clock recovery circuit for timing recovery before being output to the RPDATA and RNDATA pins. Clock timing recovery of the line interface is accomplished by means of a digital PLL scheme which has high input jitter tolerance. A continuously active (ungapped or unswitched) reference clock must be present at ExCLK to enable the Timing Generator block. ExCLK must be an independent reference such as an oscillator or system clock for proper operation. The ExCLK frequency must be 1.544 MHz 130 ppm for DS1 operation or 2.048 MHz 80 ppm for CEPT operation. Any data pattern with a minimum long-term 1s density of 12.5% with 15 or fewer consecutive 0s is allowed. 1.1.1 Loss of Signal: Both digital (DLOS) and analog (ALOS) loss-of-signal detection are used. The analog signal detector uses the output of the peak detector to determine if a signal is present at RTIP and RRING. If the input amplitude drops below approximately 0.4 Vp, the analog detector becomes active.Hysteresis is provided in the analog detector to eliminate ALOS chattering. Either the analog or digital detector sets RLOS "High". 1.2 TRANSMITTER:
The transmitter accepts a clock with positive and negative data (dual-rail NRZ format) and converts the signal to a balanced bipolar data signal (AMI format). Positive 1s are produced by a positive pulse on device pin TTIP and negative 1s are produced by a positive pulse on device pin TRING. Binary 0s are converted to null pulses. All pulse shapes are controlled on-chip according to equalizer control inputs as defined in Table 6 below.
TABLE 6: EQUALIZER/RATE CONTROL
OPERATION DS1 CLOCK RATE TRANSMITTER EQUALIZATION* 0 ft -131 ft 131 ft - 262 ft 1.544 MHz 262 ft - 393 ft 393 ft - 524 ft 524 ft - 655 ft CEPT 2.048 MHz 75 120 MAXIMUM CABLE LOSS** 0.6 1.2 1.8 2.4 3.0 EC1 0 0 0 1 1 1 1 EC2 0 1 1 0 0 1 1 EC3 1 0 1 0 1 0 1
NOTES: 1. 2. * Distance to DSX in feet for 22-Ga. Use maximum loss figures for other cable types. ** dB at 772 kHz.
Transmitter specifications are shown in Figure 6. The DS1 pulse shape template is specified at the DSX and is illustrated in Figure 6.CEPT transmit waveforms at the device output conform to the template shown in Figure 7.
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XRT83D10 SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
FIGURE 6. DSX-1 PULSE TEMPLATE (NORMALIZED AMPLITUDE)
TABLE 7: DSX1 INTERFACE ISOLATED PULSE MASK PER ANSI T1.102-1993 AND CORNER POINT SPECIFICATIONS
MINIMUM CURVE
TIME (UI) NORMALIZED AMPLITUDE (V) TIME (UI)
MAXIMUM CURVE
NORMALIZED AMPLITUDE (V)
-0.77 -0.23 -0.23 -0.15 0.0 0.15 0.23 0.23 0.46 0.66 0.93 1.16
-0.05 -0.05 0.5 0.95 0.95 0.9 0.5 -0.45 -0.45 -0.2 -0.05 -0.05
-0.77 -0.39 -0.27 -0.27 -0.12 0.0 0.27 0.35 0.93 1.16
0.05 0.05 0.8 1.15 1.15 1.05 1.05 -0.07 0.05 0.05
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XRT83D10 SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
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FIGURE 7. ITU G.703 PULSE TEMPLATE
269 ns (244 + 25)
20%
10%
V = 100%
10%
20%
194 ns (244 - 50)
Nominal pulse
50%
244 ns
10%
488 ns (244 + 244) Note - V corresponds to the nominal peak value.
1.3 JITTER ATTENUATOR To reduce frequency jitter in the transmit clock or receive clock, a crystal-less jitter attenuator is provided. The jitter attenuator can be selected either in the transmit or receive path or it can be disabled as shown in Table 8.
TABLE 8: JITTER ATTENUATOR SELECTION
JITTER ATTENUATOR CONNECTIVITY Bypass (Disabled) Transmit Path Receive Path Test Mode MODE 1 0 0 1 1 MODE 2 0 1 0 1
1.3.1
FIFO Overflow Signal (FOFS):
A FIFO overflow Signal (FOFS = 1) is indicated if the phase jitter exceeds the tolerance of the jitter attenuator. When FOFS is "High", jitter attenuator bandwidth is increased to track the short term jitter and no data error will
20%
12
10%
0%
10%
10%
219 ns (244 - 25)
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XRT83D10 SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
occur.Jitter attenuator is no longer attenuating input jitter.(This signal is asserted until normal operation resumes.) 1.4 1.4.1 ALARMS AND MAINTENANCE: Loss of Signal:
A digital loss of signal (DLOS =1) is indicated if 17575 or more consecutive 0s occur in the receive data stream during DS1 operation.During CEPT operation, a DLOS is indicated when 32 or more consecutive 0s occur in the receive data stream.DLOS is the deactivated when the ones density exceeds 12.5% and there are no more than 100 consecutive 0s for DS1 and 16 consecutive 0s for CEPT, signifying the return of good signal.DLOS deactivation monitors the data in a fixed 32-bit window.Each window must have at least four 1s with no more than 15 consecutive 0s. Upon DLOS detection, RCLK is phase-locked to the external clock (ExCLK) so that other system devices slaved to the line clock continue to operate without instantaneous phase hits or discontinuities. Either an analog loss of signal (ALOS) or a digital loss of signal (DLOS) activates the RLOS output pin. 1.4.2 Loss of Clock Signal (CLKLOS):
A loss of clock signal (CLKLOS =1) is indicated if either the transmit clock (TCLK) or the smoothing clock (SCLK) output of the jitter attenuator is absent.If the jitter attenuator is placed in the transmit path, the SCLK is monitored.If the jitter attenuator is not placed in the transmit path, TCLK or Remote Loopback Clock is monitored.For every ten clock periods of the ExCLK oscillator clock, a strobe is generated.If a single transmit clock period occurs between strobes, then CLKLOS = 0. If no transmit clock period occurs between strobes, then CLKLOS = 1 and the output drivers ((TTIP and TRING) are placed into a high-impedance state and no data is transmitted. 1.4.3 AIS (TAOS) Generator: When the transmit all ones (TAOS = 1) signal is set, a continuous stream of bipolar 1s is transmitted onto the line synchronous with ExCLK. The TPDATA and TNDATA inputs are ignored during this mode. If the RLOS output is externally connected to the TAOS input, an RLOS error initiates a transmit all 1s signal as long as RLOS = 1.Also, TAOS input is ignored when a remote loopback is selected. There is no microprocessor input for the TAOS input, i.e., any change on the TAOS pin is fed directly into the device and is not impeded by the CS function. 1.5 LOOPBACKS:
The XRT83D10 has three independent loopback paths, which are activated as shown in Figure 9.
TABLE 9: LOOPBACK CONTROL
OPERATION Normal Digital Local loopback Remote Loopback Local Loopback SYMBOL LP3 LP2* LP1 LOOPA 0 0 1 1 LOOPB 0 1 0 1
NOTE: During Remote Loopback, TAOS is ignored.
A local loopback (LP1) connects the jitter attenuator's output clock and data to the receive clock and data output pins. MODE1:2 = 01 must be selected for this loopback to operate (jitter attenuator in the transmit path). Valid transmit output data continues to be sent to the network. However, if the transmit all 1s (TAOS =1) is
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XRT83D10 SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
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initiated, an all 1s signal is sent to the network and does not corrupt the looped data. The RLOS alarm still monitors the entire receive function. A remote loopback (LP2) loops the recovered clock and re-timed data into the transmitter and back onto the line. The receive front end, receive PLL, jitter attenuator (if enabled), and transmit driver circuitry are all exercised. The transmit clock, transmit data, and TAOS inputs are ignored. Valid receive output data continues to be sent to RPDATA and RNDATA. This loop can be used to isolate failures between systems. A digital local loopback (LP3) directly loops the transmit clock and data to the receive clock and data output pins. The transmit all 1s signal can be transmitted when in this loopback. LP3 (rather than LP1) must be selected if MODE2 = 0. 1.6 MICROPROCESSOR INTERFACE: A chip select input (CS) configures the device in either hardware mode or microprocessor mode. The chipselect function, applies to the following inputs: MODE1, MODE2,EC1,EC2,EC3,LOOPA and LOOPB. In the hardware mode, any change on these asynchronous input pins fed directly into the device.To maintain hardware mode, set CS = 0. In the microprocessor mode, new digital control inputs are loaded into the XRT83D10 on the falling edge of CS and are latched on the rising edge of CS. 1.7 IN-CIRCUIT TESTING:
The XRT83D10 has the ability to allow for in-circuit testing by activating the high-impedance mode (ICT = 0).During this mode, all output buffers (TTIP,TRING,RCLK,RPDATA,RNDATA,RLOS,FOFS and CLKLOS) are 3-stated. During the 3-stated condition, the absolute maximum voltage ratings must not be exceeded on any pin. 1.8 ABSOLUTE MAXIMUM RATINGS: Stresses in excess of absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only.Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet.
ELECTRICAL CHARACTERISTICS - ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage Range Storage Temperature Maximum Voltage (any pin) with respect to VDD Minimum Voltage (any pin) with respect to GND Maximum voltage allowed (RTIP,RRING) with respect to GND ESD (Human-body model) -0.5 -5.0 2000 5.0
SYMBOL
VDD STO
MIN
MAX
UNIT
-0.5 -65
6.5 125 0.5
V degC V V V V
NOTE: Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the device.The above values are absolute stress ratings only. Exposure to Absolute Maximum Ratings for extended periods can adversely affect device reliability.
2.0 APPLICATIONS: 2.1 Line Termination: For the following applications, the tolerance of all transformer turns ratios is a maximum of 2%. The tolerance of all resistors in the transmit path is a maximum of 1%.
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XRT83D10 SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
FIGURE 8. CEPT APPLICATION FOR TWISTED-PAIR INTERFACE - 5V OR 3.3V OPERATION.
1:2
R T IP 866
RPDATA RNDATA
200 866
R e c e iv e In p u t
RC LK
DVDD AVDD R R IN G 0 .1 F +5 V 10 F
2 .4 2 :1
9 .1 T T IP DGND AGND
120
T ra n s m it O u tp u t
TPDATA TNDATA
9 .1 T R IN G
TC LK
FIGURE 9. DS1 APPLICATION FOR TWISTED-PAIR INTERFACE - 5V OR 3.3V OPERATION.
1:2
R T IP 500
RPDATA RNDATA
200 500
R e c e iv e In p u t
RC LK
DVDD R R IN G AVDD 1 F 10 F +5 V
2:1
0 .6 8 F T T IP DGND AGND
100
T ra n s m it O u tp u t
TPDATA TNDATA TC LK
T R IN G
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XRT83D10 SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
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FIGURE 10. CEPT APPLICATION FOR COAXIAL INTERFACE - 5V OR 3.3V OPERATION.
1:2
R T IP 270
RPDATA RNDATA
200 270
R e c e iv e In p u t
RC LK
DVDD R R IN G AVDD 0 .1 F +5 V 1 0 F
2 .4 2 :1
6 .2 T T IP DGND AGND
75
T ra n s m it O u tp u t
TPDATA TNDATA
6 .2 T R IN G
TC LK
FIGURE 11. DS1 APPLICATION FOR TWISTED-PAIR INTERFACE 5V OR 3.3V OPERATION
1:2
R T IP 500
RPDATA RNDATA
200 500
R e c e iv e In p u t
RC LK
DVDD AVDD R R IN G 1 F 10 F +5 V
2 .4 2 :1
2 T T IP DGND AGND
100
T ra n s m it O u tp u t
TPDATA TNDATA
2 T R IN G
TC LK
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SINGLE CHANNEL DS1/T1/CEPT LINE INTERFACE UNIT
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XRT83D10
REV. 1.0.3
ORDERING INFORMATION
PRODUCT NUMBER XRT83D10IW
PACKAGE 28 Lead 300 Mil Jedec SOJ
OPERATING TEMPERATURE RANGE -400C to +850C
PACKAGE DIMENSIONS
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SINGLE CHANNEL DS1/T1/CEPT LINE INTERFACE UNIT REVISION HISTORY
REVISION #
P1.0.0 P1.0.1 P1.0.2 P1.0.3 P1.0.4 1.0.0 1.0.1 1.0.2 1.0.3
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XRT83D10
REV. 1.0.3
DATE
06/17/03 7/28/2003 8/11/2003 8/29/2003 12/16/2003 2/16/2004 3/12/2004 5/3/2004 7/23/2004 1st release of the XRT83D10 mkll.0 preliminary data sheet.
DESCRIPTION
Modified the block diagram. Added application circuits.Corrected the timinga dn electrical characteristics. For Receiver Sensitivity, added a note stating that DS1 measured at 772 KHz and CEPT measured at 1024 KHz. Cleaned up the description for the LOS condition. Transformer information and resistor values included.Rearranged and added information in the tables. The TBD numbers filled in. "Preliminary" removed. Included Table 7 Included the Power Levels for DS1 Included the Max Power numbers.Included Figure 11 for DS1 interface
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2003 EXAR Corporation Datasheet July 2004. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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