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IC-LF1401
128x1 Linear Image Sensor
Rev A3, Page 1/9 FEATURES 128 active photo pixels of 56 m at a 63.5 m pitch (400 DPI) Integrating L-V conversion followed by a sample & hold circuit High sensitivity and uniformity over wavelength High clockrates of up to 5 MHz Only 128 clocks required for readout Shutter function enables exible integration times Glitch-free analogue output Push-pull output amplier 5 V single supply operation Can run off external bias to reduce power consumption Pin-to-pin compatible with TSL1401 APPLICATIONS Optical line image sensors CCD substitute
PACKAGES
OLGA LF2C
OBGATM LF3C
Die size (8.5 mm x 1.6 mm)
BLOCK DIAGRAM
Copyright (c) 2005 iC-Haus
http://www.ichaus.com
IC-LF1401
128x1 Linear Image Sensor
Rev A3, Page 2/9 DESCRIPTION IC-LF1401 is an integrating light-to-voltage converter with a line of 128 pixels pitched at 63.5 m (center-tocenter distance). Each pixel consists of a 56.4 m x 200 m photodiode and an integration capacitor with a sample-and-hold circuit. The integrated control logic makes operation very simple, with only a start and clock signal necessary. A third control input (DIS) enables the integration to be suspended at any time (electronic shutter). When the start signal is given hold mode is activated for all pixels simultaneously with the next leading clock edge; starting with pixel 1 the hold voltages are switched in sequence to the push-pull output amplier. The second clock pulse resets all integration capacitors and the integration period starts again in the background during the output phase. A run is complete after 128 clock pulses. IC-LF1401 is suitable for high clock rates of up to 5 MHz. If this is not required the supply current can be reduced via the external bias setting (current into pin RSET).
IC-LF1401
128x1 Linear Image Sensor
Rev A3, Page 3/9 PACKAGES OLGA LF2C, OBGA LF3C TM PIN CONFIGURATION OLGA LF2C (top view) PIN FUNCTIONS No. Name Function Start Integration Input Clock Input Analogue Output +5 V Supply Voltage Bias Current (connected to GND for internal bias = default; resistor from VCC to RSET for reduced current consumption) 6 AGND Analogue Ground 7 GND Digital Ground 8 DIS Hold Integration Input 1 2 3 4 5 SI CLK AO VCC RSET
PIN CONFIGURATION OBGATM LF3C (top view)
CHIP LAYOUT Die size: 8.5 mm x 1.6 mm
IC-LF1401
128x1 Linear Image Sensor
Rev A3, Page 4/9 ABSOLUTE MAXIMUM RATINGS
Beyond these values damage may occur; device operation is not guaranteed. Item No. Symbol Parameter Digital Supply Voltage Analog Supply Voltage Voltage at SI, CLK, DIS, RSET, TP, AO Current in RSET, TP, AO ESD Susceptibility at all pins Operating Junction Temperature Storage Temperature Range see package specication MIL-STD-883, Method 3015, HBM 100 pF discharged through 1.5 k -40 Conditions Fig. Min. -0.3 -0.3 -0.3 -10 Max. 6 6 VCC + 0.3 10 2 125 V V V mA kV C Unit
G001 VDD G002 VCC G003 V() G004 I() G005 Vd() G006 Tj G007 Ts
THERMAL DATA
Operating Conditions: VCC = VDD = 5 V 10 % Item No. T01 Symbol Ta Parameter Conditions Fig. Min. Operating Ambient Temperature Range see package specication (extended range on request) Typ. Max. Unit
All voltages are referenced to ground unless otherwise stated. All currents into the device pins are positive; all currents out of the device pins are negative.
IC-LF1401
128x1 Linear Image Sensor
Rev A3, Page 5/9 ELECTRICAL CHARACTERISTICS
Operating Conditions: VCC = VDD = 5 V 10 %, RSET = GND, Tj = -25...85 C unless otherwise noted Item No. 001 002 003 004 005 006 007 008 Symbol Parameter Conditions Tj C Fig. Min. 4.5 4.5 f(CLK) = 1 MHz V(VCC), I() = 1 mA V(AGND), V(VCC), 0.3 -1.5 0.3 -1.5 200 8 Typ. Max. 5.5 5.5 300 13 1.8 -0.3 1.5 -0.3 V V A mA V V V V Unit
Total Device VDD VCC I(VDD) I(VCC) Vc()hi Vc()lo Vc()hi Vc()lo Digital Supply Voltage Range Analog Supply Voltage Range Supply Current in VDD Supply Current in VCC Clamp Voltage hi at SI, CLK,DIS, Vc()hi = V() TP, RSET Clamp Voltage lo at SI, CLK,DIS, Vc()hi = V() TP, RSET I() = -1 mA Clamp Voltage hi at AO Clamp Voltage lo at AO, VCC, VDD, GND Radiant Sensitive Area Spectral Sensitivity Spectral Application Range Saturation Voltage lo Saturation Voltage hi Sensitivity Offset Voltage Offset Voltage Deviation during integration mode Signal Deviation during hold mode Settling Time
Vc()hi = V(AO) I(AO) = 1 mA Vc()lo = V() I() = -1 mA
V(AGND),
Photodiode Array 201 202 203 301 302 303 304 305 306 307 A() S( )max ar Vs()lo Vs()hi K V0() V0() V() tp(CLKAO) VCCon VCCoff VCChys Ibias() Vref Vt()hi Vt()lo Vt()hys I() fclk 200 m x 56.40 m per Pixel = 680 nm S( ar) = 0.25 x S( )max I() = 1 mA Vs()hi = VCC V(), I() = -1 mA 2.88 400 -250 -150 800 50 150 200 = 680 nm, package OLGA LF2C integration time 1 ms, no illumination V0() = V(AO)t1 V(AO)t2, t = t2 t1 = 1 ms V0() = V(AO)t1 V(AO)t2, t = t2 t1 = 1 ms Cl(AO) = 10 pF, CLK lo V(AO) = 0.98 x V(VCC) hi until 400 0.01128 0.5 980 0.5 1 mm A/W nm V V V/pWs mV mV mV ns
Analogue Output AO
Power-On Reset 801 802 803 901 902 B01 B02 B03 B04 B05 Power-On Release by VCC Power-Down Reset by VCC Hysteresis Permissible External Bias Current Reference Voltage Threshold Voltage hi Threshold Voltage lo Hysteresis Pull-Down Current Permissible Clock Frequency Vt()hys = Vt()hi Vt()lo I(RSET) = Ibias 2 2 2 VCChys = VCCon VCCoff 1 0.4 20 2.5 1.4 0.9 300 10 30 3 1 2 100 3.5 1.8 1.2 800 50 5 4.4 V V V A V V V mV A MHz
Bias Current Adjust RSET
Input Interface SI, CLK, DIS
IC-LF1401
128x1 Linear Image Sensor
Rev A3, Page 6/9 OPTICAL CHARACTERISTICS: Diagrams
100 % 90 80 70 60 50 40 30 20 10 400 600 800 1000 nm
Figure 1: Relative spectral sensitivity
OPERATING REQUIREMENTS: Logic
Operating Conditions: VCC = VDD = 5 V 10 %, Tj = -25...85 C input levels lo = 0...0.45 V, hi = 2.4 V...VCC, see Fig. 2 for reference levels Item No. Symbol Parameter Setup Time: SI stable before CLK lo Conditions Fig. Min. 3 hi hi 3 50 ns 50 Max. ns Unit
I001 tset I002 thold
Hold Time:SI stable after CLK lo
thold
V
CLK
2.4V 2.0V
Input/Output
SI
0.8V 0.45V t 1 0
tset
Figure 2: Reference levels
Figure 3: Timing diagram
IC-LF1401
128x1 Linear Image Sensor
Rev A3, Page 7/9 DESCRIPTION OF FUNCTIONS Normal operation Following an internal power-on reset the integration and hold capacitors are discharged and the sample and hold circuit is set to sample mode. A high signal at SI and a rising edge at CLK triggers a readout cycle and with it a new integration cycle. In this process the hold capacitors of pixels 1 to 127 are switched to hold mode immediately (SNH = 1), with pixel 128 (SNH128 = 1) following suit one clock pulse later. This special procedure allows all pixels to be read out with just 128 clock pulses. The integration capacitors are discharged by a one clock long reset signal (NRCI = 0) which occurs between the 2nd and 3rd falling edge of the readout clock pulse (cf. Figure 4). After the 127 pixels have been read out these are again set to sample mode (SNH = 0), likewise for pixel 128 one clock pulse later (SNH128 = 0).
Figure 4: Readout cycle and integration sequence If prior to the 128th clock pulse a high signal occurs at SI the present readout is halted and immediately reinitiated with pixel 1. In this instance the hold capacitors retain their old value i.e. hold mode prevails (SNH/SNH128 = 0).
Figure 5: Restarting a readout cycle With more than 128 clock pulses until the next SI signal, pixel 1 is output without entering hold mode; the output voltage tracks the voltage of the pixel 1 integration capacitor.
IC-LF1401
128x1 Linear Image Sensor
Rev A3, Page 8/9
Figure 6: Clock pulse continued without giving a new integration start signal Operation with the shutter function Integration can be suspended at any time via pin DIS, i.e. the photodiodes are disconnected from their corresponding integration capacitor when DIS is high and the current integration capacitor voltages are maintained. If this pin is open or switched to GND the pixel photocurrents are summed up by the integration capacitors until the next successive SI signal follows.
Figure 7: Dening the integration time via shutter input DIS External bias current setting In order to reduce the power consumption of the device an external reference current can be supplied to pin RSET which reduces the maximum readout frequency, however. To this end a resistor must be connected from VCC to RSET. If this pin is not used, it should be connected to GND.
This specication is for a newly developed product. iC-Haus therefore reserves the right to change or update, without notice, any information contained herein, design and specication; and to discontinue or limit production or distribution of any product versions. Please contact iC-Haus to ascertain the current data. Copying - even as an excerpt - is only permitted with iC-Haus approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specication on this site and does not assume liability for any errors or omissions in the materials. The data specied is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, tness for a particular purpose or of any other nature are made hereunder with respect to information/specication or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
IC-LF1401
128x1 Linear Image Sensor
Rev A3, Page 9/9 ORDERING INFORMATION
Type iC-LF
Package OLGA LF2C OBGA LF3C TM -
Order Designation iC-LF OLGA LF2C iC-LF OBGA LF3C iC-LF chip
For information about prices, terms of delivery, other packaging options etc. please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (61 35) 92 92-0 Fax: +49 (61 35) 92 92-192 Web: http://www.ichaus.com E-Mail: sales@ichaus.com

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