|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
Integrated Circuit Systems ICS1527 Video Clock Synthesizer General Description The ICS1527 is a low-cost, high-performance frequency generator. It is suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video applications. Using ICS's advanced low-voltage CMOS mixed-mode technology, the ICS1527 is an effective clock synthesizer that supports video projectors and displays at resolutions from VGA to beyond XGA. The ICS1527 offers single-ended clock outputs to 60 or 110 MHz. The HSYNC_out, and VSYNC_out pins provide the regenerated versions of the HSYNC and VSYNC inputs synchronous to the CLK output. The advanced PLL uses either its internal programmable feedback divider or an external divider. The device is programmed by a standard I2C-busTM serial interface and is available in a TSSOP16 package. Features * Lead-free packaging (Pb-free) * Low jitter (typical 27 ps short term jitter) * LVCMOS single-ended clock outputs * 60/110 MHz speed grades available * Uses 3.3 V power supply * 5 Volt tolerant Inputs (HSYNC, VSYNC) * Coast (ignore HSYNC) capability via VSYNC pin * Industry standard I2C-bus programming interface * PLL Lock detection via I2C or LOCK output pin * 16-pin TSSOP package Applications * Frequency synthesis * LCD monitors, video projectors and plasma displays * Genlocking multiple video subsystems ICS1527 Functional Diagram HSYNC VSYNC IC EXTFB External Divider CLK 2 Pin Configuration (16-pin TSSOP) VSSD SDA SCL VSYNC EXTFB HSYNC VDDA VSSA HSYNC_out ICS1527 VSYNC_out 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDDD VSSQ VSYNC_out VDDQ CLK HSYNC_out LOCK I2CADR MDS 1527 G ICS reserves the right to make changes in the preliminary device data identified in this publication without notice. ICS advises its customers to obtain the latest version of all device data to verify that information being relied upon is current and accurate. Revision 110905 ICS1527 Data Sheet Section 1 Overview Section 1 Overview The ICS1527 has the ability to operate in line-locked mode with the HSYNC input. The ICS1527 is a user-programmable, high-performance general purpose clock generator. It is intended for graphics system line-locked and genlocked applications, and provides the clock signals required by high-performance analog-to-digital converters. 1.1 Phase-Locked Loop The phase-locked loop has a very wide input frequency range (8 kHz to 100 MHz). Not only is the ICS1527 an excellent, general purpose clock synthesizer, but it is also capable of line-locked operation. Refer to the block diagram below. Figure 1-1 HSYNC Simplified Block Diagram CP VCO VCOD 2,4,8,16 PFD CLK FD 12..4103 EXTFB Flip-flop VSYNC Flip-flop HSYNC_out VSYNC_out Note: Polarity controls and other circuit elements are not shown in above diagram for simplicity The heart of the ICS1527 is a voltage controlled oscillator (VCO). The VCO speed is controlled by the voltage on the loop filter. This voltage will be described later in this section. The VCO's clock output is first passed through the VCO Divider (VCOD). The VCOD allows the VCO to operate at higher speeds than the required output clock. NOTE: Under normal, locked operation the VCOD has no effect on the speed of the output clocks, just the VCO frequency. The output of the VCOD is the full speed output frequency seen on the CLK. This clock is then sent through the 12-bit internal Feedback Divider (FD). The feedback divider controls how many clocks are seen during every cycle of the input reference. The Phase Frequency Detector (PFD) then compares the feedback to the input and controls the filter voltage by enabling and disabling the charge pump. The charge pump has programmable current drive and will source and sink current as appropriate to keep the MDS 1527 G 2 input and the HSYNC_out output aligned. The input HSYNC and VSYNC can be conditioned by a high-performance Schmitt-trigger by sharpening the rising/falling edge. The HSYNC_out and VSYNC_out signals are aligned with the output clock (CLK) via a set of flip flops. 1.2 Output Drivers and Logic Inputs The ICS1527 uses low-voltage TTL (LVTTL) inputs and LVCMOS outputs, operating at the 3.3 V supply voltage. The LVTTL inputs are 5 V tolerant. The LVCMOS drive resistive terminations or transmission lines. 1.3 Automatic Power-On Reset Detection The ICS1527 has automatic power-on reset detection (POR) circuitry and it resets itself if the supply voltage drops below threshold values. No external connection to a reset signal is required. Revision 110905 In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1 w w w. i c s t . c o m ICS1527 Data Sheet Section 1 Overview 1.4 I2C Bus Serial Interface The ICS1527 uses a 5 volt tolerant, industry-standard I2C-bus serial interface that runs at either low-speed (100 kHz) or high-speed (400 kHz). The interface uses 12 word addresses for control and status: one write-only, eight read/write, and three read-only addresses. Two ICS1527 devices can sit on the same I2C bus, each selected by the Master according to the state of the I2CADR pin. The 7 bit device address is 0100110 (binary) when I2CADR is low. The device address is 0100111 (binary) when I2CADR is high. See Section 4, "Programming" MDS1527 G 3 Revision 110905 In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1 w w w. i c s t . c o m ICS1527 Data Sheet Section 2 Pin Descriptions Section 2 Pin Descriptions TYPE POWER IN/OUT IN IN IN IN POWER POWER IN LVCMOS OUT LVCMOS OUT LVCMOS OUT POWER LVCMOS OUT POWER POWER DESCRIPTION Digital ground Serial data Serial clock Vertical sync External feedback Horizontal sync Analog supply Analog ground I2C device address Lock HSYNC output Pixel clock output Output driver supply VSYNC output Output driver ground Digital supply From External Divider Clock input to PLL Power for analog circuitry Ground for analog circuitry Chip I2C address select PLL lock Schmitt-trigger filtered HSYNC realigned with the output pixel clock LVCMOS driver for full-speed clock Power for output drivers Schmitt-trigger filtered VSYNC realigned with the output pixel clock Ground for output drivers Power for digital sections I2C-bus I C-bus 2 Table 2-1 ICS1527 Pin Descriptions PIN NO. PIN NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSSD SDA SCL VSYNC EXTFB HSYNC VDDA VSSA I2CADR LOCK HSYNC_out CLK VDDQ VSYNC_out VSSQ VDDD COMMENTS Notes 1 1 1&2 1&2 1&2 Notes: 1. These LVTTL inputs are 5 V tolerant. 2. Connect to ground if unused. MDS 1527 G 4 Revision 110905 In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1 w w w. i c s t . c o m ICS1527 Data Sheet Section 3 Register map summary Section 3 Word Address 00h Register map summary Reset Value 1 0 Name Input Control Access R/W Bit Name CPen VSYNC_Pol Bit # 0 1 Description Charge Pump Enable 0=External Enable via VSYNC, 1=Always Enabled VSYNC Polarity (Charge Pump Enable) Requires 00h:0=0 0=Coast (charge pump disabled) while VSYNC low, 1=Coast (charge pump disabled) while VSYNC high HSYNC Polarity 0=Rising Edge, 1=Falling Edge External Feedback Polarity 0=Positive Edge, 1=Negative Edge External Feedback Select 0=Internal Feedback, 1=External Reserved Enable PLL Lock Status Output 0=Disable, 1=Enable Reserved HSYNC_Pol Fbk_Pol Fbk_Sel Reserved EnPLS Reserved 2 3 4 5 6 7 0 0 0 0 1 0 01h Loop Control* R/W ICP0-2 0-2 ICP (Charge Pump Current) Bit 2,1,0 = {000 =1 A, 001 = 2 A, 010 = 4 A... 110 = 64 A, 111 = 128 A}. Increasing the PF Detector Gain makes the loop respond faster, raising the loop bandwidth. The typical value when using the internal loop filter is 011. Reserved VCO Divider Bit 5,4= {00 = /2, 01=/4, 10=/8, 11=/16} Reserved Reserved VCOD0-1 Reserved 3 4-5 6-7 02h FdBk Div 0* R/W FBD0-7 0-7 Feedback Divider LSBs (bits 0-7) 03h FdBk Div 1* R/W FBD8-11 0-3 Feedback Divider MSBs (bits 8-11) Divider setting = 12 bit word + 8 Minimum 12 = 000000000100 Maximum 4103 =111111111111 Reserved Reserved 4-7 04h Reserved Reserved 0-7 0 Reserved 05h Schmitttrigger* R/W Schmitt control Metal_Rev 0 1-7 1 0 Schmitt-trigger control 0=Schmitt-trigger, 1=No Schmitt-trigger Metal Mask Revision Number 06h Output Enables R/W Reserved OE Reserved 0 1 2-7 0 0 0 Reserved Output Enable for CLK, HSYNC_out, VSYNC_out 0=High Impedance (disabled), 1=Enabled Reserved MDS1527 G 5 Revision 110905 In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1 w w w. i c s t . c o m ICS1527 Data Sheet Word Address Reset Value Section 3 Register map summary Name Access Bit Name Bit # Description 07h Reserved Reserved Reserved 0-6 7 0 Reserved Part requires a 0 for correct operation 08h Reset Write Reserved 0-7 0 Writing 5Ah resets part and commits values written to word addresses 01h-03h and 05h 09-0Fh Reserved Read Reserved 0-7 Reserved 10h Chip Ver Read Reserved 0-7 Reserved 11h Chip Rev Read Chip Rev 0-7 01 Reserved 12h Rd_Reg Read Reserved PLL_Lock Reserved 0 1 2-7 N/A N/A 0 Reserved PLL Lock Status 0=Unlocked, 1=Locked Reserved *. Written values to these registers do not take effect immediately, but require a commit via register 08h MDS 1527 G 6 Revision 110905 In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1 w w w. i c s t . c o m ICS1527 Data Sheet Section 4 Programming Section 4 Programming 4.1 Industry-Standard I2C Serial Bus: Data Format ICS1527 Data Format for I2C 2-Wire Serial Bus D ata (0) A C K A C K ... D ata (n) AS CT KO P Figure 4-1 S ingle/m ultiple register w rite (page w rite) D evice address W ord address S010011B0A T C A K R T S ingle/m ultiple register read D evice address S010011B0A T C A K R T S equ ential single/m u ltiple register read D evice address S010011B1A T C A K R T M aster drives line D ata (0) W ord address D evice address AS010011B1A CT C KA K R T D ata (0) A C K ... D ata (n) N O A C K S T O P D ata (n) A C K ... N O A C K S T O P S lave drives line Notes: The ICS1527 uses 16 byte pages (00h-0Fh is the first page, 10h-1Fh is the second page). Writing or reading beyond the end of page yields undefined results. The ICS1527 has a device address of 010011B, where B is the state of the I2CADR pin. MDS1527 G 7 Revision 110905 In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1 w w w. i c s t . c o m ICS1527 Data Sheet Section 5 AC/DC Operating Conditions Section 5 AC/DC Operating Conditions 5.1 Absolute Maximum Ratings Table 5-1 lists absolute maximum ratings for the ICS1527. Stresses above these ratings can cause permanent damage to the device. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the ICS1527 at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Table 5-1 ICS1527 Absolute Maximum Ratings Item VDD, VDDA, VDDQ (measured to VSS)* Digital Inputs Analog Inputs Analog Outputs Digital Outputs Storage Temperature Junction Temperature Soldering Temperature ESD Susceptibility* Rating 4.3 V VSS -0.3 V to 5.5 V VSS -0.3 V to 6.0 V VSSA -0.3 V to VDDA +0.3 V VSSQ -0.3 V to VDDQ +0.3 V -65C to +150C 125C 260C > 2 KV** *. Measured with respect to VSS. During normal operations, the VDD supply voltage for the ICS1527 must remain within the recommended operating conditions. **. Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation. Table 5-2 Environmental Conditions Parameter Ambient Operating Temperature Power Supply Voltage Table 5-3 DC Characteristics Min. 0 +3.0 Typ. - +3.3 Max. +70 +3.6 Units C V Parameter Digital Supply Current Output Driver Supply Current Analog Supply Current Power consumption Power-On-Reset (POR) Threshold Symbol IDDD IDDQ IDDA Conditions VDDD = 3.6 V VDDD = 3.6 V No drivers enabled VDDA = 3.6 V VSS Min. - Max. 25 6 5 300 1.8 UNITS mA mA mA mW V MDS 1527 G 8 Revision 110905 In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1 w w w. i c s t . c o m ICS1527 Data Sheet Table 5-4 AC Characteristics Section 5 AC/DC Operating Conditions Parameter Symbol fVCO K fEXTFB VIH VIL fHSYNC fVSYNC VIH VIL Min. 50 Typical Max. 400 Units MHz MHz/V Notes General VCO Frequency VCO Gain 165 8 1.0 8 30 1.7 VSS - 0.3 0.2 VIH VIL 2 VSS - 0.3 2 VSS - 0.3 10,000 120 5.5 1.1 0.8 5.5 0.8 VDD+0.3 0.8 0.4 6.0 10,000 2.0 AC Inputs EXTFB Input Frequency EXTFB Input High Voltage EXTFB Input Low Voltage HSYNC Input Frequency VSYNC Input Frequency Input High Voltage Input Low Voltage Input Hysteresis kHz V V kHz Hz V V V V V V V V V IOUT = 3 mA Determined by external Rset resistor VDDD = 3.3 V VDDD = 3.3 V 2 30 kHz input to 50 MHz output HSYNC in to CLK out IOUT = 4 mA IOUT = -4 mA 1 Schmitt trigger active Analog Input (HSYNC/VSYNC) SDA, SCL Digital Inputs Input High Voltage Input Low Voltage I2CADDR Digital Input High Voltage Input Low Voltage Input VIH VIL VOL VOH SDA Digital Output SDA Output Low Voltage SDA Output High Voltage LVCMOS Outputs (CLK, HSYNC_out, VSYNC_out, LOCK) Output Frequency, ICS1527-110GLF Output Frequency, ICS1527-60GLF Duty Cycle Jitter, STJ, RMS Jitter, STJ, pk-pk Jitter, Input-Output Output Low Voltage Output High Voltage HSYNC to HSYNC_out propagation delay (without Schmitt-trigger) Fs Fs SDC STJ STJ IOJ VOL VOH 2.4 2 9 2.5 2.5 45 50 0.027 0.200 2.500 0.4 110 60 55 MHz MHz % ns ns ns V V ns MDS1527 G 9 Revision 110905 In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1 w w w. i c s t . c o m ICS1527 Data Sheet Section 5 AC/DC Operating Conditions Parameter HSYNC to HSYNC_out propagation delay (with Schmitt-trigger) CLK to HSYNC_out/ VSYNC_out skew Clock and HSYNC_out/VSYNC_out Transition Time - Rise Clock and HSYNC_out/VSYNC_out Transition Time - Fall LOCK Transition Time - Rise LOCK Transition Time - Fall Symbol Min. Typical 6 Max. 10 Units ns Notes 1 1.0 TCR 1.0 1.5 ns ns 2 TCF 1.0 1.5 ns 2 TLR TLF 3.0 2.0 ns ns 2 2 Note 1--Measured between chosen edge of HSYNC (00h:2) and rising edge of output Note 2--Measured at 110 MHz, 3.3 VDC, 25oC, 15 pF, unterminated MDS 1527 G 10 Revision 110905 In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1 w w w. i c s t . c o m ICS1527 Data Sheet Section 6 Package Outline and Package Dimensions Section 6 Package Outline and Package Dimensions 16-pin TSSOP 4.40 mm body, 0.65 mm pitch Package dimensions are kept current with JEDEC Publication No. 95 16 Millimeters Symbol Min Max Inches Min Max E1 INDEX AREA E 12 D A A1 A2 b C D E E1 e L aaa -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 A2 A1 A c -Ce b SEATING PLANE aaa C L Section 7 Ordering Information Marking 1527G2LF 1527G2LF 1527G1LF 1527G1LF Part / Order Number ICS1527G-60LF ICS1527G-60LFT ICS1527G-110LF ICS1527G-110LFT Shipping packaging Tubes Tape & Reel Tubes Tape & Reel Package 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP Temperature 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS1527 G 11 Revision 110905 In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1 w w w. i c s t . c o m |
Price & Availability of ICS1527 |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |