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19-2223; Rev 1; 1/02
Quad Differential LVECL/LVPECL Buffer/Receivers
General Description
The MAX9400/MAX9402/MAX9403/MAX9405 are extremely fast, low-skew quad LVECL/ECL or LVPECL/ PECL buffer/receivers designed for high-speed data and clock driver applications. These devices feature an ultra-low propagation delay of 335ps and channel-tochannel skew of 16ps in asynchronous mode with 86mA supply current. The four channels can be operated synchronously with an external clock, or in asynchronous mode determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. A variety of input and output terminations are offered for maximum design flexibility. The MAX9400 has open inputs and open emitter outputs. The MAX9402 has open inputs and 50 series outputs. The MAX9403 has 100 differential input impedance and open emitter outputs. The MAX9405 has 100 differential input impedance and 50 series outputs. These devices operate with a supply voltage of (VCC VEE) = 2.375V to 5.5V, and are specified for operation from -40C to +85C. These devices are offered in space-saving 32-pin 5mm 5mm TQFP and 32-lead 5mm 5mm QFN packages.
Features
o 400mV Differential Output at 3.0GHz Data Rate o 335ps Propagation Delay in Asynchronous Mode o 8ps Channel-to-Channel Skew in Synchronous Mode o Integrated 50 Outputs (MAX9402/MAX9405) o Integrated 100 Inputs (MAX9403/MAX9405) o Synchronous/Asynchronous Operation
MAX9400/MAX9402/MAX9403/MAX9405
Ordering Information
PART TEMP RANGE PINDATA OUTPUT PACKAGE INPUT Open Open Open Open 100 100 100 100 Open Open 50 50 Open Open 50 50
MAX9400EHJ -40C to +85C 32 TQFP MAX9400EGJ* -40C to +85C 32 QFN MAX9402EHJ -40C to +85C 32 TQFP MAX9402EGJ* -40C to +85C 32 QFN MAX9403EHJ -40C to +85C 32 TQFP MAX9403EGJ* -40C to +85C 32 QFN MAX9405EHJ -40C to +85C 32 TQFP MAX9405EGJ* -40C to +85C 32 QFN
Applications
Data and Clock Driver and Buffer Central Office Backplane Clock Distribution DSLAM Backplane Base Station ATE
*Future product--contact factory for availability.
Pin Configurations
OUT0 VCC VEE IN0 IN0 IN1 26 IN1 25 24 VCC 23 OUT1 22 OUT1 21 VEE 20 VEE 19 OUT2 18 OUT2 17 VCC 9 IN3 10 IN3 11 VCC 12 OUT3 13 OUT3 14 VEE 15 IN2 16 IN2
TOP VIEW
32 VCC SEL SEL CLK CLK 1 2 3 4 5 6 7 8
31
30
29
28
OUT0
27
Functional Diagram appears at end of data sheet.
EN EN VCC
MAX9400 MAX9402 MAX9403 MAX9405
TQFP (5mm x 5mm)
Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Quad Differential LVECL/LVPECL Buffer/Receivers MAX9400/MAX9402/MAX9403/MAX9405
ABSOLUTE MAXIMUM RATINGS
VCC to VEE ................................................................-0.3V to +6V Inputs to VEE...............................................-0.3V to (VCC + 0.3V) Differential Input Voltage .......................................................3V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA Continuous Power Dissipation (TA = +70C) 32-Pin 5mm x 5mm TQFP (derate 9.5mW/C above +70C) .................................761mW 32-Lead 5mm x 5mm QFN (derate 21.3mW/C above +70C) ...................................1.7W Junction-to-Ambient Thermal Resistance in Still Air 32-Pin 5mm x 5mm TQFP ........................................+105C/W 32-Lead 5mm x 5mm QFN ........................................+47C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow 32-Pin 5mm x 5mm TQFP .........................................+73C/W Junction-to-Case Thermal Resistance 32-Pin 5mm x 5mm TQFP .........................................+25C/W 32-Lead 5mm x 5mm QFN .........................................+2C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (Inputs and Outputs) ........................2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 5.5V, MAX9400/MAX9403 outputs terminated with 50 1% to VCC - 2.0V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, TA = +25C, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER SYMBOL CONDITIONS MIN VEE + 1.4 VEE VCC - VEE < +3.0V VCC - VEE +3.0V MAX9400/ MAX9402 Input Current IIH, IIL MAX9403/ MAX9405 EN, EN, SEL, SEL , IN_, IN_, CLK, or CLK = VIHD or VILD EN, EN, SEL, SEL, CLK, or CLK = VIHD or VILD 0.2 0.2 -10 -10 86 TYP MAX UNITS
INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL) Differential Input High Voltage Differential Input Low Voltage VIHD VILD Figure 1 Figure 1 VCC VCC 0.2 VCC VEE 3.0 25 A 25 114 V V
Differential Input Voltage
VID
Figure 1
V
Differential Input Resistance OUTPUTS (OUT_, OUT_) Differential Output Voltage Output Common-Mode Voltage Internal Current Source Output Impedance POWER SUPPLY Supply Current
RIN VOH VOL VOCM ISINK ROUT
MAX9403/MAX9405
Figure 1 Figure 1 MAX9402/MAX9405, Figure 2 MAX9402/MAX9405, Figure 2 MAX9402/MAX9405 MAX9400/MAX9403
600 VCC 1.5 6.5 40
660 VCC 1.25 8.3 50 150 86 VCC 1.1 10 60 180 118
mV V mA
IEE
mA
2
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Quad Differential LVECL/LVPECL Buffer/Receivers
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 5.5V, outputs terminated with 50 1% to VCC - 2.0V, enabled, CLK = 3.2GHz, fIN = 1.6GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.2V, VIHD - VILD = 0.2V to smaller of |VCC - VEE| or 3V, unless otherwise noted. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 0.9V, VILD = VCC 1.7V, TA = +25C, unless otherwise noted.) (Notes 1, 4)
PARAMETER IN-to-OUT Differential Propagation Delay CLK-to-OUT Differential Propagation Delay IN-to-OUT Channel-to-Channel Skew (Note 5) CLK-to-OUT Channel-toChannel Skew (Note 5) Maximum Clock Frequency Maximum Data Frequency Added Random Jitter (Note 6) SYMBOL tPLH1 tPHL1 tPLH2 tPHL2 tSKD1 tSKD2 fCLK(MAX) fIN(MAX) tRJ CONDITIONS MAX9400/MAX9403 MAX9402/MAX9405 MAX9400/MAX9403 MAX9402/MAX9405 SEL = high SEL = low VOH - VOL 500mV, SEL = low VOH - VOL 400mV, SEL = high SEL = low, fCLK = 3.0GHz clock, fIN = 1.5GHz SEL = high, fIN = 2GHz SEL = low, fCLK = 3.0GHz, IN_ = 3.0Gbps 223 - 1 PRBS pattern tDJ SEL = high, IN = 2.0Gbps 223 - 1 PRBS pattern Figure 4 Figure 4 Figure 3 Figure 3 80 80 80 80 0.2 120 120 1 3.0 2 0.64 0.74 17 40 1.3 1.5 30 ps(P-P) 55 ps ps ps ps ps/C SEL = high, Figure 3 SEL = low, Figure 4 MIN 237 237 397 397 TYP 335 335 475 475 16 8 MAX 437 437 597 597 80 55 UNITS ps ps ps ps GHz GHZ ps(RMS)
MAX9400/MAX9402/MAX9403/MAX9405
Added Deterministic Jitter (Note 6) IN-to-CLK Setup Time CLK-to-IN Hold Time Output Rise Time Output Fall Time Propagation Delay Temperature Coefficient
tS tH tR tF tPD/ T
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25C. DC limits are guaranteed by design and characterization over the full operating temperature range. Note 4: Guaranteed by design and characterization. Limits are set to 6 sigma. Note 5: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 6: Device jitter added to the input signal.
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3
Quad Differential LVECL/LVPECL Buffer/Receivers MAX9400/MAX9402/MAX9403/MAX9405
Typical Operating Characteristics
(VCC - VEE = 3.3V, MAX9400, outputs terminated with 50 1% to VCC - 2.0V, enabled, SEL = high, CLK = 2.0GHz, fIN = 1.0GHz, input transition time = 125ps (20% to 80%), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT (IEE) vs. TEMPERATURE
MAX9400 toc01
OUTPUT AMPLITUDE (VOH - VOL) vs. IN_ FREQUENCY
MAX9400 toc02
OUTPUT RISE/FALL vs. TEMPERATURE
MAX9400 toc03
95
1000
100
OUTPUT RISE/FALL TIME (ps)
OUTPUT AMPLITUDE (mV)
90 SUPPLY CURRENT (mA)
800
90 tR 80 tF
85
600
80
400
75
200
70
70 -40 -15 10 35 60 85 TEMPERATURE (C)
0 0 500 1000 1500 2000 2500 3000 3500 IN_ FREQUENCY (MHz)
60 -40 -15 10 35 60 85 TEMPERATURE (C)
IN-TO-OUT PROPAGATION DELAY vs. TEMPERATURE
MAX9400 toc04
CLK-TO-OUT PROPAGATION DELAY vs. TEMPERATURE
MAX9400 toc05
355 350 PROPAGATION DELAY (ps) 345 340 335 330 325 -40 -15 10 35 60 tPLH tPHL
520
PROPAGATION DELAY (ps)
500
480
tPLH2 tPHL2
460
440 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
4
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Quad Differential LVECL/LVPECL Buffer/Receivers
Pin Description
PIN 1, 8,11, 17, 24, 30 2 3 4 5 6 7 9 10 12 13 14, 20, 21, 27 15 16 18 19 22 23 25 26 28 29 31 32 -- NAME VCC FUNCTION Positive Supply Voltage. Bypass VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four channels to operate in synchronous mode. Inverting Differential Select Input Noninverting Differential Clock Input Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs to the outputs when SEL = low. Noninverting Differential Output Enable Input. Setting EN = high and EN = low (differential high) enables the outputs. Setting EN = low and EN = high (differential low) drives outputs low. Inverting Differential Output Enable Input Noninverting Differential Input 3 Inverting Differential Input 3 Inverting Differential Output 3 Noninverting Differential Output 3 Negative Supply Voltage Noninverting Differential Input 2 Inverting Differential Input 2 Inverting Differential Output 2 Noninverting Differential Output 2 Noninverting Differential Output 1 Inverting Differential Output 1 Inverting Differential Input 1 Noninverting Differential Input 1 Noninverting Differential Output 0 Inverting Differential Output 0 Inverting Differential Input 0 Noninverting Differential Input 0 Exposed Paddle (MAX940_EGJ only). Connected to VEE internally. See package dimensions.
MAX9400/MAX9402/MAX9403/MAX9405
SEL SEL CLK CLK EN EN IN3 IN3 OUT3 OUT3 VEE IN2 IN2 OUT2 OUT2 OUT1 OUT1 IN1 IN1 OUT0 OUT0 IN0 IN0 EP
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5
Quad Differential LVECL/LVPECL Buffer/Receivers MAX9400/MAX9402/MAX9403/MAX9405
Detailed Description
The MAX9400/MAX9402/MAX9403/MAX9405 are extremely fast, low-skew quad LVECL/ECL or LVPECL/ PECL buffer/receivers designed for high-speed data and clock driver applications. The devices feature an ultra-low propagation delay of 335ps and channel-tochannel skew of 16ps in asynchronous mode with an 86mA supply current. The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. A variety of input and output terminations are offered for maximum design flexibility. The MAX9400 has open inputs and open-emitter outputs. The MAX9402 has open inputs and 50 series outputs. The MAX9403 has 100 differential input impedance and open-emitter outputs. The MAX9405 has 100 differential input impedance and 50 series outputs. The CLK signal is ignored in this mode. In asynchronous mode, the CLK signal should be set to either a logic low or high state to minimize noise coupling.
Synchronous Operation
Setting SEL = low and SEL = high enables all four channels to operate in synchronous mode. In this mode, buffered inputs are clocked into flip-flops simultaneously on the rising edge of the differential clock input (CLK and CLK).
Differential Signal Input Limit
The maximum signal magnitude of the differential inputs is VCC - VEE or 3V, whichever is less.
Applications Information
Input Bias
Unused inputs should be biased or driven as shown in Figure 5. This avoids noise coupling that might cause toggling at the unused outputs.
Supply Voltage
The MAX9400/MAX9402/MAX9403/MAX9405 are designed for operation with a single supply. Using a single negative supply of VEE = -2.375V to -5.5V (VCC = ground) yields LVECL/ECL-compatible input and output levels. Using a single positive supply of VCC = 2.375V to 5.5V (VEE = ground) yields LVPECL/PECL input and output levels.
Output Termination
Terminate open-emitter outputs (MAX9400/MAX9403) through 50 to VCC - 2V or use an equivalent Thevenin termination. Terminate both outputs and use identical termination on each for the lowest output-to-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if OUT_ is used as a single-ended output, terminate both OUT_ and OUT_. Ensure that the output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device's total thermal limits should be observed.
Data Inputs
The MAX9400/MAX9402 have open inputs and require external termination. The MAX9403/MAX9405 have integrated 100 differential input termination resistors from IN_ to IN_, reducing external component count.
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to maximize the performance and noise immunity. Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors as close to the device as possible with the 0.01F capacitor closest to the device pins. Use multiple bypass vias for connection to minimize inductance.
Outputs
The MAX9402/MAX9405 have internal 50 series output termination resistors and 8mA internal pulldown current sources. Using integrated resistors reduces external component count. The MAX9400/MAX9403 have open-emitter outputs. An external termination is required. See the Output Termination section.
Circuit Board Traces
Input and output trace characteristics affect the performance of the MAX9400/MAX9402/MAX9403/MAX9405. Connect each of the inputs and outputs to a 50 characteristic impedance trace. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by maintaining the distance between differential traces and avoid sharp corners. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 char-
Enable
Setting EN = high and EN = low enables the device. Setting EN = low and EN = high forces the outputs to a differential low, and all changes on CLK, SEL, and IN_ are ignored.
Asynchronous Operation
Setting SEL = high and SEL = low enables the four channels to operate independently as buffer/receivers.
6
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Quad Differential LVECL/LVPECL Buffer/Receivers
acteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces.
Chip Information
TRANSISTOR COUNT: 713 PROCESS: Bipolar
MAX9400/MAX9402/MAX9403/MAX9405
VCC VID VID = 0V
VIHD (MAX)
VCC
VILD (MAX) VOH - VOL VIHD (MIN) VID VEE INPUT VOLTAGE DEFINITION VID = 0V VILD (MIN) OUTPUT VOLTAGE DEFINITION VOCM
VOH
VOL
VEE
Figure 1. Input and Output Voltage Definitions
IN_
IN_ 100k
IN_
IN_
MAX9420/MAX9421
MAX9422/MAX9423
VCC
VCC
50 OUT_ 50 OUT_
OUT_ OUT_ 8mA 8mA VEE
MAX9420/MAX9422
MAX9421/MAX9423
Figure 2. Input and Output Configurations
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7
Quad Differential LVECL/LVPECL Buffer/Receivers MAX9400/MAX9402/MAX9403/MAX9405
IN_ VIHD - VILD IN_
tPLH1 OUT_ VOH - VOL OUT_
tPHL1
80%
VOH - VOL
80%
OUT_ - OUT_
DIFFERENTIAL OUTPUT WAVEFORM
20%
VOH - VOL
20%
tR
tF SEL = HIGH EN = HIGH
Figure 3. IN-to-OUT Propagation Delay and Transition Timing Diagram
CLK VIHD - VILD CLK
tH IN_
tS
tH
VIHD - VILD IN_
tPLH2 OUT_ VIHD - VILD OUT_
tPHL2
SEL = LOW EN = HIGH
Figure 4. CLK-to-OUT Propagation Delay Timing Diagram
8
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Quad Differential LVECL/LVPECL Buffer/Receivers MAX9400/MAX9402/MAX9403/MAX9405
VCC VCC
IN_ OUT_ 100 OUT_ IN_ 1k 1/4 MAX9400/MAX9402
IN_ OUT_ 100 OUT_ IN_ 1k 1/4 MAX9403/MAX9405
VEE
VEE
Figure 5. Input Bias Circuits for Unused Inputs
Pin Configurations (continued)
OUT0 OUT0
VCC
TOP VIEW
IN0 IN0 32 31
VEE
IN1
30
29
28
27
*
26
25
*
IN1
VCC SEL SEL CLK CLK EN EN VCC
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16
* *
24 23 22
VCC OUT1 OUT1 VEE VEE OUT2 OUT2 VCC
MAX9400 MAX9402 MAX9403 MAX9405
*EXPOSED PADDLE
21 20 19 18 17
9
IN3
IN3
VEE
OUT3
QFN-EP*
*EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO VEE.
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OUT3
VCC
IN2
IN2
9
Quad Differential LVECL/LVPECL Buffer/Receivers MAX9400/MAX9402/MAX9403/MAX9405
Functional Diagram
IN0 IN0 D D CK CK Q Q 1
0
OUT0 OUT0
IN1 IN1 D D CK CK Q Q
1
0
OUT1 OUT1
IN2 IN2 D D CK CK Q Q
1
0
OUT2 OUT2
IN3 IN3 D D CK CK Q Q
1
0
OUT3 OUT3
CLK CLK
SEL SEL
EN EN
10
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Quad Differential LVECL/LVPECL Buffer/Receivers
Package Information
32L TQFP, 5x5x01.0.EPS
MAX9400/MAX9402/MAX9403/MAX9405
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11
Quad Differential LVECL/LVPECL Buffer/Receivers MAX9400/MAX9402/MAX9403/MAX9405
Package Information (continued)
12
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Quad Differential LVECL/LVPECL Buffer/Receivers
Package Information (continued)
MAX9400/MAX9402/MAX9403/MAX9405
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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