View ICS87949I-01_586532.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR
FEATURES
* 15 single ended LVCMOS/LVTTL outputs, 7 typical output impedance * Selectable LVCMOS/LVTTL or LVPECL clock inputs * CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum input frequency: 250MHz * Output skew: 250ps (maximum) * Part-to-part skew: 1ns (maximum) * Full 3.3V or mixed 3.3V core/2.5V output supply * -40C to 85C ambient operating temperature * Functionally compatible to the MPC949 in a smaller footprint requiring less board space
ICS87949I-01
GENERAL DESCRIPTION
The ICS87949I-01 is a low skew, /1, /2 Clock Generator and a member of the HiPerClock STM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87949I-01 has selectable single ended clock or LVPECL clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 15 to 30 by utilizing the ability of the outputs to drive two series terminated lines.
ICS
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS87949I-01 is characterized at 3.3V core/3.3V output and 3.3V core/2.5V output. Guaranteed bank, output and partto-part skew characteristics make the ICS87949I-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_SEL CLK0 CLK1 PCLK nPCLK PCLK_SEL
1
0
0
PIN ASSIGNMENT
GND GND GND GND VDDB VDDA VDDB QA0 QA1 QB0 QB1 QB2
/1 /2
R
1
1
48 47 46 45 44 43 42 41 40 39 38 37 MR/nOE CLK_SEL
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
GND GND QD0 VDDD QD1 GND QD2 VDDD QD3 GND QD4 VDDD
36 35 34 33 32 31 30 29 28 27 26 25
nc GND QC0 VDDC QC1 GND QC2 VDDC QC3 GND GND QD5
VDD QA0, QA1 CLK0 CLK1 PCLK nPCLK QB0:QB2 PCLK_SEL DIV_SELA DIV_SELB DIV_SELC QC0:QC3 DIV_SELD
DIV_SELA
0 1
ICS87949I-01
DIV_SELB
0 1
DIV_SELC
0
QD0:QD5
1
DIV_SELD MR/nOE
87949AYI-01
48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 1, 2003
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR
Type Description Active HIGH Master Reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and Pulldown the outputs are tri-stated (HiZ). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1. When Pulldown LOW, selects CLK0. LVCMOS / LVTTL interface levels. Positive supply pin. Pullup Pullup LVCMOS / LVTTL clock inputs. Inver ting differential LVPECL clock input. Pulldown Non-inver ting differential LVPECL clock input. Pulldown PCLK select input. LVCMOS / LVTTL interface levels. Controls frequency division for Bank A outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank C outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank D outputs. Pulldown LVCMOS / LVTTL interface levels. Power supply ground. Bank D outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank D outputs. Bank C outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank C outputs. No connect. Positive supply pins for Bank B outputs. Bank B outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Bank A outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank A outputs.
ICS87949I-01
TABLE 1. PIN DESCRIPTIONS
Number Name
1
MR/nOE
Input
2 3 4, 5 6 7 8 9 10 11 12 13, 14, 18, 22, 26, 27, 31, 35, 39, 43, 44, 48 15, 17, 19 21, 23, 25 16, 20, 24, 28, 30, 32, 34 29, 33 36 37, 41 38, 40, 42 45, 47 46
CLK_SEL VDD CLK0, CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND QD0, QD1, QD2, QD3, QD4, QD5 VDDD QC3, QC2, QC1, QC0 VDDC nc VDDB QB2, QB1, QB0 QA1, QA0 VDDA
Input Power Input Input Input Input Input Input Input Input Power Output Power Output Power Unused Power Output Output Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87949AYI-01
www.icst.com/products/hiperclocks.html
2
REV. A OCTOBER 1, 2003
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR
Test Conditions Minimum Typical 4 51 51 VDD, VDDx = 3.465V VDD, VDDx = 2.625V 5 23 16 7 12 Maximum Units pF K K pF pF
ICS87949I-01
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CP D ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output); NOTE 1 Output Impedance
NOTE 1: VDDx denotes VDDA, VDDB, VDDC, VDDD.
TABLE 3. FUNCTION TABLE
MR/nOE 1 0 0 0 0 0 0 0 0 DIV_SELA X 0 1 X X X X X X Inputs DIV_SELB X X X 0 1 X X X X DIV_SELC X X X X X 0 1 X X DIV_SELD X X X X X X X 0 1 QA0:QA1 Hi Z fIN/1 fIN/2 Active Active Active Active Active Active Outputs QB0:QB2 QC0:QC3 Hi Z Hi Z Active Active Active Active fIN/1 Active fIN/2 Active Active fIN/1 Active fIN/2 Active Active Active Active QD0:QD5 Hi Z Active Active Active Active Active Active fIN/1 fIN/2
87949AYI-01
www.icst.com/products/hiperclocks.html
3
REV. A OCTOBER 1, 2003
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ICS87949I-01
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = -40C TO 85C
Symbol Parameter VDD Positive Supply Voltage Output Supply Voltage; NOTE 1 VDDx Power Supply Current IDD Output Supply Current; NOTE 2 IDDx NOTE 1: VDDx denotes VDDA, VDDB, VDDC, VDDD. NOTE 2: IDDx denotes IDDA, IDDB, IDDC, IDDD. Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 60 20 Units V V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = -40C TO 85C
Symbol Parameter DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA: DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 2.6 0.5 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1. 3 150 5 Units V V V V A A A A V V
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL VOH VOL
Input Low Current
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
87949AYI-01
www.icst.com/products/hiperclocks.html
4
REV. A OCTOBER 1, 2003
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR
Test Conditions PCLK nPCLK PCLK nPCLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.3 1 VDD Minimum Typical Maximum 150 5 Units A A A A V V
ICS87949I-01
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Input Frequency Propagation Delay, NOTE 1 Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise/Fall Time; NOTE 5 Output Duty Cycle Output Enable Time;NOTE 5 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 20% to 80% Measured with outputs in /1 f = 10MHz 400 40 2.1 Test Conditions Minimum Typical Maximum 250 5 100 300 1 950 60 5 Units MHz ns ps ps ns ps % ns ns
tsk(b) tsk(o) tsk(pp)
tR/ tF odc tEN
Output Disable Time;NOTE 5 f = 10MHz 5 tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
87949AYI-01
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 1, 2003
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR
Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 60 20 Units V V mA mA
ICS87949I-01
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDx IDD Parameter Positive Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current
IDDx Output Supply Current; NOTE 2 NOTE 1: VDDx denotes VDDA, VDDB, VDDC, VDDD. NOTE 2: IDDx denotes IDDA, IDDB, IDDC, IDDD.
TABLE 4E. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = -40C TO 85C
Symbol Parameter Input High Voltage DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 1.8 0.5 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 Units V V V V A A A A V V
VIH
VIL
Input Low Voltage
IIH
Input High Current
IIL VOH VOL
Input Low Current
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Section, 3.3V/2.5V Output Load Test Circuit.
TABLE 4F. LVPECL DC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current PCLK nPCLK PCLK nPCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.3 1 VDD Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
87949AYI-01
www.icst.com/products/hiperclocks.html
6
REV. A OCTOBER 1, 2003
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR
Test Conditions Minimum 2.0 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 20% to 80% Measured with outputs in /1 f = 10MHz 400 40 Typical Maximum 250 4.6 65 250 1 950 60 5 Units MHz ns ps ps ns ps % ns ns
ICS87949I-01
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Input Frequency Propagation Delay, NOTE 1 Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise/Fall Time; NOTE 5 Output Duty Cycle Output Enable Time;NOTE 5
tsk(b) tsk(o) tsk(pp)
tR/ tF odc tEN
Output Disable Time;NOTE 5 f = 10MHz 5 tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
87949AYI-01
www.icst.com/products/hiperclocks.html
7
REV. A OCTOBER 1, 2003
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR
ICS87949I-01
PARAMETER MEASUREMENT INFORMATION
1.65V0.15V 2.05V5% 1.25V5%
VDD, VDDx
SCOPE
Qx
V DD V DDx
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V0.15V
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
VDD
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
V
DDx
nPCLK V PCLK
PP
Qx
2
Cross Points
V
CMR
V
DDx
Qy
2 tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
PART 1 Qx
V
DDx
OUTPUT SKEW
80% 20%
tR tF 80% 20%
2
PART 2 Qy
V
DDx
Clock Outputs
2 tsk(pp)
PART-TO-PART SKEW
OUTPUT RISE/FALL TIME
VDD 2
CLK0, CLK1 nPCLK
2 Pulse Width t
PERIOD
V
DDx
QAx, QBx, QCx, QDx
PCLK
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
87949AYI-01
PROPAGATION DELAY
REV. A OCTOBER 1, 2003
www.icst.com/products/hiperclocks.html
8
odc =
t PW
QAx,QBx, QCx, QDx
tPD
VDDx 2
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR APPLICATION INFORMATION
ICS87949I-01
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87949AYI-01
www.icst.com/products/hiperclocks.html
9
REV. A OCTOBER 1, 2003
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR
gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
ICS87949I-01
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug-
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm
2.5V
3.3V
2.5V
R3 120
SSTL
R2 50
R4 120
PCLK
Zo = 60 Ohm
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
nPCLK
HiPerClockS PCLK/nPCLK
R1 120
R2 120
FIGURE 3A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V 3.3V
R3 125
R4 125
Zo = 50 Ohm
Zo = 50 Ohm
CLK
Zo = 50 Ohm
LVDS
C1
R3 1K
R4 1K
PCLK
R5 100
C2
nPCLK
nCLK
LVPECL
R1 84
Zo = 50 Ohm
HiPerClockS Input
HiPerClockS PCL K/n PC LK
R2 84
R1 1K
R2 1K
FIGURE 3C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
R3 84
R4 84
PCLK
Zo = 50 Ohm
C2
nPCLK
HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 3E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
87949AYI-01
www.icst.com/products/hiperclocks.html
10
REV. A OCTOBER 1, 2003
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR
ample of the ICS87949I-01 LVCMOS clock buffer. In this example, the input is driven by an LVCMOS driver.
ICS87949I-01
SCHEMATIC EXAMPLE
This application note provides general design guide using ICS87949I-01 LVCMOS buffer. Figure 4 shows a schematic ex-
R1
43
Zo = 50
VDDO
VDD
U1
VDD
R8 1K
RS
Zo = 50
LVCMOS CLOCK
VDD=3.3V
VDDO=3.3V or 2.5V
Logic Input Pin Examples
VDD
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install
13 14 15 16 17 18 19 20 21 22 23 24
ICS87949I-01
GND GND QD0 VDDD QD1 GND QD2 VDDD QD3 GND QD4 VDDD
R5 1K
1 2 3 4 5 6 7 8 9 10 11 12
GND QA0 VDDA QA1 GND GND QB0 VDDB QB1 GND QB2 VDDB
C1 0.1uF
48 47 46 45 44 43 42 41 40 39 38 37
VDD
MR/nOE CLK_SEL VDD CLK0 CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD
nc GND QC0 VDDC QC1 GND QC2 VDDC QC3 GND GND QD5
36 35 34 33 32 31 30 29 28 27 26 25
R2
43
Zo = 50
To Logic Input pins
RD1 Not Install
To Logic Input pins
RD2 1K
(U1-16)
VDDO
(U1-20)
(U1-24)
(U1-29)
(U1-33)
(U1-37)
(U1-41)
(U1-46)
C3 0.1uF
C4 0.1uF
C5 0.1uF
C6 0.1uF
C7 0.1uF
C8 0.1uF
C9 0.1uF
C10 0.1uF
FIGURE 4. EXAMPLE ICS87949I-01 LVCMOS CLOCK OUTPUT BUFFER SCHEMATIC
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
48 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87949I-01 is: 1545
87949AYI-01
www.icst.com/products/hiperclocks.html
11
REV. A OCTOBER 1, 2003
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR
48 LEAD LQFP
ICS87949I-01
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
87949AYI-01
www.icst.com/products/hiperclocks.html
12
REV. A OCTOBER 1, 2003
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 LVCMOS / LVTTL CLOCK GENERATOR
Marking ICS87949AYI01 ICS87949AYI01 Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
ICS87949I-01
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87949AYI-01 ICS87949AYI-01T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87949AYI-01
www.icst.com/products/hiperclocks.html
13
REV. A OCTOBER 1, 2003

▲Up To Search▲

Price & Availability of ICS87949I-01

	To Download ICS87949I-01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .