 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Preliminary Technical Data FEATURES -4 to 20dB Gain Range 1 dB Step Size 0.2 dB Differential input and output 150 Differential Input Open Collector Differential Output 8dB noise figure @ maximum gain OIP3 of ~50dBm at 140MHz -3 dB bandwidth of 690 MHz Parallel 5-bit Control Interface Wide input dynamic range Power-down feature Single 5V Supply Operation 24 Lead LFCSP 4 x 4 mm Package 24dB Range, 1dB Step Size Programmable VGA AD8375 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Differential ADC drivers High IF Sampling Receivers High Output Power IF Amplification Instrumentation Figure 1. GENERAL DESCRIPTION The AD8375 is a digitally controlled, variable gain wide bandwidth amplifier that provides precise gain control, high IP3 and low noise figure. The excellent distortion performance and high signal bandwidth makes the AD8375 an excellent gain control device for a variety of receiver applications. For wide input dynamic range applications, the AD8375 provides a broad 24dB gain range with 1 dB resolution. The gain is adjusted through a 5-pin control interface and can be driven using standard TTL levels. The open-collector outputs provide a flexible interface, allowing the overall signal gain to be set by the loading resistance. The AD8375 offers a maximum transconductance gain of 67 m-1's, resulting in a signal gain of 20dB when driving a 150-Ohm load. The maximum signal gain increases to ~24dB when driving a 250-Ohm differential load. Using a high speed SiGe process and incorporating proprietary distortion cancellation techniques, the AD8375 achieves 50 dBm output IP3 at 140 MHz. The AD8375 is powered on by applying the appropriate logic level to the PWUP pin. The quiescent current of the AD8375 is typically 130mA. When powered down, the AD8375 consumes less than 5mA and offers excellent input to output isolation. The gain setting is preserved when powered down. Fabricated on an ADI's high speed SiGe process, the AD8375 provides precise gain adjustment capabilities with good distortion performance. The AD8375 amplifier comes in a compact, thermally enhanced 4 x 4mm 24-lead LFCSP package and operates over the temperature range of -40C to +85C. Rev. PrB March 13, 2007 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2007 Analog Devices, Inc. All rights reserved. AD8375 SPECIFICATIONS Preliminary Technical Data VS = 5 V, T = 25C, ZS = ZL = 150 at 100MHz, 2 V p-p differential output unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate INPUT STAGE Maximum Input Swing Differential Input Resistance Common-Mode Input Voltage CMRR GAIN Amplifier Transconductance Maximum Voltage Gain Minimum Voltage Gain Gain Step Size Gain Flatness Gain Temperature Sensitivity Gain Step Response OUTPUT STAGE Output Voltage Swing Output impedance NOISE/HARMONIC PERFORMANCE 46 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 70 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 140 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point Gain Code = 00000 Gain Code 11000 From Gain Code 00000 to 11000 Gain Code = 00000 over 20% fractional bandwidth for fC < 200MHz Gain Code = 00000 For VIN = 0.2V, Gain Code 10100 to 00000 -5.5 0.8 Conditions VOUT < 2 V p-p (5.2dBm) Min Typ 690 TBD TBD 150 2 TBD 0.58 0.067 0.076 Max Unit MHz V/nsec V p-p V dB -1 dB -2.5 1.2 dB dB dB mdB/C ns Pins VIN+ and VINFor linear operation (AV = 0dB) Differential Gain Code = 00000 20 -4 1.0 TBD TBD TBD 10 5k//1 Pins OUT+ and OUTAt P1dB, Gain Code = 00000 Differential Gain Code = 00000 VOUT = 2 V p-p VOUT = 2 V p-p 2 MHz spacing, +3 dBm per tone Gain Code = 00000 VOUT = 2 V p-p VOUT = 2 V p-p 2 MHz spacing, +3 dBm per tone Gain Code = 00000 VOUT = 2 V p-p VOUT = 2 V p-p 2 MHz spacing, +3 dBm per tone 8.5 -86 -91 50 19 dB dBc dBc dBm dBm 8.5 -94 -92 50 19 V p-p /pF 8.5 -94 -92 50 19 dB dBc dBc dBm dBm dB dBc dBc dBm dBm Rev. PrB | Page 2 of 6 Preliminary Technical Data Parameter 200 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point POWER-INTERFACE Supply Voltage Quiescent Current per Channel vs. Temperature Power Down Current vs. Temperature ENABLE INTERFACE Enable Threshold PWUP Input Bias Current GAIN CONTROL INTERFACE VIH VIL Maximum Input Bias Current Conditions Gain Code = 00000 VOUT = 2 V p-p VOUT = 2 V p-p 2 MHz spacing, +3 dBm per tone Min Typ 8.5 -85 -88 50 18 4.5 thermal connection made to exposed paddle under device -40C TA +85C PWUP Low -40C TA +85C 130 5.5 140 165 3 TBD 1.6 0.5 Pins A0, A1, A2, A3, A4 Max Unit dB dBc dBc dBm dBm V mA mA mA mA V nA V 0.8 900 nA AD8375 Pin PWUP Minimum voltage to enable the device Minimum voltage for a logic high Maximum voltage for a logic low 1.6 Table 2. Gain-Code versus Voltage Gain Look-Up Table 5-Bit Binary Gain Code 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 Voltage Gain (dB) 20 19 18 17 16 15 14 13 12 11 10 9 8 5-Bit Binary Gain Code 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 >11000 Voltage Gain (dB) 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -4 Rev. PrB | Page 3 of 6 AD8375 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage, VPOS PWUP, A0, A1, A2, A3, A4 Input Voltage, VIN+ ,VINInternal Power Dissipation JA (Exposed paddle soldered down) JA (Exposed paddle not soldered down) JC (At exposed paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 5.5 V -0.6 to (VPOS + 0.6V) -0.6 to +3.1V TBD mW TBDC/W TBDC/W TBDC/W TBDC -40C to +85C -65C to +150C TBDC Preliminary Technical Data Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrB | Page 4 of 6 Preliminary Technical Data PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS AD8375 Figure 2. 24 Lead LFCSP Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9, 10,12, 13, 23 11, 14, 20, 21, 22, 24 15, 17 16, 18 19 Mnemonic VCOM VIN+ VINA4 A3 A2 A1 A0 VPOS COMM VOUT+ VOUTPWUP Description Common Mode Pin. Typically bypassed to ground using external capacitor. Voltage Input Positive. Voltage Input Negative. The Most Significant Bit (MSB) for the 5-bit Gain Control Interface. MSB-1 for the Gain Control Interface. MSB-2 for the Gain Control Interface. LSB+1 for the Gain Control Interface. The Least Significant Bit (LSB) for the 5-bit Gain Control Interface. Positive Supply Pins. Should be bypassed to Ground using suitable bypass capacitor. Device Common (DC Ground). Positive Ouptut Pins (Open Collector). Require DC bias of +5V nominal. Negative Ouptut Pins (Open Collector). Require DC bias of +5V nominal. Chip Enable Pin. Rev. PrB | Page 5 of 6 AD8375 OUTLINE DIMENSIONS Preliminary Technical Data Figure2. 24-Lead LFCSP) ORDERING GUIDE Model AD8375ACPZ-WP AD8375ACPZ-REEL7 AD8375-EVALZ Temperature -40C to +85C -40C to +85C Package Description Waffle Pack, 24 Lead Frame Chip Scale Package 7" Reel, 24 Lead Frame Chip Scale Package Evaluation Board Package Option CP-24 CP-24 (c) 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06724-0-3/07(PrB) Rev. PrB | Page 6 of 6 |
Price & Availability of AD8375ACPZ-REEL7
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |