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LE25FV051T 3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
Command Definition
Table 2 contains a command list and a brief summary of the commands. The following is a detailed description of the options initiated by each command.
Read
Fig.5 shows the timing waveform of read operation. The read operation is initiated by READ command. After writing OPcode of "FFH" and following 24bit address and 16 dummy bits, SO is transformed into Low-impedance state, and the specified addresses' data are read out synchronously with SCK clock. While the SCK clock is continuously on, the device counts up the next address automatically and reads the data in order. When the address reaches its maximum, while the read operation still be continuing, the address is reset to the lowest one, and the device continues reading data from the beginning. When CS is set High so as to deselect the device, the read operation terminates with the output in Highimpedance state. Do not execute read operation while the device is in Byte_Program or Sector_Erase Cycle to prevent inadvertent writes.
memory contents within the addressed sector are erased and other sectors are not inadvertently erased. The erase operation begins with the rising edge of the CS pulse and terminates automatically by using an internal timer. Termination of this mode is found out by using Status Register Read.
Byte_Program Fig.8 shows the timing waveform of Byte_Program. Byte_Program command consists of 6 bus cycles from 1st bus cycle to 6th bus cycle, and stages the device for Byte programmable. To execute the Byte_Program operation, program address, program data and Dummy bits must be written to the command register after writing the OPcode of (10H). The program operation begins with the rising edge of the CS pulse and terminates automatically by using an internal timer. Termination of this mode is found out by using Status Register Read.
Reset
Fig.9 shows the timing waveform of Reset operation. Reset operation is effective while the device is already in Program or Erase mode. But the data of specified address are not guaranteed. The Reset Command can be provided as a means to safely abort the Erase or Program Command sequences. Following 4th bus cycles (erase or program) with a write of (FFH) in 5th bus cycle will safely abort the operation. Memory contents will not be altered.
Status_Register Read
Fig.6 shows the timing waveform of Status_Register Read. Status_Register can be read while the device is in Program or Erase mode. As is shown in the table below, the LSB (Least Significant Bit) of Status_Register is set to BSY with other bits intact. By setting CS to LOW and writing "9FH" in command register, the contents of the Status_Register come out from MSB. The LSB of the Status_Register stands for if the device is busy or not. Therefore,"0" stands for busy and "1" for not in Program or Erase mode. When CS goes High, Status Register reading terminates with the output pin in Highimpedance state.
7(MSB) X 6 X 5 X 4 X 3 X 2 X 1 X 0(LSB)
BSY
Hardware Write Protection
Setting WP to LOW prevents inadvertent writes by inhibiting write operation. As WP is connected internally to the Vcc, don't connect externally to any nodes when this function is not necessary. To prevent inadvertent writes during system power-up, LE25FV051T has poweron-reset circuit. To perform power up more safely, the usage of RESET is recommended as follows. By holding RESET LOW during system power up and setting to High after Vcc reaches operation voltage, inadvertent writes can be prevented (see Fig.10). Don't use this function except during power up. As RESET is connected to Vcc internally, don't connect externally to any nodes when this function is not necessary.
Sector_Erase
Fig.7 shows the timing waveform of Sector_Erase. Sector_Erase command consists of 6 bus cycles from 1st bus cycle to 6th bus cycle. This command stages the device for electrical erasing of all bytes within a sector. A sector contains 256 bytes. This sector erasability enhances the flexibility and usefulness of the LE25FV051T, since most applications only need to change a small number of bytes or sectors, not the entire chip. To execute the Sector_Erase operation, erase address, 2nd OPcode (D0H) and Dummy bits must be written to the command register after writing 1st OPcode of (20H). This two-step sequence ensures that only
Decoupling Capacitors
Ceramic capacitors (0.1 F) must be added between VCC and VSS to each device to assure stable flash memory operation.
SANYO Electric Co., Ltd. 3/10
LE25FV051T 3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
Absolute Maximum Stress Ratings
Storage Temperature ........................................................-55 C ~ 150 C Supply Voltage..................................................................-0.5 V ~ 4.6 V D.C. Voltage on Any Pin to Grand Potential .....................-0.5 V ~ Vcc + 0.5 V
Permanent device damage may occur if ABSOLTE MAXIMUM RATINGS are exceeded.
Operating Range
Ambient Temperature .......................................................0 C ~ 70 C Vcc ....................................................................................3.0 V ~ 3.6 V
DC Operating Characteristics
Symbol Parameter Min. ICCR Power Supply Current (Read) ICCW Power Supply Current (Write) ISB1 Standby Vcc Current (TTL input) ISB2 Standby Vcc Current (CMOS input) ILI ILO VIL VIH VOL VOH Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Vcc-0.2 -0.3 2.4 10 10 0.4 Vcc+0.3 0.2 A A V V V V 20 A 3 mA 45 mA Limit Max. 10 mA unit Test Condition
CS = VIL
SO, WP open
SI = VIL / VIH, f = 10MHz, VCC = VCC max. VCC = VCC max.
CS = VIH CS = VCC-0.3V
SO, WP , RESET open SO, WP , RESET open
VCC = VCC max.
VCC = VCC max. VIN = VSS ~ VCC, VCC = VCC max. VIN = VSS ~ VCC, VCC = VCC max. VCC = VCC max. VCC = VCC min. IOL = 100 A, VCC = VCC min. IOH = -100 A, VCC = VCC min.
Power-up Timing
Symbol tPU_READ tPU_WRITE tPU_RST Parameter Power-up to Read Operation(without using RESET ) Power-up to Write Operation(without using RESET ) From RESET goes High to Command Entry Minimum 10 10 1 Units ms ms s
Capacitance (Ta = 25 C, f = 1 MHz)
Symbol CDQ Description DQ Pin Capacitance Maximum 12 6 Unit pF pF Test Condition VDQ = 0V VIN = 0V
CIN Input Capacitance Note: These parameters are periodically sampled and are not 100% tested.
SANYO Electric Co., Ltd. 4/10
LE25FV051T 3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
AC Characteristics
Symbol fCLK tCSS tCSH tCPH tCHZ tDS tDH tCLH tCLL tCLZ tV tHO tSE tBP tRST Clock Frequency
CS setup time CS hold time CS standby pulse width CS to Hi-Z output
Parameter Min. 400 400 250
Limit Max. 10
unit MHz ns ns ns 250 ns ns ns ns ns ns 40 ns ns 4 35 4 ms s s
Data Setup time Data hold time SCK High pulse width SCK Low pulse width SCK to Lo-Z output SCK to output valid Output data hold time Sector Erase Cycle Time Byte Program Cycle time Write Reset Recovery Time
30 30 45 45 0 0
AC Test Conditions Input Pulse Level .................................................0 V ~ 3.0 V Input Rise/Fall Time ..............................................5 ns Input/Output Timing Level ...................................1.5V Input Load Levels..................................................30 pF
SANYO Electric Co., Ltd. 5/10
LE25FV051T 3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
Timing waveforms
Figure 3: Serial Input Timing Diagram ( SPI mode 0 )
tCPH
CS SCK SI SO
tcss
tCSH tDH
tDS
DATA VALID
High Impedance
High Impedance
(
SPI mode 3 )
tCPH
CS
tcss
tCSH tDS tDH
SCK SI SO
VALID
High Impedance
High Impedance
SANYO Electric Co., Ltd. 6/10
LE25FV051T 3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
Figure 4: Serial Output Timing Diagram ( SPI mode 0 )
CS
tCLH tCLL
SCK
tcLZ tHO
DATA VALID
tCSH tCHZ
SO
tV
SI
( SPI mode 3 )
CS
tCLL tCLH tCSH
SCK
tcLZ tHO
DATA VALID
tCHZ
SO
tV
SI
SANYO Electric Co., Ltd. 7/10
LE25FV051T 3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
(The following is described in SPI mode 0) Figure 5: Read Cycle Timing Diagram
CS
012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71
SCK SI SO
FFH Add. Add. Add. X X
N N+1
DATA MSB
N+2
DATA MSB
High Impedance
DATA MSB
Figure 6: Status Register Read Timing Diagram
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 23 24 31
SCK SI SO
9FH
High Impedance
MSB
DATA
DATA MSB
DATA MSB
SANYO Electric Co., Ltd. 8/10
LE25FV051T 3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
Figure 7: Sector_Erase Timing Diagram
Self-timed Sector Erase Cycle t SE
CS
012345678 15 16 23 24 31 32 39 40 47
SCK SI SO
20H Add. Add. X D0H X
High Impedance
Figure 8: Byte_Program Timing Diagram
Self-timed Byte Program Cycle t BP
CS
012345678 15 16 23 24 31 32 39 40 47
SCK SI SO
10H Add. Add. Add. PD X
High Impedance
SANYO Electric Co., Ltd. 9/10
LE25FV051T 3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
Figure 9: Reset Timing Diagram Reset Command is effective when the device is only in Erase or Program sequence (in tBP or tSE period).
t RST
CS
01234567
SCK SI SO
FFH
High Impedance
Figure 10: Command Entry Recover Timing from RESET goes High
Vcc
t PU_RST
RESET
SANYO Electric Co., Ltd. 10/10

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