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| 3-BIT SCANNABLE REGISTER SY10E212 SY100E212 FEATURES s s s s s s s Scannable version E112 driver Extended 100E VEE range of -4.2V to -5.5V 1025ps max. CLK to Output Dual differential outputs Master Reset Internal 75K input pull-down resistors Fully compatible with industry standard 10KH, 100K ECL levels s Fully compatible with Motorola MC10E/100E212 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E212 are scannable registered ECL drivers typically used as fan-out memory address drivers for ECL cache driving. In a VLSI array-based CPU design, use of the E212 allows the user to conserve array output cell functionality and also output pins. The input shift register is designed with control logic which greatly facilitates its use in boundary scan applications. PIN CONFIGURATION NC S-OUT SHIFT MR VCCO S-OUT D Q D2 Q2b Q2a Q2a Q2b 25 24 23 22 21 20 19 LOAD CLK D2 VEE D1 D0 S-IN Q2b Q2a BLOCK DIAGRAM 26 27 28 1 2 3 4 5 6 7 8 9 10 11 18 17 Q2b Q2a VCC Q1b Q1a Q1b Q1a TOP VIEW PLCC J28-1 16 15 14 13 12 D Q D1 Q1b Q1a Q1a Q1b VCCO Q0a Q0b Q0a Data Inputs Scan Input Scan Control Clock Master Reset Scan Output True Outputs D Q D0 S-IN LOAD SHIFT CLK MR Q0b Q0a Q0a Q0b PIN NAMES Pin D0 - D2 S-IN LOAD SHIFT CLK MR S-OUT Q[0:2]a, Q[0:2]b Q[0:2]a, Q[0:2]b VCCO Function LOAD/HOLD Control Inverting Outputs VCC to Output VCCO Rev.: C NC Q0b Amendment: /1 1 Issue Date: February, 1998 Micrel SY10E212 SY100E212 TRUTH TABLE LOAD L H X X SHIFT L L H X MR L L L H Mode Load Hold Shift Reset DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 80 80 96 96 -- -- 80 80 96 96 -- -- 80 92 96 110 Min. -- Typ. -- Max. 150 Min. -- TA = +25C Typ. -- Max. 150 -- TA = +85C Min. Typ. -- Max. 150 Unit A mA Condition -- -- AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol tPLH tPHL Parameter Propagation Delay to Output CLK MR CLK to S-OUT Set-up Time D SHIFT LOAD S-IN Hold Time D SHIFT LOAD S-IN Reset Recovery Within-Device Skew Within-Gate Skew Rise/Fall Times 20% to 80% Min. 575 575 575 175 150 225 150 250 300 225 300 600 -- -- 275 Typ. 800 800 800 25 -50 50 -50 25 100 0 100 350 100 50 425 Max. 1025 1025 1025 -- -- -- -- -- -- -- -- -- -- -- 650 Min. 575 575 575 175 150 225 150 250 300 225 300 600 -- -- 275 TA = +25C Typ. 800 800 800 25 -50 50 -50 25 100 0 100 350 100 50 425 Max. 1025 1025 1025 -- -- -- -- -- -- -- -- -- -- -- 650 TA = +85C Min. 575 575 575 175 150 225 150 250 300 225 300 600 -- -- 275 Typ. 800 800 800 25 -50 50 -50 25 100 0 100 350 100 50 425 Max. 1025 1025 1025 ps -- -- -- -- ps -- -- -- -- -- -- -- 650 ps ps ps ps -- 1 2 -- -- -- Unit ps Condition -- tS tH tRR tskew tskew tr tf NOTES: 1. Within-device skew is defined as identical transitions on similar paths through a device. 2. Within-gate skew is defined as the difference in delays between various outputs of a gate when driven from the same input. PRODUCT ORDERING CODE Ordering Code SY10E212JC SY10E212JCTR SY100E212JC SY100E212JCTR 2 Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial Micrel SY10E212 SY100E212 28 LEAD PLCC (J28-1) Rev. 03 3 Micrel SY10E212 SY100E212 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 4 |
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