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| AT28LV64B Features * * * * * * * * * * * Single 3.3V 10% Supply 3-Volt-Only Read and Write Operation Software-Protected Programming Low Power Dissipation 15 mA Active Current 20 A CMOS Standby Current Fast Read Access Time - 200 ns Automatic Page Write Operation Internal Address and Data Latches for 64-Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 10 ms Maximum 1 to 64-Byte Page Write Operation DATA Polling for End of Write Detection High Reliability CMOS Technology Endurance: 10,000 Cycles Data Retention: 10 Years JEDEC Approved Byte-Wide Pinout Commercial and Industrial Temperature Ranges Description The AT28LV64B is a high-performance electrically erasable programmable read only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 A. The AT28LV64B is accessed like a static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow (continued) 64K (8K x 8) Low Voltage CMOS E2PROM with Page Write and Software Data Protection Pin Configurations Pin Name A0 - A12 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable AT28LV64B PDIP, SOIC Top View Data Inputs/Outputs No Connect Don't Connect PLCC Top View TSOP Top View Note: PLCC package pins 1 and 17 are DON'T CONNECT. 0299C 2-135 Description (Continued) writing of up to 64-bytes simultaneously. During a write cycle, the addresses and 1 to 64-bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel's 28LV64B has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. A software data protection mechanism guards against inadvertent writes. The device also includes an extra 64-bytes of E2PROM for device identification or tracking. Block Diagram Absolute Maximum Ratings* Temperature Under Bias................. -55C to +125C Storage Temperature...................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ................... -0.6V to +6.25V All Output Voltages with Respect to Ground .............-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ................... -0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2-136 AT28LV64B AT28LV64B Device Operation READ: The AT28LV64B is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their systems. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. PAGE WRITE: T h e p a g e w r i t e o p e r a t i o n o f t h e AT28LV64B allows 1 to 64-bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 100 s (tBLC) of the previous byte. If the tBLC limit is exceeded, the AT28LV64B will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 to A12 inputs. For each WE high to low transition during the page write operation, A6 to A12 must be the same. The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28LV64B features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: I n a d d i t i o n t o DATA P o l l i n g , t he AT28LV64B provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28LV64B in the following ways: (a) VCC power-on delay- once VCC has reached 1.8V (typical) the device will automatically time out 10 ms (typical) before allowing a write; (b) write inhibitholding any one of OE low, CE high or WE high inhibits write cycles; (c) noise filterpulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software-controlled data protection feature has been implemented on the AT28LV64B. Software data protection (SDP) helps prevent inadvertent writes from corrupting the data in the device. SDP can prevent inadvertent writes during power-up and power-down as well as any other potential periods of system instability. The AT28LV64B can only be written using the software data protection feature. A series of three write commands to specific addresses with specific data must be presented to the device before writing in the byte or page mode. The same three write commands must begin each write operation. All software write commands must obey the page mode write timing specifications. The data in the 3-byte command sequence is not written to the device; the addresses in the command sequence can be utilized just like any other location in the device. Any attempt to write to the device without the 3-byte sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. DEVICE IDENTIFICATION: A n e x t r a 6 4 - b y t e s o f E2PROM memory are available to the user for device identification. By raising A9 to 12V 0.5V and using address locations 7FC0H to 7FFFH, the additional bytes may be written to or read from in the same manner as the regular memory array. 2-137 DC and AC Operating Range AT28LV64B-20 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 3.3V 10% AT28LV64B-25 0C - 70C -40C - 85C 3.3V 10% Operating Modes Mode Read Write (2) CE VIL VIL VIH X X X VIL OE VIL VIH X (1) WE VIH VIL X VIH X X (3) I/O DOUT DIN High Z Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable Chip Erase X VIL VIH VH 3. VH = 12.0V 0.5V. High Z High Z VIL Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. DC Characteristics Symbol ILI ILO ISB ICC VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA IOH = -100 A 2.0 2.0 0.45 Condition VIN = 0V to VCC + 1V VI/O = 0V to VCC CE = VCC - 0.3V to VCC + 1V f = 5 MHz; IOUT = 0 mA Com. Ind. Min Max 10 10 20 50 15 0.6 Units A A A A mA V V V V 2-138 AT28LV64B AT28LV64B AC Read Characteristics AT28LV64B-20 Symbol tACC tCE (1) tOE (2) tDF tOH (3, 4) AT28LV64B-25 Min Max Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first Min Max Units ns ns ns ns ns 200 200 0 0 0 80 55 0 0 0 250 250 100 60 AC Read Waveforms (1, 2, 3, 4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. Input Test Waveforms and Measurement Level Output Test Load tR, tF < 20 ns Pin Capacitance (f = 1 MHz, T = 25C) (1) Typ CIN COUT Note: Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 4 8 1. This parameter is characterized and is not 100% tested. 2-139 AC Write Characteristics Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tDV tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Time to Data Valid Write Pulse Width High Min 0 100 0 0 200 100 0 NR (1) Max Units ns ns ns ns ns ns ns ns 100 Notes: 1. NR = No Restriction. 2. All byte write operations must be preceded by the SDP command sequence. AC Write Waveforms WE Controlled CE Controlled 2-140 AT28LV64B AT28LV64B Page Mode Characteristics Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 100 0 100 100 0 200 100 Min Max 10 Units ms ns ns ns ns ns s ns Write Algorithm (1) LOAD DATA AA TO ADDRESS 1555 LOAD DATA 55 TO ADDRESS 0AAA LOAD DATA A0 TO ADDRESS 1555 LOAD DATA XX TO ANY ADDRESS (3) LOAD LAST BYTE TO LAST ADDRESS Notes for software program code: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A12 - A0 (Hex). 2. Data protect state will be re-activated at the end of the write cycle. 3. 1 to 64-bytes of data are loaded. WRITES ENABLED (2) ENTER DATA PROTECT STATE Software Data Protection Write Cycle Waveforms (1, 2, 3) Notes: 1. A0 - A12 must conform to the addressing sequence for the first three bytes as shown above. 2. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 3. OE must be high only when WE and CE are both low. 2-141 Data Polling Characteristics (1) Symbol tDH tOEH tOE tWR Parameter Data Hold Time OE Hold Time OE to Output Delay (2) Min 0 0 0 Typ Max Units ns ns ns ns Write Recovery Time Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. Data Polling Waveforms Toggle Bit Characteristics (1) Symbol tDH tOEH tOE tOEHP tWR Parameter Data Hold Time OE Hold Time OE to Output Delay (2) OE High Pulse Write Recovery Time 150 0 2. See AC Read Characteristics. Min 10 10 Typ Max Units ns ns ns ns ns Notes: 1. These parameters are characterized and not 100% tested. Toggle Bit Waveforms Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used, but the address should not vary. 2-142 AT28LV64B AT28LV64B Ordering Information (1) tACC (ns) 200 ICC (mA) Active 15 Standby 0.05 AT28LV64B-20JC AT28LV64B-20PC AT28LV64B-20SC AT28LV64B-20TC AT28LV64B-20JI AT28LV64B-20PI AT28LV64B-20SI AT28LV64B-20TI AT28LV64B-25JC AT28LV64B-25PC AT28LV64B-25SC AT28LV64B-25TC AT28LV64B-25JI AT28LV64B-25PI AT28LV64B-25SI AT28LV64B-25TI Ordering Code Package 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T Operation Range Commercial (0C to 70C) 15 0.05 Industrial (-40C to 85C) 250 15 0.05 Commercial (0C to 70C) 15 0.05 Industrial (-40C to 85C) Note: 1. See Valid Part Number table below. Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers AT28LV64B AT28LV64B Speed 20 25 Package and Temperature Combinations JC, JI, PC, PI, SC, SI, TC, TI JC, JI, PC, PI, SC, SI, TC, TI Package Type 32J 28P6 28S 28T 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28 Lead, Plastic Thin Small Outline Package (TSOP) 2-143 |
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