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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1-of-16 Decoder/Demultiplexer
High-Performance Silicon-Gate CMOS
The MC54/74HC154 is identical in pinout to the LS154. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device, when enabled, selects one of 16 active-low outputs. Two active-low Chip Selects are provided to facilitate the chip-select, demultiplexing, and cascading functions. When either Chip Select is high, all outputs are high. The demultiplexing function is accomplished by using the Address inputs to select the desired device output. Then, while holding one chip select input low, data can be applied to the other chip select input (see Application Note). The HC154 is primarily used for memory address decoding and data routing applications. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 192 FETs or 48 Equivalent Gates
MC54/74HC154
24 1
J SUFFIX CERAMIC PACKAGE CASE 758-02
24 1
N SUFFIX PLASTIC PACKAGE CASE 724-03
24 1
DW SUFFIX SOIC PACKAGE CASE 751E-04
ORDERING INFORMATION MC54HCXXXJ MC74HCXXXN MC74HCXXXDW Ceramic Plastic SOIC
LOGIC DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17
PIN ASSIGNMENT
Y0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y1 Y2 Y3 Y4 Y5 ACTIVE-LOW OUTPUTS Y6 Y7 Y8 Y9 Y10 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A0 A1 A2 A3 CS2 CS1 Y15 Y14 Y13 Y12 Y11
BINARY ADDRESS INPUTS
A0 A1 A2 A3
23 22 21 20
CHIP SELECT INPUTS
18 CS1 CS2 19
PIN 24 = VCC PIN 12 = GND
10/95
(c) Motorola, Inc. 1995
1
REV 6
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III I III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Vin = VCC or GND 6.0 8 80 160 A Iout = 0 A NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
RECOMMENDED OPERATING CONDITIONS
MC54/74HC154
Symbol
Vin, Vout
Symbol
Symbol
VCC
Vout
Tstg
ICC
Iout
VCC
Vin
PD
TL
VOH
tr, tf
Iin
VOL
ICC
TA
VIH
VIL
Iin
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP) (Ceramic DIP or SOIC Package)
Storage Temperature
Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time (Figure 2)
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
Parameter
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| 20 A
Vin = VCC or GND
Vin = VIH or VIL |Iout| |Iout|
Vin = VIH or VIL |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v
v
v
v
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Test Conditions
- 0.5 to VCC + 0.5
- 1.5 to VCC + 1.5
- 65 to + 150
- 0.5 to + 7.0
2 - 55 Min 2.0 Value
v 4.0 mA v 5.2 mA
v 4.0 mA v 5.2 mA
0 0 0
0
50
25
20
260 300
750 500
+ 125
1000 500 400
VCC
Max
6.0
VCC V
6.0
4.5 6.0
2.0 4.5 6.0
4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
- 55 to 25_C
0.1
1.5 3.15 4.2
0.26 0.26
3.98 5.48
0.1 0.1 0.1
1.9 4.4 5.9
0.3 0.9 1.2
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 1.0 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2
v
1.0 1.5 3.15 4.2 0.40 0.40 3.70 5.20 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2
v
Unit
A V V V V
MC54/74HC154
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit Symbol tPLH, tPHL tPLH, tPHL tTLH, tTHL Cin Parameter VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- - 55 to 25_C 190 38 32 175 35 30 75 15 13 10
v 85_C v 125_C
240 48 41 220 44 37 95 19 16 10 285 57 48 265 53 45 110 22 19 10
Unit ns
Maximum Propagation Delay, Input A to Output Y (Figures 1 and 3) Maximum Propagation Delay, CS to Output Y (Figures 2 and 3)
ns
Maximum Output Transition Time, Any Output (Figures 2 and 3) Maximum Input Capacitance
ns
pF
NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package)* 80
pF
* Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS A0, A1, A2, A3 (Pins 23, 22, 21, 20) Address inputs. These inputs, when the 1-of-16 decoder is enabled, determine which of its sixteen active-low outputs is selected. OUTPUTS Y0 - Y15 (Pins 1 - 11, 13 - 17) Active-low outputs. These outputs assume a low level when addressed and both chip-select inputs are active. These outputs remain high when not addressed or a chip- select input is high. CONTROL INPUTS CS1, CS2 (Pins 18, 19) Active-low chip-select inputs. With low levels on both of these inputs, the outputs of the decoder follow the Address inputs. A high level on either input forces all outputs high.
FUNCTION TABLE
Inputs CS1 L L L L L L L L L L L L L L L L L H H CS2 L L L L L L L L L L L L L L L L H L H A3 L L L L L L L L H H H H H H H H X X X A2 L L L L H H H H L L L L H H H H X X X A1 L L H H L L H H L L H H L L H H X X X A0 L H L H L H L H L H L H L H L H X X X Y0 L H H H H H H H H H H H H H H H H H H Y1 H L H H H H H H H H H H H H H H H H H Y2 H H L H H H H H H H H H H H H H H H H Y3 H H H L H H H H H H H H H H H H H H H Y4 H H H H L H H H H H H H H H H H H H H Y5 H H H H H L H H H H H H H H H H H H H Y6 H H H H H H L H H H H H H H H H H H H Outputs Y7 H H H H H H H L H H H H H H H H H H H Y8 H H H H H H H H L H H H H H H H H H H Y9 H H H H H H H H H L H H H H H H H H H Y10 H H H H H H H H H H L H H H H H H H H Y11 H H H H H H H H H H H L H H H H H H H Y12 H H H H H H H H H H H H L H H H H H H Y13 H H H H H H H H H H H H H L H H H H H Y14 H H H H H H H H H H H H H H L H H H H Y15 H H H H H H H H H H H H H H H L H H H
H = High Level, L = Low Level, X = Don't Care
High-Speed CMOS Logic Data DL129 -- Rev 6
3
MOTOROLA
MC54/74HC154
SWITCHING WAVEFORMS
VALID INPUT A tPLH OUTPUT Y 50% 50% GND tPHL OUTPUT Y VALID tf VCC 90% CS1 OR CS2 50% 10% tr VCC GND tPHL 90% 50% 10% tTHL tTLH tPLH
Figure 1.
Figure 2.
TEST POINT OUTPUT DEVICE UNDER TEST CL*
* Includes all probe and jig capacitance
Figure 3. Test Circuit
TYPICAL APPLICATIONS
A0 A1 A2 A3 Y0 A0 A1 A2 A3 Y0
Y15 STROBE CS1 CS2 1 OF 16 DECODER SELECTED OUTPUT IS LOW DATA INPUT CS1 CS2
Y15
1 OF 16 DEMULTIPLEXER SELECTED OUTPUT'S LOGIC LEVEL FOLLOWS LOGIC LEVEL ON DATA INPUT
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC154
EXPANDED LOGIC DIAGRAM
1 CS1 CS2 18 19 2
Y0
Y1
3 Y2
4
Y3
5 A0 23
Y4
6 Y5
7 A1 22
Y6
8 Y7
9 A2 21 10
Y8
Y9
11
Y10
13 A3 20
Y11
14 Y12
15
Y13
16 Y14
17
Y15
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC54/74HC154
OUTLINE DIMENSIONS
J SUFFIX CERAMIC PACKAGE CASE 758-02 ISSUE A
B
24 13 NOTES: 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH. 5. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. DIM A B C D F G J K L N P INCHES MIN MAX 1.240 1.285 0.285 0.305 0.160 0.200 0.015 0.021 0.045 0.062 0.100 BSC 0.008 0.013 0.100 0.165 0.300 0.310 0.020 0.050 0.360 0.400 MILLIMETERS MIN MAX 31.50 32.64 7.24 7.75 4.07 5.08 0.38 0.53 1.14 1.57 2.54 BSC 0.20 0.33 2.54 4.19 7.62 7.87 0.51 1.27 9.14 10.16
L
P
1
12
-A-
J
N C K G F D 24 PL 0.25 (0.010)
M
-T-
SEATING PLANE
TA
M
-A-
24 1 13
N SUFFIX PLASTIC PACKAGE CASE 724-03 ISSUE D
NOTES: 1. CHAMFERED CONTOUR OPTIONAL. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH.
-B-
12
C -T-
SEATING PLANE
L
K E G F D
24 PL
NOTE 1
N J 0.25 (0.010) TA
24 PL
M
0.25 (0.010)
M M
M
TB
M
DIM A B C D E F G J K L M N
INCHES MIN MAX 1.230 1.265 0.250 0.270 0.145 0.175 0.015 0.020 0.050 BSC 0.040 0.060 0.100 BSC 0.007 0.012 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040
MILLIMETERS MIN MAX 31.25 32.13 6.35 6.85 3.69 4.44 0.38 0.51 1.27 BSC 1.02 1.52 2.54 BSC 0.18 0.30 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC154
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E-04 ISSUE E
-A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
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High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
7
*MC54/74HC154/D*
MC54/74HC154/D MOTOROLA

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