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CXD2956AGL-1
GPS Baseband LSI
Description The CXD2956AGL-1 is a dedicated LSI for the GPS (Global Positioning System), satellite-based location measurement system. Compared with conventional methods, position detection time and sensitivity are substantially improved with the use of an advanced signal processing scheme. Although package sizes differ, the CXD2956AGL-1 has realized compatibility with a foot pattern to the CXD2963GH. This LSI used together with the Sony GPS RF down converter IC enables the configuration of a 2-chip system capable of measuring its position anywhere on the globe. The CXD2956AGL-1 is ideal for use in automotive, cellular handset, handheld navigation, mobile computing and other location-based applications. Features * 12-channel GPS receiver capable of simultaneously receiving 12 satellites * Reception frequency: 1575.42MHz (L1 band, CA code) * Reference clock (TCXO) frequency: 18.414MHz (GPS, Sony compatible), * 32-bit RISC CPU (ARM7TDMI) * 288K-byte Program ROM * 72K-byte Data RAM Power is supplied only to 8K-byte Data RAM while in backup mode. * System power management * 1-channel UART * Internal RTC (Real Time Clock) * 10-bit successive approximation system A/D converter * All-in-view positioning * Communication format: Supports NMEA-0183 * Supports DGPS (optional) Conforms to RTCM SC-104 Ver. 2.1 and DARC * 1 PPS output * Supports assisted-GPS for cellular (optional) Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
183 pin VFLGA (Plastic)
Absolute Maximum Ratings * Supply voltage I/O IOVDD * Supply voltage core CVDD * Input voltage VI * Output voltage VO * Operating temperature Topr * Storage temperature Tstg
-0.5 to +4.6 -0.5 to +2.5 -0.5 to +6 -0.5 to +6 -40 to +85 -50 to +150
V V V V C C
Recommended Operating Conditions * Supply voltage I/O IOVDD 3.0 to 3.6 Under operation with internal ROM, using no external expansion bus: IOVDD 2.6 to 3.6V Under operation in backup mode: BKUPIOVDD 2.5 (Min.) V * Supply voltage core CVDD 1.62 to 1.98 * Operating temperature Topr -40 to +85 Input/Output Pin Capacitance * Input capacitance CIN * Output capacitance COUT * I/O capacitance CI/O
V
V C
9 (Max.) 11 (Max.) 11 (Max.)
pF pF pF
-1-
E04729A5Z
CXD2956AGL-1
Performance * Tracking sensitivity: -152dBm (average) or less
* Acquisition sensitivity: -139dBm (average) or less in normal mode -150dBm (average) or less in high sensitivity mode Reference data using the Sony's reference board when using both an antenna of 25dBi gain and a RF amplifier with NF 2dB, 25dB gain. * TTFF (Time to First Fix): Time until initial position measurement after power-on with the following conditions: Cold Start (without both ephemeris and almanac time): 50s (average) / 60s (95% possibility) Warm Start (without ephemeris but with almanac time): 35s (average) / 40s (95% possibility) Hot Start (with both ephemeris and almanac time): 2s (minimum) / 6s (95% possibility) Reference data with elevation angle of 5 or more and no interception environment with satellite powers -130dBm. (Not in high sensitivity mode) Note) "95% possibility" means "position time with 95% possibility". * Positioning accuracy: 2DRMS: approx. 5m Reference data with elevation angle of 5 or more and no interception environment with satellite powers -130dBm. * Measurement data update time: 1s * Current consumption: 40mW (average) while position calculating with tracking satellites in low power mode 90mW (average) while position calculating with acquiring and tracking satellites Reference data using the Sony's reference board when the reference clock input is 18.414MHz, and its amplitude is 3.3V swing. * 1PPS output 1s or less precision, 1PPS outputs from ECLKOUT (Pin 97). Note) These values are not guaranteed, depending on the conditions.
-2-
CXD2956AGL-1
Block Diagram
IF 1.023MHz
Acquisition Block TCXO Reference clock 18.414MHz (GPS, Sony compatible) * Acquire GPS signals
Tracking Block * Locking to GPS signals * 12ch correlations
Costas Loop & DLL
ARM7TDMI
External bus UART A/D RAM 72KB ROM 288KB
Computation & Control * Control acquisition & Tracking block * Position calculation RTC Timer 3ch
X'tal 32.768kHz
-3-
CXD2956AGL-1
Pin Configuration (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
40 A
NC
42
NC NC
34
NC
31
NC
32
NC
26
TCK
22
TDO
18
CVSS1
14
IOVSS1
12
9
6
3
1 A 173
ERXD0
EPORT11 EPORT8
EPORT5 EPORT2 EPORT0
46 B 48 C
NC NC
44
NC
43
NC
35
NC
33
NC
30
NC
28
TMS
24
TDI
20
TRST
16
11
8
5
EPORT4
2
EPORT1
176
IOVDD6
ETCXO EPORT10 EPORT7
B
47
NC
45
NC
41
NC
39
NC
37
NC
36
NC
27
23
21
17
13
10
7
4
NC
175
IOVSS7
ETESTTCK ETESTTDO ETESTTINT EXTCXO EPORT12 EPORT9
EPORT6 EPORT3
C
50 D
NC
49
NC
55
NC
38
NC
29
25
19
CVDD1
15
IOVDD1 NC
172
CVDD6
171
CVSS6
ETESTTMS ETESTTDI
D
56 E
NC
52
NC
51
NC
174
ETXD0
169
ED1
167
ED3
E
58 F
NC
54
NC
53
NC
170
ED0
165
ED5
163
ED7
F
G
57
NC
59
NC
60
NC
61
NC
168
ED2
166
ED4
161
ED9
159
ED11
G
H
62
CVSS2
64
65
66
164
ED6
162
ED8
157
ED13
155
ED15
ETEST0 ETEST1 ETEST2
H
J
63
CVDD2
68
EA18
67
EA19
69
EA17
160
ED10
158
ED12
154
IOVDD5
153
IOVSS6
J
K
70
EA16
72
EA14
71
EA15
73
EA13
156
ED14
148
152
151
ED16 ETESTXRS EXRS
K
L
75
IOVSS2
74
EA12
77
EA11 NC
146
ED18
144
ED20
150
CVDD5 NC
L
M
76
IOVDD2
79
EA9 NC
142
ED22
147
ED17
149
CVSS5
M
N
81
CVSS3
83
EA7
78
EA10
140
ED24
143
ED21
145
ED19
N
P
82
CVDD3
85
EA5
80
EA8
105
EVIN2
108
110
112
IOVDD7
122
ECLKS2
138
ED26
139
ED25
141
ED23
P
EAVDAD ETEST3
R
88
EA2
87
EA3
90
EA0
94
ECLKO
98
102
103
EVIN0
106
EVIN3
111
ETEST4 NC
121
120
126
EXOE
128
EXWE2
136
ED28
135
ED29
137
ED27
R
EXROMI EADVRB
ECLKS1 ECLKS0
T
86
EA4
84
EA6
92
CVDD4
93
97
100
104
EVIN1
109
114
116
118
125
124
EXCS0
130
EXWE0
134
ED30
132
IOVDD4
133
ED31
T
ECLKI ECLKOUT EAVDPLL
IOVSS8 BKUPCVDD ECCKO BKUPIOVDD EXCS1
U
89
EA1
91
CVSS4
95
IOVSS3
96
99
101
107
113
115
117
119
123
127
EXWE3
129
EXWE1
131
IOVSS5
U
IOVDD3 EAVSPLL EAVSAD EADVRT BKUPCVSS ECCKI BKUPIOVSS EOSCEN IOVSS4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 : Pin 1 index.
-4-
CXD2956AGL-1
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol EPORT0 EPORT1 EPORT2 EPORT3 EPORT4 EPORT5 EPORT6 EPORT7 EPORT8 EPORT9 EPORT10 EPORT11 EPORT12 IOVSS1 IOVDD1 ETCXO EXTCXO CVSS1 CVDD1 TRST ETESTTINT TDO ETESTTDO TDI ETESTTDI TCK ETESTTCK TMS I O O O I I I I I I O I/O I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Description I/O port 0 (with a software controllable pull-down resistor, Pull-up.) I/O port 1 (with a software controllable pull-down resistor, See software application note.) I/O port 2 (with a software controllable pull-down resistor, See software application note.) I/O port 3 (with a software controllable pull-down resistor, See software application note.) I/O port 4 (with a software controllable pull-down resistor, IF signal input.) I/O port 5 (with a software controllable pull-down resistor, See software application note.) I/O port 6 (with a software controllable pull-down resistor, See software application note.) I/O port 7 (with a software controllable pull-down resistor, See software application note.) I/O port 8 (with a software controllable pull-down resistor, See software application note.) I/O port 9 (with a software controllable pull-down resistor, See software application note.) I/O port 10 (with a software controllable pull-down resistor, See software application note.) I/O port 11 (with a software controllable pull-down resistor, See software application note.) I/O port 12 (with a software controllable pull-down resistor, See software application note.) GND 3.3V TCXO oscillator (Frequency selectable, See software application note.) GND 1.8V Test (Open, with a pull-down resistor) Test Test Test Test (Open, with a pull-up resistor) Test (Open, with a pull-up resistor) Test (Open, with a pull-down resistor) Test (Open, with a pull-down resistor) Test (Open, with a pull-up resistor) -5-
CXD2956AGL-1
Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Symbol ETESTTMS NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC CVSS2 CVDD2
I/O I
Description Test (Open, with a pull-up resistor)
GND 1.8V
-6-
CXD2956AGL-1
Pin No. 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol ETEST0 ETSET1 ETEST2 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 IOVSS2 IOVDD2 EA11 EA10 EA9 EA8 CVSS3 CVDD3 EA7 EA6 EA5 EA4 EA3 EA2 EA1 EA0 CVSS4 CVDD4 ECLKI ECLKO IOVSS3 IOVDD3 ECLKOUT EXROMI EAVSPLL EAVDPLL
I/O I I I O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z External expansion address 19 External expansion address 18 External expansion address 17 External expansion address 16 External expansion address 15 External expansion address 14 External expansion address 13 External expansion address 12 GND 3.3V O/Z O/Z O/Z O/Z External expansion address 11 External expansion address 10 External expansion address 9 External expansion address 8 GND 1.8V O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z External expansion address 7 External expansion address 6 External expansion address 5 External expansion address 4 External expansion address 3 External expansion address 2 External expansion address 1 External expansion address 0 GND 1.8V I O CPU clock oscillator GND 3.3V O/Z I Test (Connect to GND.)
Description
1PPS output (Effective 1s late after reset release) Boot selection (Low: Internal ROM, High: External Memory/EXCS0) PLL GND PLL 3.3V -7-
CXD2956AGL-1
Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138
Symbol EAVSAD EADVRB EVIN0 EVIN1 EVIN2 EVIN3 EADVRT EAVDAD IOVSS8 ETEST3 ETEST4 IOVDD7 BKUPCVSS BKUPCVDD ECCKI ECCKO BKUPIOVSS BKUPIOVDD EOSCEN ECLKS0 ECLKS1 ECLKS2 IOVSS4 EXCS0 EXCS1 EXOE EXWE3 EXWE2 EXWE1 EXWE0 IOVSS5 IOVDD4 ED31 ED30 ED29 ED28 ED27 ED26
I/O A/D converter GND I I I I I I
Description
A/D converter Reference input Bottom A/D converter Analog input 0 A/D converter Analog input 1 A/D converter Analog input 2 A/D converter Analog input 3 A/D converter Reference input Top A/D converter 3.3V GND
I/O/Z I/O/Z
Test (Connect to GND with a resistor.) Test (Connect to GND with a resistor.) 3.3V Backup core power supply GND Backup core power supply 1.8V
I O
RTC oscillator (32.768kHz, includes feedback resistor.) Backup I/O power supply GND Backup I/O power supply 3.3V
I I I I O/Z O/Z O/Z O/Z O/Z O/Z O/Z
Oscillator enable (H-Active), See backup mode section. Test (Connect to GND.) Test (Connect to GND.) Test (Connect to GND.) GND External expansion chip selection 0 (Program boot is enable if EXROMI is high.) External expansion chip selection 1 External expansion read signal External expansion write signal External expansion write signal External expansion write signal External expansion write signal GND 3.3V
I/O I/O I/O I/O I/O I/O
External expansion data 31 (with a pull-down resistor) External expansion data 30 (with a pull-down resistor) External expansion data 29 (with a pull-down resistor) External expansion data 28 (with a pull-down resistor) External expansion data 27 (with a pull-down resistor) External expansion data 26 (with a pull-down resistor) -8-
CXD2956AGL-1
Pin No. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
Symbol ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 CVSS5 CVDD5 EXRS ETESTXRS IOVSS6 IOVDD5 ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 CVSS6 CVDD6 ERXD0 ETXD0 IOVSS7 IOVDD6
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Description External expansion data 25 (with a pull-down resistor) External expansion data 24 (with a pull-down resistor) External expansion data 23 (with a pull-down resistor) External expansion data 22 (with a pull-down resistor) External expansion data 21 (with a pull-down resistor) External expansion data 20 (with a pull-down resistor) External expansion data 19 (with a pull-down resistor) External expansion data 18 (with a pull-down resistor) External expansion data 17 (with a pull-down resistor) External expansion data 16 (with a pull-down resistor) GND 1.8V
I I
Reset (L-Active) Test (Open, with a pull-up resistor) GND 3.3V
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
External expansion data 15 (with a pull-down resistor) External expansion data 14 (with a pull-down resistor) External expansion data 13 (with a pull-down resistor) External expansion data 12 (with a pull-down resistor) External expansion data 11 (with a pull-down resistor) External expansion data 10 (with a pull-down resistor) External expansion data 9 (with a pull-down resistor) External expansion data 8 (with a pull-down resistor) External expansion data 7 (with a pull-down resistor) External expansion data 6 (with a pull-down resistor) External expansion data 5 (with a pull-down resistor) External expansion data 4 (with a pull-down resistor) External expansion data 3 (with a pull-down resistor) External expansion data 2 (with a pull-down resistor) External expansion data 1 (with a pull-down resistor) External expansion data 0 (with a pull-down resistor) GND 1.8V
I O/Z
UART (CH0) reception data (with a pull-down resistor during reset interval) UART (CH0) transmission data (with Hi-Z during reset interval) GND 3.3V -9-
CXD2956AGL-1
A/D Converter Operating Conditions Item Supply voltage Operating temperature Symbol VAD Ta Pin name EAVDAD1 -- Min. 3.0 -40.0 Typ. 3.3 Max. 3.6 +85.0 Unit V C
A/D Converter Characteristics Item Resolution Channel Differential linearity error (DLE) Integral linearity error (ILE) Sampling time Conversion time Reference input voltage (Top) Reference input voltage (Bottom) Analog input voltage Current consumption Applicable pins 1 EAVDAD (Pin 108) 2 EADVRT (Pin 107) 3 EADVRB (Pin 102) 4 EVIN[0:3] (Pins 103 to 106) VRT2 VRB3 VIN4 VAD = 3.0V Symbol Conditions
(VAD = 3.0 to 3.6V, Ta = -40 to +85C) Min. Typ. Max. 10 4 VAD = 3.0V, VRT = 3.0V, VRB = 0.3V TCXO = 18.414MHz -1.0 -2.0 3 11 2.0 0 VRB 1.6 VAD 0.7 VRT +1.0 +2.0 Unit Bit Ch LSB LSB s s V V V mA
- 10 -
CXD2956AGL-1
DC Characteristics Item Input voltage1 Output voltage2 Output voltage3 Pull-up resistor4 Pull-down resistor5 Current consumption during normal operation (via IOVDD and CVDD)6 High level Low level High level Low level High level Low level
(IOVDD = 3.0 to 3.6V, CVDD = 1.62 to 1.98V, Ta = -40 to +85C) Symbol VIH VIL VOH1 VOL1 VOH2 VOL2 RU RD IOPE TCXO = 18.414MHz, Ta = 25C BKUPIOVDD = 3.6V, Ta = 25C BKUPIOVDD = 3.6V, Ta = 85C BKUPCVDD = 1.98V, Ta = 25C BKUPCVDD = 1.98V, Ta = 85C IOH = 4mA IOL = 4mA IOH = 8mA IOL = 8mA 56 51 45 0.2 0.2 7.5 50 1.0 1.0 15 120 2.4 0.4 110 100 2.4 0.4 Conditions Min. 0.7IOVDD Typ. Max. 5.5 0.2IOVDD Unit V V V V V V k k mA A A A A
Current consumption during backup ISTB1 operation (via BKUPIOVDD)7 Current consumption during backup ISTB2 operation (via BKUPCVDD)8
Applicable pins 1 Pins 1 to 13, 20, 24 to 29, 64 to 66, 98, 119, 120 to 122, 133 to 148, 151, 152, 155 to 170, 173 2 Pins 1 to 13, 21 to 23, 97, 174 3 Pins 67 to 74, 77 to 80, 83 to 90, 124 to 130, 133 to 148, 155 to 170 4 Pins 24, 25, 28, 29, 152 5 Pins 1 to 13, 20, 26, 27, 133 to 148, 155 to 170, 173 6 Pins 15, 76, 96, 132, 154, 176 (3.3V) Pins 19, 63, 82, 92, 150, 172 (1.8V) 7 Pin 118 8 Pin 114
- 11 -
CXD2956AGL-1
AC Characteristics * External RAM I/F (Read/32-bit mode) (CVDD = 1.62 to 1.98V, IOVDD = 3.0 to 3.6V, CL = 25pF, Topr = -40 to +85C) Item EXOE to address valid EXOE to EXCS Data setup Data hold Symbol Toea Toecs Tas Tah Min. Max. 3 1 15 0 Unit ns ns ns ns
EXOE Toea EA[19:0] Toecs
EXCS[1:0] Tas ED[31:0] Tah
- 12 -
CXD2956AGL-1
* External RAM I/F (Write/32-bit mode (1-wait)) (CVDD = 1.62 to 1.98V, IOVDD = 3.0 to 3.6V, CL = 25pF, Topr = -40 to +85C) Item EXCS to address valid EXCS to EXWE EXCS to EXWE EXCS to data valid Tsys: ARM clock cycle Symbol Tcsfav Tcswef Tcswer Tcsd Min. Max. 2 Tsys - 1 Tsys x 3 - 2 15 Unit ns ns ns ns
T1
T2
T3
EXCS[1:0] Tcsfav
EA[19:0] Tcswer Tcswef EXWE[3:0] Tcsd
ED[31:0]
- 13 -
CXD2956AGL-1
Backup Mode The backup mode is established by setting both EOSCEN and EXRS low. In this mode, the low power consumption can be achieved by stopping all oscillators except for RTC oscillator during the reset interval. Although all registers are initialized, the SRAM contents in backup area are held. In order to cancel this mode (reset cancellation), please set EOSCEN high at first and then set EXRS high after the oscillation stabilization time and PLL lock time have passed. It needs 100ms or more. See Initialization section.
Normal operation
Backup
Reset
Normal operation
IOVDD CVDD
BKUPIOVDD BKUPCVDD
OSC, PLL output EOSCEN EXRS Oscillation stabilization time PLL lock time (0.5ms max.)
ED[31:0], EPORT[12:0], ERXD0 ETXD0 EXCS[1:0], EXWE[3:0], EXOE EA[19:0], ECLKOUT
Power Off Power Off Power Off Power Off
Pull-down output Hi-Z output High output Low output
- 14 -
CXD2956AGL-1
Initialization The CXD2956AGL-1 is initialized by setting the reset signal EXRS (Pin 151) to the low level. Note that internal RAM is not initialized by the operation. Satisfy the conditions shown below for the timing and others. 1. When turning the power on (Power-on reset)
VDD Power supply, EOSCEN (Pin 119) VDD [V] 100ms or more VDD/2 EXRS (Pin 151)
GND
Since there is a possibility that overcurrent may flow, please be sure to add power supply to the LSI before activate functional pin of this LSI. Additionally, the power supply both 3.3V and 1.8V should turn on simultaneously, and EOSCEN (Pin 119) should also rise simultaneously with the power supply turning on. EXRS (Pin 151) should rise 100ms or more after the power supply and EOSCEN rise. 2. Initialization during operation
VDD EXRS (Pin 151) VDD [V] 100s or more VDD/2 Power supply, EOSCEN (Pin 119)
GND
For initialization during operation, the interior circuit except internal RAM is initialized by setting the EXRS (Pin 151) signal to the low level for 100s or more. Note that internal RAM is not also initialized by the operation. At this time, the EOSCEN (Pin 119) signal should keep the high level.
- 15 -
CXD2956AGL-1
RTC Crystal and TCXO In order to operate CXD2956AGL-1 appropriately, the recommended characteristics of RTC crystal and TCXO is shown below. Recommended characteristics of RTC crystal Operating temperature Nominal frequency Frequency tolerance Frequency temperature coefficient Frequency peak temperature Frequency aging -40 to +85C 32.768kHz 20ppm -0.04ppm/C2 (Max.) +25 5C 3ppm/year
Recommended characteristics of TCXO Operating temperature Frequency tolerance Frequency vs. temperature Frequency vs. supply voltage Frequency vs. load Frequency aging Recommended parts RTC crystal TCXO EPSON FC-255 NDK SNA3088B (NT5032 Series) -40 to +85C 2.0ppm 2.5ppm 0.2ppm 0.2ppm 1ppm/year
- 16 -
Application Circuit
L046 56nH
10P
CNO 12
TXD0
1
R001 22
R004 100k
R005 100k
RXD0 1 XRESET BKUPIOVDD_3.3V IC006 R1160N181B 1 IC005 R1124N181D L045 1H C059 0.1 C048 2.2 CE 3 VDD 4 C066 10 C162 10 BKUPCVDD_1.8V R013 470k C046 0.1 C121 0.1 1 VDD IC004 2 GND R3112Q291A CD 3 C045 0.1 OUT 4 1 VOUT 5 NC 2 GND 2 GND ECO 4 3 CE VDD VOUT 5 2 GND 3 Reset In Vcc 4 IC003 MAX6364 OUT 5 BATT 6
2
R002 22
RXD1
3
R063 22
JS040 0
L003 10H
R202 XX
NMEA/Orig
4
UPDATE
5
R062 22
IC002 XX
RESET/POWER DOWN
6
R205 47k
DGND
7
L002 22H
1 VOUT 5 NC 2 GND
VDD (3.3V/5V)
8
BATT
9
C004 22
3 VDD
4
C161 10
C013 10
CE
AGND
10
JS041 0
Note) If a Flash ROM is used, the programs which are GPS software, Flash updater etc, required for desired operation should be written into a Flash ROM in advance.
R1124N331D
JS025 0
SYSTEM_RESET
C069 0.1
C072 0.1
C077 0.1
C079 0.1
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
ED8
ED9
ED10
ED11
ED12
ED13
ED14
ED15
ED16
ED17
ED18
ED19
ED20
ED21
ED22
ED23
ED24
ED25
ED26
ED27
ED28
ED29
ED30 133 ED31
B16 C17 E15 B17 D16 D17 F15 E16 G14 E17 G15 F16 H14 F17 H15 G16 J14 G17 J15 H16 K14 H17 J16 J17 K16 K17 L16 M17 K15 M16 L14 N17 L15 N16 M15 P17 N15 P16 P15 R17 R15 R16 T15 T17
IOVDD6
ETXD0
ERXD0
CVDD6
ETESTXRS
EXRS
CVSS6
CVDD5
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
ED8
ED9
ED10
ED11
ED12
ED13
ED14
ED15
IOVDD5
CVSS5
ED16
ED17
ED18
ED19
ED20
ED21
ED22
ED23
ED24
ED25
ED26
ED27
ED28
ED29
IOVSS7
175
174
173
172
167
166
158
157
IOVSS6
145
144
176
169
168
164
161
160
159
146
141
140
137
136
171
170
165
163
162
156
155
154
153
152
151
150
149
148
147
143
142
139
138
135
134
ED30
ED31
R209 4700 A16 1 EPORT0 EPORT1 EPORT2 EPORT3 EPORT4 EPORT5 EPORT6 EPORT7 EPORT8 123 IOVSS4 ECLKS2 ECLKS1 ECLKS0 EOSCEN BKUPIOVDD T11 BKUPIOVSS U11 ECCKO ECCKI BKUPCVDD T9 BKUPCVSS U9 IOVDD7 ETEST4 ETEST3 IOVSS8 EAVDAD 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 EADVRT EVIN3 EVIN2 EVIN1 EVIN0 EADVRB EAVSAD EAVDPLL EAVSPLL EXROMI ECLKOUT IOVDD3 IOVSS3 ECLKO ECLKI CVDD4 CVSS4 EA0 EA1 P10 R9 P9 T8 P8 108 U8 R8 P7 T7 R7 R6 U7 T6 U6 R5 T5 U5 U4 R4 T4 T3 U3 R3 U2 C094 0.1 CVDD_1.8V R201 XX C093 0.1 ED9 C092 0.1 R028 XX ED22 ED23 C125 0.1 ED24 C090 0.1 U10 T10 R203 22 X002 C086 12p U12 R12 R029 100k C089 0.1 C085 12p R11 P11 R208 100k R052 XX 122 121 120 119 118 117 116 115 114 113 112 111 110 109 U13 124 EXCS0 T13 125 EXCS1 T12 126 EXOE R13 127 EXWE3 U14 128 EXWE2 R14 129 EXWE1 U15 130 EXWE0 T14 131 IOVSS5 U16 B15 2 A15 3 C15 4 B14 5 A14 6 C14 7 B13 8 A13 9 R204 22 C13 10 EPORT9 B12 11 EPORT10 A12 12 EPORT11 C067 0.1 A11 14 IOVSS1 D11 15 IOVDD1 R020 1M C11 17 EXTCXO A10 18 CVSS1 D10 19 CVDD1 B10 20 TRST C10 21 ETESTTINT A9 22 TDO C9 23 ETESTTDO B9 24 TDI D9 25 ETESTTDI A8 26 TCK C8 27 ETESTTCK B8 28 TMS D8 29 ETESTTMS B7 30 NC A6 31 NC A7 32 NC B6 33 NC A5 34 NC B5 35 NC C7 36 NC C6 37 NC D7 38 NC C5 39 NC A2 40 NC C4 41 NC A3 42 NC B4 43 NC B3 44 NC C068 0.1 B11 16 ETCXO C12 13 EPORT12 132 IOVDD4 T16
C088 0.1
IF_Input
ED7
ED8
ED6
ED5 EA13 EA10 A8 NC NC NC Vcc Vss A11 DQ7 DQ8 A12 DQ6 Vss NC DQ5 DQ26 DQ25 DQ21 DQ27 DQ11 DQ10
R057 100k R056 100k
ED26
ED25
ED21
ED27
ED11
IC020 CXD2956AGL-1
H4 H3 H2 H1 G9 G8 G7 G6 G5 G4 G3 G2 G1 F9 F8 F7 F6 F5 F4 F3 F2
EA14
ED10
DQ4
ED4
A4
A1
NC
XWE
NC
XCE
Vcc
A5
A2
ACC
NC
DW/XW
Vss
DQ30
DQ17
DQ1
DQ0
A3
XWP
NC
45 NC
46 NC
47 NC
48 NC
49 NC
50 NC
51 NC
52 NC
53 NC
54 NC
55 NC
56 NC
57 NC
58 NC
59 NC
60 NC
61 NC
62 CVSS2
63 CVDD2
64 ETEST0
65 ETSET1
66 ETEST2
67 EA19
68 EA18
69 EA17
70 EA16
71 EA15
72 EA14
73 EA13
74 EA12
75 IOVSS2
76 IOVDD2
77 EA11
78 EA10
79 EA9
80 EA8
81 CVSS3
82 CVDD3
83 EA7
84 EA6
85 EA5
86 EA4
87 EA3
88 EA2
C3 B2 C2 C1 D2 D1 E3 E2 F3 F2 D3 E1 G1 F1 G2 G3 G4 H1 J1 H2 H3 H4 J3 J2 J4 K1 K3 K2 K4 L2 L1 M1 L3 N3 M2 P3 N1 P1 N2 T2 P2 T1 R2 R1
A3 A4 A5 A6 A7 A8 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7
EA6
EA3
EA7
EA4
EA19
EA18
EA17
EA16
EA15
EA14
EA13
EA12
EA11
EA10
EA9
EA8
EA7
EA6
EA5
EA4
EA3
EA2
ED30
ED17
DE1
C076 0.1
C082 0.1
C083 0.1
C129 0.1
CXD2956AGL-1
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
ED0
EA5
XOE
- 17 -
L024 1H R025 100k
C060 0.01
C124 0.1
X001
H5 NC EA17 H6 A15 H7 A18 H8 DQ24 H9 Vcc J1 DQ22 J2 DQ23 EA8 EA11 J3 A6 J4 A9 J5 NC C126 0.1 EA16 EA19 J6 A14 J7 A17 J8 Vcc J9 DQ9 K2 Vss EA9 EA12 K3 A7 K4 A10 K5 NC EA15 EA18 K6 A13 K7 A16 K8 A19
DQ20 F1 DQ12 E9 DQ28 E8 Vss E7 NC E6 NC E5 DQ2 E4 DQ18 E3 DQ19 E2 DQ3 E1
ED20 ED12 ED28
L051 56nH
C122 0.1
ED2 ED18 ED19 ED3
IC021 MBM29PL3200
DQ13 D9 DQ29 D8 DQ14 D7 DQ31/A-1 D6 NC D5 A0 D4 DQ16 D3 Vss D2 Vcc D1 Vcc C9 DQ15 C8 EA2
ED13 ED29 ED14 ED31
ED16
C127 0.1
ED15 C128 0.1
CXD2956AGL-1
Package Outline
Unit: mm
183PIN VFLGA (PLASTIC)
0.1 S A 10.0 X
S
1.0MAX 0.1MAX
10.0
B
0.1
x4 0.08 DETAIL X
3-
0.8
0.5 A
U T R P N M L K J H G F E D C B A
183-0.27 0.04 0.05 M S AB
B
(0.5)
0.8
C0
.3
1 2 3 4 5 6 7 8 9 101112 13 14151617
0.8 (0.5) 1.0
1.0
0.5
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VFLGA-183P-051 P-VFLGA183-10X10-0.5
ORGANIC SUBSTRATE
TERMINAL TREATMENT NICKEL & GOLD PLATING TERMINAL MATERIAL PACKAGE MASS COPPER 0.3g
S
- 18 -
0.08
S
S
PIN 1 INDEX
0.2
Sony Corporation

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