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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
Features
* 16x16 Synchronous Serial Crosspoint Switch * Serial Data Rates: 2.0Gb/s * 32Gb/s Aggregate Data Bandwidth * Parallel Switches Can Increase Data Bandwidth in Multiples of 32Gb/s * Designed in Conjunction with the VSC870 Backplane Transceiver * Automatic Word and Cell Synchronization to the Transceiver * Two Modes of Operation: Distributed Control Self-routing Packet Mode and Central Control Cell Mode * Multicast Supported in All Modes
High Performance 16x16 Serial Crosspoint Switch
* Supports Variable Length Packets in Packet Mode * Built-in Flow Control Channel in Packet Mode * Supports Cell Synchronization in Cell Mode * Parallel CPU Interface and Parallel Switch Configuration Interface * Loopback, Built-in Self Test and Scan Functions * 5V Tolerant TTL Inputs * Dual 3.3V/2.5V or Dual 3.3V/2.0V Power Supplies * Serial Port Quadrants Can be Powered Down * Available in 304 BGA Package
VSC880 Block Diagram
Serial Port (16x)
TXS+/TXS-
Switch Matrix Parallel to Serial
VSCTE VSCIPNC VSCOPNC MEN FACLPBK CMODE TESTEN SCANIN SCANOUT
Port Logic
RXS+/RXS-
DRU
Serial to Parallel
WCLK REFCLK TCLKEN LOCKDET CCLK RESET BSTLPBK BSTEN BSTRST BSTPASS
Arbitration Logic and Switch Control Registers
CEN DATA[15:0] FI[3:0] WEN
CMU
Clock Gen
ADDR[5:0]
Status and Control Registers
CDATA[7:0] CWEN CSEL INT RESYNEN
BIST Logic
G52191-0, Rev 4.2 01/05/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
High Performance 16x16 Serial Crosspoint Switch
Data Sheet
VSC880
General Description
The VSC880 is a 16x16 serial crosspoint switch with serial data rates at 2.125Gb/s. The VSC880 has been designed to operate with the VSC870 backplane transceiver to establish a synchronous high performance switching system with an aggregate bandwidth of 32Gb/s. The switch chip transmits the master word clock (62.5Mb/s), and master cell clock (if used) to all port cards through the serial data channels. The transceivers automatically perform bit alignment, word alignment and cell alignment to the switch chip. The transceiver and switch chip have been optimized for both self-routing and cell-based systems and include special commands for connection requests (selfrouting) and cell synchronous operation (cell based). In addition, a parallel CPU interface can be used to control internal modes and read status information from the switch. A 20-bit interface can also be used to program the switch matrix in 4 clock cycles. The switch chip runs off of a 3.3V/2.5V or 3.3V/2.0V power supplies. The serial I/O buffers contain on-chip termination resistors (see Application Note 34).
Pin Descriptions
Pin
TXS[15:0]+/ TXS[15:0]RXS[15:0]+/ RXS[15:0]DATA[15:0] FI[3:0]
Name
Transmit Serial Outputs Receive Serial Inputs Configuration Data Input Force IDLE Input
I/O
O I I I
Freq Type
2.125Gb/s LVDS 2.125Gb/s LVDS 62.5Mb/s TTL 62.5Mb/s TTL 62.5Mb/s TTL 62.5Mb/s TTL 62.5Mb/s TTL 62.5Mb/s TTL
Description
16 high speed serial differential transmit channels 16 high speed serial differential receive channels Parallel input signals used to program the switch matrix in 4 clock cycles when the signal CEN is LOW. Parallel input signals used to program force IDLE words at the switch matrix output in 4 clock cycles when the signal CEN is LOW. When CEN is held LOW, the inputs DATA[15:0] and FI[3:0] can be used to program the switch matrix in 4 word clock cycles timed to the WEN signal. If CEN is LOW, this signal provides a synchronization pulse for loading switch configuration data into DATA[15:0] and FI[3:0]. The address to read and write data through parallel interface CDATA[7:0]. This signal allows several switch chips to share an 8 bit data bus connected to CDATA[7:0]. If CSEL is LOW, data will be read or written to CDATA[7:0]. If CSEL is HIGH, the outputs will be high impedance and the inputs disabled. Bidirectional CPU interface for the status and control registers. If CSEL is LOW, the data will be read or written into this port. If CSEL is HIGH, the outputs will be high impedance and the inputs will be disabled. This signal is set HIGH to read the internal status registers through the parallel interface CDATA[7:0]. It is set LOW to write into this interface.
CEN
Configure Enable
I
WEN ADDR[5:0]
Write Enable Data Address
I I
CSEL
Chip Select
I
CDATA[7:0]
Status Data Output
B
62.5Mb/s TTL 62.5Mb/s TTL
CWEN
Control Write Enable
I
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(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52191-0, Rev 4.2 01/05/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
Pin Name I/O Freq Type
<1MHz TTL <1MHz TTL <1MHz TTL <1MHz TTL <1MHz TTL <1MHz TTL 62.5Mb/s TTL 62.5Mb/s TTL 62.5MHz TTL 62.5MHz TTL <1MHz TTL 62.5MHz TTL <1MHz TTL <1MHz TTL <1MHz TTL <1MHz TTL <1MHz TTL
High Performance 16x16 Serial Crosspoint Switch
Description
If RESYNEN is HIGH, all links that have a link error condition will be reinitialized. This will override the internal control register settings. If INT is LOW, a receive error has occurred in one of the links that has it's output enable (OE) bit set HIGH and interrupt control register bit set HIGH. This signal is reserved for future use and should be set LOW during normal operation. If this signal is set HIGH, all serial inputs are looped back to their serial outputs. This will override the internal control register setting. CMODE is set HIGH for Cell Mode operation. This signal is used in ATE testing to measure propagation delay. It is also used in ATE testing of the BIST logic. Set to logic LOW in normal operation. The input signal for measuring propagation delay on the ATE tester. The output signal for measuring propagation delay on the ATE tester. When TESTEN is set LOW, the longer delay path is enabled. This is the word clock output. This is the reference clock and the source of the system wide word clock period. This input is set HIGH in test mode, so that the CMU is bypassed and the REFCLK becomes the bit clock. This signal is for ATE test only. Set LOW in normal operation. This is the source of the system wide cell clock. It is internally synchronized to the REFCLK. In Packet mode, set this signal HIGH to enable external switch configuration for BIST. Global chip reset (active LOW) When BSTLPBK is set HIGH and TESTEN is LOW, all serial data output signals are looped back to their serial data inputs. If BSTLPBK is set HIGH and TESTEN is HIGH, only ports 0-7 are placed in loopback. When BSTEN is HIGH, at-speed built-in self testing is enabled. The BSTRST signal is set HIGH to reset the PRBS generator and comparator. The BSTPASS signal is HIGH if BTSEN is HIGH and the PRBS comparator detects the correct pattern in built-in self test mode.
RESYNEN
Resynch Enable
I
INT MEN FACLPBK CMODE
Interrupt Reserved Facility Loop Back Cell Mode
O I I I
TESTEN SCANIN SCANOUT WCLK REFCLK TCLKEN
Scan Test Enable Scan Data In Scan Data Out Word Clock Reference Clock Test Clock Enable
I I O O I I
CCLK
Cell Clock
I
RESET
Reset Built-in Self Test Loop Back Built-in Self Test Enable Built-in Self Test Reset Built-in Self Test Pass
I
BSTLPBK
I
BSTEN BSTRST BSTPASS
I I O
G52191-0, Rev 4.2 01/05/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
High Performance 16x16 Serial Crosspoint Switch
Freq Type
<1MHz TTL <1MHz TTL <1MHz TTL <1MHz VECL 3.3V 3.3V 0V 2 ~ 2.5V
Data Sheet
VSC880
I/O
O I I O
Pin
LOCKDET VSCTE VSCIPNC VSCOPNC VDD1, VDD2, VDD3, VDD4 VDDA VSSA VMM
Name
CMU Lock Detect NOR Chain Test Enable NOR Chain Input NOR Chain Output Serial Port Power Supplies CMU Power Supply CMU Ground Core Power Supply
Description
This signal is LOW while the CMU is acquiring lock. Used for ATE testing of the parametric NOR chain in the I/O frame. Set to logic LOW during normal operation. Used for ATE testing of the parametric NOR chain in the I/O frame. Set to logic LOW during normal operation. Used for ATE testing of the parametric NOR chain in the I/O frame. Leave output open during normal operation. VDD1 = Serial Port 0-3 power supply VDD2 = Serial Port 4-7 power supply VDD3 = Serial Port 8-11 power supply VDD4 = Serial Port 12-15 power supply Clean power supply for CMU Clean ground for CMU Core power supply
P P P P
Functional Description
The VSC880 switch can be used in conjunction with the VSC870 transceivers to support two modes of operation: Packet Mode and Cell Mode. In Packet mode, the chip set provides a switching system to support variable length, self-routing data packets. In Cell Mode, the chip set provides a cell synchronous switching system with a user defined scheduler. In this mode, it can support only fixed length data packets (cells). Routing decisions are carried out in the scheduler and crosspoint configuration is synchronized to a cell clock. The scheduler configures the switch matrix using the parallel interface. To conserve power, each serial port quadrant can be powered down if not used. The following section gives a detailed functional description of the operation of the switch chip. Most of the discussion includes some of the transceiver operation (see the VSC870 data sheet). The two major operation modes are described separately in the Packet Mode and the Cell Mode sections.
1.0 Common Features
1.1 Synchronization
1.1.1 Link Characteristic
The serial link is used to connect the switch chip to transceivers. These links operate at 2.125 Gb/s and are initialized simultaneously at power up, or separately when a link error occurs. A link is first bit synchronized, then word synchronized and, if CMODE is HIGH, cell synchronized. In Packet or Cell mode, the switch acts as the master, generating the bit clock along with the word and cell boundary information. The transceivers act as slaves, recovering the bit clock, word clock and cell clock. The transceiver also contains redundant serial inputs and outputs which can be used with a redundant switch chip.
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(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52191-0, Rev 4.2 01/05/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
1.1.2 Data Scrambling
High Performance 16x16 Serial Crosspoint Switch
To allow the VSC870 CRU to recover the bit clock, a 15% edge transition density must be guaranteed on the serial data links. All command words and connection request words contain this required density. In order to get this density on data words, scrambling must be employed by the transceiver (see VSC870 data sheet).
1.1.3 Bit Synchronization
In Packet Mode and Cell Mode, the switch acts as the source of the bit clock. It multiplies the local 62.5MHz reference clock by 34 to generate a 2.125GHz clock and uses this clock to serialize the 32-bit word and 2 overhead bits. The transceiver receives and feeds this serial data stream to a digital CRU to recover the bit clock and deserialize the data stream to a 32-bit word plus 2 overhead bits at 62.5MHz. The transceiver also uses this recovered clock to serialize its transmit words that are sent to the switch. In this way, the switch and all the transceivers are frequency-locked to one clock source which is provided by the reference clock on the switch card. Because of this, the switch chip needs to recover only the phase information on the serial receive channel using a data recovery unit (DRU). The DRU is designed as a delay lock loop and remains phase-locked to the incoming data stream as long as the temperature does not change by more than 20C after link initialization. If this temperature variation is exceeded, a link error may occur causing the link to reinitialize. Because of this, system reset should be held until the system reaches temperature stability before starting the link initializing process.
1.1.4 Word Synchronization
During power up or at reset, the transceiver can initiate the word synchronization process. First, the transceiver sends reset patterns to the switch to request that the switch starts the initialization process. The switch, upon receiving this request, will send out special ALIGN words. The transceiver receives this serial data stream and word aligns to this ALIGN word by adjusting its own word boundary one bit at a time. Upon detecting the correct word alignment, it starts the transmit word alignment process. In this process, the transceiver continuously sends ALIGN words to the switch. The switch uses its own word clock (REFCLK) to detect this ALIGN word. If the transmitters word is not aligned to the switch chip word clock when it arrives at the switch, the switch chip continues to send out ALIGN words. After receiving 32 ALIGN words from the switch chip, the transceiver changes its transmit word boundary by 1 bit position and repeats the process (this limits the distance from the transceiver to the switch to less than 180ns one way). If the switch detects the transceivers ALIGN word correctly, it sends IDLE words to the transceiver to signal that the transmitter has now word synchronized with the switch. It also clears the internal registers LERR, TERR, DERR and CERR and sets the signal INT HIGH if all the enabled serial channels are successfully initialized (see section 1.4).
1.1.5 Cell Synchronization
If CMODE is set HIGH, after the word synchronization process completes, the transceiver starts the cell synchronization process. In this process, the transceiver detects the received cell clock (CCLK) sent from the switch embedded in the alignment word. The switch delays the global cell clock to adjust out the pipeline delay from the transceiver to the switch. The switch chip does this by connecting each port to itself during link initialization. By sending an ALIGN words to itself, the transceiver can adjust the transmit clock until it is properly phase shifted relative to the global cell clock. If cells are sent from the transceiver aligned to this transmit cell clock, they will arrive at the switch aligned to the master cell clock which is originated at the switch. For this alignment process to work, the minimum cell size is 8 words (32 bytes).
G52191-0, Rev 4.2 01/05/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
High Performance 16x16 Serial Crosspoint Switch
1.1.6 Link Error Detection
Data Sheet
VSC880
There are four types of link errors that can be flagged on the receive serial links. Link errors are detected using IDLE words. If a link error is detected, a bit in the LERR register is set HIGH for that particular channel (see section 1.4). After every 8 link errors, a bit in the TERR register is set HIGH. If the DRU goes out of range, a bit in the DERR register is set HIGH. If the last word in the cell period is an IDLE word and it does not have bits B[1:0] set HIGH to designate a cell clock, a bit in the CERR register will be set HIGH. If an error bit is set in any of these registers, the INT signal can be programmed to go LOW and/or the link can be programmed to automatically start link initialization depending on the value loaded into the Interrupt Control Register (see section 1.4). These error register bits will be cleared if the link is reinitialized, or the registers are read. If the signal RESYNEN is set HIGH, link initialization will begin immediately upon the detection of any of these errors. If the switch is used without IDLE words, the user is responsible for detecting parity error conditions and restarting the link initialization process.
1.2 Data Encoding Format
To provide self-routing and cell synchronization, the transceiver and switch require special word formats. Depending on the mode that the switch is used in, different word types are recognized by the switch. In both the Packet and Cell Modes, the switch processes both data words and command words. They have the same format in both modes and will be described in following section. The format for the connection request words and header words are described later in the Packet Mode section.
1.2.1 Data Word Format on the Serial Data Lines
The data word format as seen at the serial output of the transceiver or switch chip is shown below. Two overhead bits are added by the transceiver or switch chip to designate a data word to the receiving switch chip or transceiver. The serial data is transmitted with the MSB first.
33 32 BB 10 31 30 29 28 DDDD 31 30 29 28 27 26 25 24 DDDD 27 26 25 24 23 22 21 20 DDDD 23 22 21 20 19 18 17 16 DDDD 19 18 17 16 15 14 13 12 DDDD 15 14 13 12 11 10 09 08 DDDD 11 10 09 08 07 06 05 04 DDDD 07 06 05 04 03 02 01 00 DDDD 03 02 01 00
--------------- Data Payload ----------------
Where: B[1:0]If Packet Mode, 01=Flow control channel, 10=Flow control channel, 11=Acknowledge from switch chip or header word to switch chip If Cell Mode, 01, 10, 11 = data D[31:0]32 bit data payload
1.2.2 Command Word Format on the Serial Data Lines
The command word format as seen at the serial output of the transceiver or switch chip is shown below. Two overhead bits are added by the transceiver or switch to designate a command word (00) to the receiving switch chip or transceiver. The serial data is transmitted with the MSB first. In Packet Mode, the IDLE word from the switch always returns the current output connections for the port.
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G52191-0, Rev 4.2 01/05/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
33 32 00 31 30 29 1BB 10 28 27 26 25 24 CCCCC 04 03 02 01 00 -- Command -23 22 21 20 DDDD 15 14 13 12 19 18 17 16 DDDD 11 10 09 08 15 14 13 12 DDDD 07 06 05 04 -- Data -11 10 09 08 DDDD 03 02 01 00
High Performance 16x16 Serial Crosspoint Switch
07 06 05 04 1010
03 02 01 00 1010
Where: B[1:0]00=Undefined (during normal operation) or alignment word 01=Flow control channel, 10=Flow control channel, 11=Acknowledge (from switch chip only) or link initialization reset or cell clock in cell mode C[4:0]Command type 00XXX=Link Control (00000=ALIGN word, 00111=IDLE word) 01XX0=Command word for transceiver (01000=set DLYEN/CCKIN value) 10XX0=Command word for switch 11XX0=Command word for receiving port card (TBD) D[15:0]Optional data payload Default=1010101010101010 IDLE Word from switch=Current switch outputs this port is connected to D[15] is for port 0, D[0] is for port 15 If C[4:0]=01000, D[3:0]=DLYEN/CCKIN value
1.2.3 IDLE Words
IDLE words are the default word used on the serial channel when none of the other word types are present. In most cases, these words are automatically generated by the transceiver or switch chip. In Packet Mode, IDLE words are inserted between packets and the IDLE word from the switch always returns the current output connections for the port that is receiving the IDLEs. These connection bits will be in the same location as in the CRQ word. In cell mode, IDLEs will be transmitted from the switch chip if the force IDLE (FI) bit is set in the control registers. IDLE words are also used to detect link error conditions. If the switch chip detects an IDLE word, it uses a bit mask to verify the proper bit pattern within the word.
1.3 Loopback
The VSC880 supports a loopback function at the serial interfaces which is used in built-in self-test mode. If the BSTLPBK signal is set HIGH and TESTEN is set LOW, the serial transmit data is looped back to the serial receive side for all 16 channels. If the BSTLPBK signal is set HIGH and TESTEN is set HIGH, the serial transmit data is looped back to the serial receive side for channels 0-7 only. If the FACLPBK signal is set HIGH, the serial receive signal is looped back to the serial output for all 16 channels. Each channel can also be programmed to be looped back separately from serial input to serial output by using the control registers described below. The VSC880 does not support simultaneous BIST and facilty loopback functions (either FACLPBK pin or LPBK[15:0] register).
1.4 Internal Register Definitions
The internal status and control registers are defined in the following table. The address signal ADDR[5:0] is used along with CSEL and CWEN to read or write data through the CDATA[7:0] interface. CWEN is set LOW to write and HIGH to read from this port. If CSEL is HIGH, the outputs become high impedance and the inputs become
G52191-0, Rev 4.2 01/05/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
High Performance 16x16 Serial Crosspoint Switch
Data Sheet
VSC880
disabled. All data transfer timing is asynchronous to REFCLK. The Interrupt Control Register is written by the user to mask certain operations. If ICE is set HIGH, the INT output pin will go LOW if any error bit is set in the CERR register. If RCE is set HIGH, the link will automatically start link initialization if any error bit is set in the CERR register. The corresponding pins can be used for the DERR, TERR and LERR registers. If the INT signal goes LOW, the Interrupt Status Register can be read to determine which of the four registers received an error. The CDEL[3:0] bits are used to program a value for the cell clock delay (see section 3.0). The switch matrix status information can be read from the CN and FI registers. A serial link can be forced to reinitialize by writing a HIGH into the RSY register. A serial output can be logically disabled by writing a HIGH into the OE register. A serial input can be forced to loop back directly to a serial output by writing a HIGH into the LPBK register. All registers are cleared upon RESET. Also, the LERR, TERR, DERR and CERR registers are cleared on reading. Figure 1: Status and Control Register Definition CDATA[7:0] Bit Position ADDR[5:0]
X00000 X00001 X00010 X 00011 X00100 X00101 X00110 X00111 X01000 X01001 X01010 X01011 001100 001101 001110 001111 010000 010001 010010 R R R R R R R R R/W R/W R/W R/W R/W R/W R/W C0[3:0] C1[3:0] C2[3:0] C3[3:0] C4[3:0] C5[3:0] C6[3:0] CERR[7:0] CERR[15:8] DERR[7:0] DERR[15:8] TERR[7:0] TERR[15:8] LERR[7:0] LERR[15:8] C8[3:0] C9[3:0] C10[3:0] C11[3:0] C12[3:0] C13[3:0] C14[3:0] CCLK error register LSB CCLK error register MSB DRU error register LSB DRU error register MSB Error threshold register LSB Error threshold register MSB Link error register LSB Link error register MSB Output0/Output8 Config Output1/Output9 Config Output2/Output10 Config Output3/Output11 Config Output4/Output12 Config Output5/Output13 Config Output6/Output14 Config
R/W
R R/W R/W
7
6
5
4
3
CE
2
DE IDE
1
TE ITE
0
LE ILE Interrupt Status Register Interrupt Control Register BIST and Count Register
RCE
RDE
RTE
RLE BIST
ICE
CDEL[3:0]
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G52191-0, Rev 4.2 01/05/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
CDATA[7:0] Bit Position ADDR[5:0]
010011 101100 101101 101110 101111 110000 110001 110010 110011 X10100 X10101 X10110 X 10111 X11000 X11001 X11010 X11011
High Performance 16x16 Serial Crosspoint Switch
R/W
R/W R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
Output7/Output15 Config Output0/Output8 Status Output1/Output9 Status Output2/Output10 Status Output3/Output11 Status Output4/Output12 Status Output5/Output13 Status Output6/Output14 Status Output7/Output15 Status Force IDLEs LSB Force IDLEs MSB Resynch LSB Resynch MSB Output Enable LSB Output Enable MSB Loopback LSB Loopback MSB
C7[3:0] S0[3:0] S1[3:0] S2[3:0] S3[3:0] S4[3:0] S5[3:0] S6[3:0] S7[3:0] FI[7:0] FI[15:8] RSY[7:0] RSY[15:8] OE[7:0] OE[15:8] LPBK[7:0] LPBK[15:8]
C15[3:0] S8[3:0] S9[3:0] S10[3:0] S11[3:0] S12[3:0] S13[3:0] S14[3:0] S15[3:0]
Where: CE Cell clock errorRCE Resynch on cell errorICE Interrupt on cell error DE DRU error RDE Resynch on DRU errorIDE Interrupt on DRU error TE Threshold errorRTE Resynch on thresh errorITE Interrupt on threshold error LE Link error RLE Resynch on link errorILE Interrupt on link error BIST Set this bit HIGH to test the BIST circuitry CDEL[3:0] Cell clock delay CERR[15:0]Cell clock error register, bit 0 is channel 0 etc, Cleared on read DERR[15:0]DRU error register, bit 0 is channel 0 etc. Cleared on read TERR[15:0]Threshold error register, bit 0 is channel 0 etc. Cleared on read LERR[15:0]Link error register, bit 0 is channel 0 etc, Cleared on read CN[3:0]Switch configuration data. N is the output port number, [3:0] is the input port connected. Default = 0xF. SN[3:0]Output status data. N is the output port number, SN[3:2] = 00 for normal operation. 01 for out of synch 10 for word synch in progress 11 for cell synch in progress SN[1] = Output busy in packet mode SN[0] = Connection valid in packet mode
G52191-0, Rev 4.2 01/05/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
High Performance 16x16 Serial Crosspoint Switch
FI[15:0]Force IDLE register, bit 0 is channel 0 etc RESY[15:0]Resynch register, bit 0 is channel 0 etc OE[15:0]Output enable register, bit 0 is channel 0 etc LPBK[15:0]Facility loopback register, bit 0 is channel 0 etc
Data Sheet
VSC880
1.5 Parallel CPU Interface
There is a parallel 8 bit CPU interface on the VSC880 that can be used to read and write the status and control registers described above. This is an asynchronous interface that was design to operate with many common micro controllers that are available. The functional timing diagrams for a write and a read are shown in the following figures. Timing information can be found in the AC Characteristics section of this data sheet. Figure 2: CPU Interface Functional Write Cycle Timing
CWEN CSEL ADDR CDATA Valid Address Valid Data
Figure 3: CPU Interface Functional Read Cycle Timing
CWEN CSEL ADDR CDATA Valid Address Valid Data Hi-Z
1.6 Parallel Configuration Interface
In addition to reading and writing the switch configuration using the CPU interface as described above, the entire switch matrix can be reprogrammed in 4 word clocks by setting the CEN signal LOW. If CEN is set LOW, the parallel interface DATA[15:0] contains a 16 bit switch configuration input port, the inputs FI[3:0] load the FI bits and the WEN signal becomes a programming signal as shown in the figure below. It takes 4 word clocks to load all 64 bits of switch configuration data and 16 FI bits into holding registers. All data transfer timing is relative to REFCLK. After data has been loaded, and if CCLK is HIGH, all 80 bits of data are strobed into the switch matrix and FI control logic. Otherwise, the configuration information is stored in holding registers until the next CCLK pulse strobes it in. Since the CCLK signal is delayed internally in the switch, it can be asserted as early as the WEN signal pulse to strobe in the configuration information.
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G52191-0, Rev 4.2 01/05/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
High Performance 16x16 Serial Crosspoint Switch
Figure 4: Switch Configuration Interface Functional Timing (CEN=0)
REFCLK FI[3:0] DATA[15:0] WEN CCLK F0 C0 F1 C1 F2 C2 F3 C3 Switch updated in this cycle
Min. of 5 Cycles
The switch configuration data for each port is as follows: F0[3:0] = FI[port9], FI[port8], FI[port1], FI[port0] F1[3:0] = FI[port11], FI[port10], FI[port3], FI[port2] F2[3:0] = FI[port13], FI[port12], FI[port5], FI[port4] F3[3:0] = FI[port15], FI[port14], FI[port7], FI[port6] C0[15:0] = Port9[3:0], Port8[3:0], Port1[3:0], Port0[3:0] C1[15:0] = Port11[3:0], Port10[3:0], Port3[3:0], Port2[3:0] C2[15:0] = Port13[3:0], Port12[3:0], Port5[3:0], Port4[3:0] C3[15:0] = Port15[3:0], Port14[3:0], Port7[3:0], Port6[3:0] Where FI[portN] is the Force IDLE bit for port N and PortN[3:0] is the input port number to be connected to output port N.
1.7 Built-in Self-Test
The switch has built-in self-test logic that can be used to verify the high-speed circuitry as well as the switch matrix while operating at full speed. The built-in self-test mode is enabled by setting the built-in self-test enable (BSTEN) signal HIGH. If the signal BSTLPBK is set HIGH and TESTEN is set LOW, it loops all 16 serial outputs back to the Data Recovery Unit (DRU) at the serial inputs. An internal Pseudo Random Bit Sequence (PRBS) generator connected to the switch matrix at port 0. The random data is sent to port 0, passed through the switch matrix, looped back through the serial interface and returned to the data comparator. If this data matches the correct pattern, BSTPASS is set HIGH. By configuring port 0 to connect to other ports (ports 1 through 15) through the switch matrix using the parallel configuration interface, the rest of the serial channels (one port at a time) can be tested in turn. For example, port 0 can be connected to port 1 by configuring the switch matrix. The PRBS generator transmits the random data through port 0 to port 1, and the random data is then looped back from port 1 to port 0 and the data comparator. To test all 16 ports, the user will need to configure the switch matrix 16 times to test all ports.
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High Performance 16x16 Serial Crosspoint Switch
Figure 5: Built-in Self-Test Functional Timing
REFCLK ADDR[4:0] BSTRST < 10S
Data Sheet
VSC880
BSTPASS
The signal BSTRST is used to reset the PRBS pattern, and there is a comparator that sets the signal BSTPASS HIGH if the test was successful. The functional timing diagram above shows a typical test sequence. The PRBS pattern generator can also be tested by itself by setting the control register bit BIST HIGH. This loops the output of the pattern generator directly back to the comparator circuit. This test will be typically run before running the tests described above. In this case, the signals BSTEN, BSTRST and BSTPASS will operate as shown in the Figure 5 above. The BIST test can be run on no more than two ports at a time, for example: port 0port 3port 8port 0.
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Data Sheet
VSC880
2.0 Packet Mode
2.1 Overview
High Performance 16x16 Serial Crosspoint Switch
In Packet Mode (CMODE=LOW), command words can be sent through the transceiver to the switch chip requesting connection to one or multiple output channels. Acknowledge (ACK) information will be returned to the transceiver from the switch allowing the port card to start transmitting data. In this mode of operation, no controller chip is connected to the switch chip as the switch chip handles all arbitration for connection requests. Details on how the transceiver operates in Packet Mode mode can be found in the VSC870 data sheet and the applications note 31: "Design Guide for a Packet Based Switch with Distributed Control". A picture of a self routing system is shown below. The minimum packet size in this mode of operation is 4 words or 16 bytes. Figure 6: Packet Mode System
Port Card
TXFIFO Trans RXFIFO VSC870
Switch Card
Switch Chip
VSC880
Port Card
TXFIFO Trans RXFIFO VSC870
2.2 Data Encoding Format
The data word and command word formats are described in section 1.0. In this section the header word and Connection Request (CRQ) word format at the serial input and serial output of the switch are described.
2.2.1 Header word Format on the Serial Data Lines
The header word format as seen at the serial output of the transceiver or switch chip is shown below. Two overhead bits are added to designate a header word to the receiving chip. The serial data is transmitted with the MSB first. If multiple headers are sent in a row, the VSC870 will convert all but the first one into IDLEs.
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High Performance 16x16 Serial Crosspoint Switch
Data Sheet
VSC880
23 22 21 20 DDDD 19 18 17 16 19 18 17 16 DDDD 15 14 13 12 15 14 13 12 DDDD 11 10 09 08 11 10 09 08 DDDD 07 06 05 04 07 06 05 04 DDDD 03 02 01 00 03 02 01 00 1010
33 32 AA 10
31 30 29 28 0BB1 10
27 26 25 24 0110
--------------- Data Payload ----------------
Where: A[1:0]11=to switch chip, 00=from switch chip B[1:0]00=Undefined, 01=Flow control channel, 10=Flow control channel, 11=Acknowledge to transceiver D[19:0]20 bit data payload
2.2.2 CRQ Word Format on the Serial Data Lines to the Switch
The CRQ command word format as seen at the output of the transceiver is shown below. Two overhead bits are added by the transceiver to designate a CRQ word to the receiving switch chip. The signal ARB, AOA and BRK are used to control modes of operation in the switch chip. The serial data is transmitted with the MSB first.
33 32 00 31 30 29 28 27 0BB10 10 26 25 24 AAB ROR BAK 23 22 21 20 CCCC 00 01 02 03 19 18 17 16 CCCC 04 05 06 07 15 14 13 12 CCCC 08 09 10 11 11 10 09 08 CCCC 12 13 14 15 07 06 05 04 DDDD 03 02 01 00 --Data-03 02 01 00 1010
------ Connection Bits ------
Where: B[1:0]00=Undefined, 01=Flow control channel, 10=Flow control channel, 11=Undefined ARB1=Multi Queue arbitration AOA1=Acknowledge on all connections granted, 0=Acknowledge on any connections granted BRK 1=Break previous connection, 0=Do not break previous connection C[0:15] Connection request bit map. Set bit high for each output requested D[3:0] User defined data sent by transmitting port card
2.2.3 CRQ Word Format on the Serial Data Line From the Switch
The CRQ command word format as seen at the output of the switch chip is shown below. Two overhead bits are added by the switch chip to designate a command word (00) to the transceiver. This word is sent on to the receiving port card when an ACK is sent to the transmitting port card. The command word contains the current active connections for this input in the switch chip. The serial data is transmitted with the MSB first.
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Data Sheet
VSC880
33 32 00 31 30 29 28 27 26 25 0BB1010 10 24 B R K 23 22 21 20 MMMM 00 01 02 03 19 18 17 16 MMMM 04 05 06 07 15 14 13 12 MMMM 08 09 10 11 11 10 09 08 MMMM 12 13 14 15
High Performance 16x16 Serial Crosspoint Switch
07 06 05 04 DDDD 03 02 01 00 --Data--
03 02 01 00 1010
------ Active Connections ------
Where: B[1:0]00=Undefined, 01=Flow control channel, 10=Flow control channel, 11=Acknowledge BRK1=This is the CRQ word for the next packet. This bit is used to break the current connection. M[0:15]Current outputs the transmitting channel is connected to D[3:0] User defined data sent by transmitting port card
2.3 Receiver Operation
In Packet Mode, the receiver looks for connection request (CRQ) words from the transceiver. All data words and IDLE words are passed on directly to the switch matrix. If BRK is HIGH, the current connection will be broken before processing the new connection request word. When BRK is LOW, the switch does not break current connections when making a new request. When AOA is HIGH, the switch will send an ACK only if the current switch connections match the C[0:15] bit field. When AOA is LOW, an ACK is sent back to the transceiver when any connection in the C[0:15] bit field is granted. In both cases, a response word is also returned to the transceiver from the switch. The response word can be embedded into an IDLE word or CRQ word that is sent back to the transceiver. If the transceiver makes a CRQ that requires a response (i.e., a multicast CRQ), the switch uses the flow control channel to force an IDLE word into the receiving data stream by forcing the internal ready to receive (RTR) signal low for one word clock (see the VSC870 data sheet). The bit field C[0:15] is used to designate the output channels that are to be acted upon for a connection request operation. To request an output to connect to, set the corresponding bit HIGH. Multiple bits can be set HIGH at the same time for multicast. The sending port card can include 4 bits of data (D[3:0]) in the CRQ word that will be passed on to the destination port card. Two example word sequences from the transceiver on the serial interface are shown in the Figure 7. The two overhead bits (BB) are used for signaling on data words (see the VSC870 date sheet).
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Figure 7: Packet Transmission Format from Transceiver
Data Sheet
VSC880
Example 2:
Example 1:
11 BB BB Header D0 D1
Start of Packet
11 BB
Header D0
Start of Packet
00 BB BB 00 00 00 11 BB DN CRQ CRQ CRQ IDLEs Header D0
CRQ CRQ D(N-D)
D words before EOP
End of Packet
Zero or more IDLEs
BB 00 00 11 BB
DN CRQ IDLEs Header D0
End of Packet
Zero or more IDLEs
2.4 Arbitration
In Packet Mode, if multiple inputs request a connection to the same output, arbitration is performed. Connection requests come into the switch chip on each word clock, and the arbitration process takes two word clock cycles. Arbitration is round-robin with the last connection to an output getting the lowest priority for that output. For multicast, if BRK is LOW, arbitration will only be performed on the requested connections that are not currently granted. If a port is in the out of synch state, any connection request to this port will be always granted. In order to improve bandwidth utilization, a system wide mode of operation can be used where the switch matrix reconfiguration time is delayed D word clocks after the time arbitration results are determined. This allows the user logic to receive arbitration results ahead of time so the port cards do not have to block data while waiting for these results. If the CRQ word is inserted into the current data packet D words before the end of the packet, arbitration results will be known at the port card just as the first word of the next data packet is ready for transmission, thus improving bandwidth utilization. The number D is selected based on the round trip delay from the time the port submits a CRQ until an ACK is received and the FIFO is ready to send a data word. This value of D is a system wide value and must be used by all port cards. D should be set to a maximum value equal to the round trip delay (typically 8 word clocks). For Multi Queue connection requests from the transceiver (ARB = 1), the switch chip performs two levels of arbitration during two word clock cycles. The first level determines which of the requested outputs are available and holds these outputs. The second level chooses one winner from the available outputs then releases the rest. Because outputs can be blocked during the first level of arbitration, all Muti Queue CRQ commands are held at the switch chip and continue to request outputs until a connection is granted or a header word is detected. If a header word is detected at the transceiver, a repeated sequence of CRQ words is sent to the switch until a connection is granted. The port number of the granted output is returned to the port card using the two overhead bits (see VSC870 data sheet).
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Data Sheet
VSC880
2.5 Transmitter Operation
High Performance 16x16 Serial Crosspoint Switch
In Packet Mode, the transmitter sends out data words that come from the switch matrix, adding the appropriate overhead bit information for acknowledges, response bits and flow control. Acknowledges are used to signal the transceiver that a connection request has been granted (see the VSC870 data sheet). The response bits are used with the Multi Queue connection request word. The flow control channel is used to pass state information from the receiving port card to the transmitting port card. The switch redirects the flow control signals to the correct output using the current switch connection state information. In the case of multicast where there is more than one receiver, these channels are logically ORed before being sent back to the transmitter. The flow control channel is also used to send response bits from the switch to the transceiver for multi queue mode (see VSC870 data sheet). Response words are required by the transceiver in Packet Mode. These response words are simply IDLE words or CRQ words in the data stream that are going back to the transceiver containing port connection status information. If the transceiver receives a connection request word that requires a response, it can use the flow control channel to force an IDLE word into the data stream. When this IDLE arrives at the switch, the switch adds the response data.
2.6 Disconnect Operation
A disconnect can be made to occur automatically after a packet is transmitted through the switch if the packet is followed by either a CRQ (Connection Request) associated with a new packet, or a null CRQ followed by a null header word. The CRQ associated with the new packet typically has the BRK bit set. This breaks down the old connection before it tries to establish the new connection through arbitration. This new connection is made only when the switch receives the header word. When the old connection is broken, the associated output ports are freed up, becoming available for new connections. The null CRQ is a CRQ with the BRK bit set, and has no output port selected. In this case, the switch chip will break down the old connection(s) and will not establish any new connections. The null CRQ word must be followed by a null (empty) header word. The switch will send IDLE words to the transceivers which have not established a new connection. During the packet transmission, if the sending link goes out of synch, the switch will terminate the connection and send an end of packet word (CRQ with the BRK bit set LOW) to the destination port followed by IDLE words. In this case, the receiving transceiver will receive only one CRQ instead of the two normally received.
2.7 Flow Control Channel
The VSC880 can support a back pressure mechanism by providing a flow control channel. The flow control channel is time shared with the signaling between the switch chip and the transceiver for acknowledgment and response bits. Therefore, it can only guarantee to pass the state information from input pin at the receiving port card through the switch and to the output pin at the transmitting port card. The main application for this flow control channel is to prevent the FIFO on the receiving side from overflowing. By using this channel, when the receive FIFO is almost full, the transmit FIFO will be disabled from sending data. During the time the switch is sending an ACK or response bits back to the port cards, these flow control bits are dropped by the switch. During a multicast transmission, the flow control channels are ORed in the switch. If a port is in an out of synch state, no flow control back pressure is exerted from this output.
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Data Sheet
VSC880
3.0 Cell Mode
3.1 Overview
In Cell Mode (CMODE = HIGH), a more sophisticated arbitration scheme can be supported by using the VSC870 and the VSC880 switch in conjunction with a central (user defined) scheduler. In this mode, only fixed length data packets (cells) can be supported. A cell clock is connected to the switch chip, and the switch chip distributes the cell clock to all connected transceivers. The transceivers adjust their transmit cell clocks so that all transceivers send the first word of a cell at such time that it arrives at the switch chip aligned to the switch cell clock (see serial link operation above). In this mode, messages containing port card queue information are sent to the central scheduler using an out of band control bus. Arbitration and flow control information are then sent back to the port cards through the out of band control bus. The scheduler then configures the switch matrix by using the parallel interface. A picture of a cell based system is shown below. Multiple switch chips can be used in parallel to increase system bandwidth (see Application Note 32 "Design Guide for a Cell Based Switch with Central Control"). Figure 8: Cell Based System
Port Card
Queuing System Trans
Switch Card
VSC870
Switch Chip
VSC880
Scheduler/ Arbiter
Port Card
Queuing System Trans VSC870
Out-of-band Control Bus
3.2 Data Encoding Format
The data word and command word formats are described in section 1.0. Command words use the overhead bits set to 00. Data words can have overhead bits 01, 10 or 11. The user can use these bits for signaling to the receiving port card. Information such as start of frame and end of frame can be passed through the switch in this manner.
3.3 Receiver Operation
If CMODE is HIGH, the receiver at each port examines the two overhead bits (B[1:0]) of the received word to determine the word type. If the word is a command word sent from the port card, the switch will respond based on the type of command specified in the C[4:0] bit field. If an IDLE word arrives at the end of the cell clock period and it does not have an embedded cell clock, a cell clock error is flagged. If it is a data word, it is sent to the switch fabric to be routed to its destination along with the user defined overhead bits.
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Data Sheet
VSC880
3.4 Transmitter Operation
High Performance 16x16 Serial Crosspoint Switch
If CMODE is HIGH and the force IDLE register is set LOW, the transmitter sends data words from the switch fabric. If the force IDLE register is set HIGH, IDLE words are transmitted. At the end of the cell clock period, bits B[1:0] in all IDLE words are set to 11 to embed the cell clock marker. For data words, user defined overhead bits are passed on to the destination as is.
3.5 Delaying The Cell Clock
If out-of-band messaging is used between the port cards and the switch card, there will be a phase offset between the cell clock (CCLK) on the switch card, and the transmit cell clock (RTM/TCLK) on the port card. A cell clock delay value can be programmed into the control register CDEL[3:0] to set the time the switch is configured after receiving a cell clock. This adds 1-14 word clocks worth of delay between CCLK input to the switch chip and the cell clock sent to the transceivers from the switch chip. In this way, the transmit cell clock (RTM/TCLK) on the transceivers can be aligned to the cell clock at the switch chip (CCLK). For a typical system design where the transceiver is less then 20" from the switch chip, the default value of 5 can be used. See Application Note 32 for more details.
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Data Sheet
VSC880
AC Characteristics
Table 1: LVDS and TTL Outputs
Parameters TR,TTL TF,TTL TR,LVDS TF,LVDS
Description TTL Output Rise Time TTL Output Fall Time LVDS Output Rise Time LVDS Output Fall Time
Min
2.5 2.5
Typ
Max
Units
ns ns
Conditions 10-90% @ 50pF 10-90% @ 50pF 20-80% 20-80%
100 100
ps ps
Figure 9: Parallel Data Input Timing Diagram
TREFCLK
REFCLK TINSU TINH
DATA[15:0], FI[3:0], WEN, CEN, CCLK,
Table 2: Transmit Data Input Timing Table
Parameter
TREFCLK FREFCLK JREFCLK TINSU TINH TSKEW
Description
Reference (word) clock period Reference clock frequency stability Reference clock input jitter Parallel data setup time with respect to REFCLK Parallel data hold time with respect to REFCLK REFCLK to REFCLK skew using parallel switch chips
Min
Typ
16
Max
100 7
Units
ns ppm ps RMS ns ns
1 2 1
ns
Note: Duty cycle for TREFCLK is 50% +/- 10% worst case
Figure 10: Parallel Data Output Timing Diagram
TINT
TINT
INT
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Data Sheet
VSC880
Table 3: Receive Data Output Timing Table
High Performance 16x16 Serial Crosspoint Switch
Parameter
TINT TRESET Interrupt pulse width
Description
RESET, RESYNEN pulse width
Min
15 64
Typ
Max
Units
ns ns
Figure 11: CPU Interface Write Cycle Timing
TSU CWEN CSEL ADDR[5:0] CDATA[7:0] TOK TWS TWC TH
Valid Address Valid Data
TWV
Figure 12: CPU Interface Read Cycle Timing
TSU CWEN CSEL TA ADDR[5:0] TRD CDATA[7:0] TRZ TD TH
Valid Address Hi-Z
TRV
Valid Data
Hi-Z
Table 4: CPU Interface Timing Table
Parameter
TOK TD TSU TH TWV TWS TWC TRV TRZ TRD
Description
CSEL falling edge to valid address CSEL inactive between read cycles CWEN valid to CSEL falling edge CSEL active to CWEN change Valid data and address during a write CSEL low time during a write CSEL cycle time during a write CSEL active to valid data CSEL deactivate to high impedance data CSEL active to low impedance data
Min
10 5 5 45 20 55 15 0
Typ
Max
5
Units
ns ns ns ns ns ns ns
45 5
ns ns ns
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Data Sheet
VSC880
DC Characteristics
Table 5: LVDS and TTL Inputs and Outputs
Parameters
VOH VOL VOCM VOUT VICM VIN VIH VIL IIH IIL IOZB
Description
Output HIGH voltage (TTL) Output LOW voltage (TTL) O/P Common Mode Range (LVDS) Differential Output Voltage (LVDS) I/P Common Mode Range (LVDS) Differential Input Voltage (LVDS) Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Bi-directional (TTL) HIGH current 3-State Output OFF
Min
2.4 -- 1.2 400 0.8 200 2.0 0 -- - 50
Typ
-- -- -- -- -- -- -- -- -- --
Max
-- 0.4 2.1 1000 2.5 1600 VDD+1.0 0.8 500 -- 500
Units
V V V mV V mV V V A A A
Conditions
IOH = -6.0 mA IOL = +6.0 mA At Min VOUT 100 across input At Min VIN -- -- -- VIN =2.4V VIN = 0.4V VOUT=2.4V
Hot Swap The LVDS input and output buffers are subject to hot swap events while being connected and disconnected from the passive backplane. If the input is powered down but still receiving a signal from an output, the input must tolerate extra input current and power. If the input is powered up but has no input connection, it must go to a valid logic state. The Table 6 below lists the LVDS I/O parameters that relate to hot swap condition. Table 6: Hot Swap LVDS I/O Parameters
Parameters
ICO ICI PCI VCDL
Description
LVDS maximum current delivered per output pin LVDS maximum current allowed per input pin LVDS maximum added power per output pin LVDS input default logic state
Value
10 40 60 LOW
Units
mA mA mW --
Conditions
Normal Operation VDD = 0V VDD = 0V on VSC870 Input Open
Power Dissipation
Table 7: Power Supply Currents
Parameter
IDD IDDA IDDX IMM PDS PDD
Description
Power supply current from VDD, VDDA (VDD, VDDA = 3.3V + 5%) Power supply current from VDDA (VDDA = 3.3V + 5%) Power supply current from each serial data quadrant VDDX (VDDX = 3.3V + 5%) Power supply current from VMM (VMM = 2.5V + 5%) Power dissipation (VDD = 3.3V+5%, VMM = 2.5V+5%, all quadrants powered) Power dissipation (VDD = 3.3V+5%, VMM = 2.0V+5%, all quadrants powered)
(Max)
1000 200 750 6800 30.7 28.1
Units
mA mA mA mA W W
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Data Sheet
VSC880
Absolute Maximum Ratings(1)
High Performance 16x16 Serial Crosspoint Switch
Power Supply Voltage (VDD) Potential to GND.................................................................................-0.5V to +4V Power Supply Voltage (VMM) Potential to GND ................................................................................-0.5V to +4V DC Input Voltage (LVDS inputs) .......................................................................................... -0.5V to VDD + 1.0V DC Input Voltage (TTL inputs) ......................................................................................................... -0.5V to 5.5V DC Input Voltage (TTL inputs for CDATA[7:0]).................................................................. -0.5V to VDD + 1.0V DC Output Voltage (TTL outputs) ........................................................................................ -0.5V to VDD + 1.0V Output Current (TTL outputs) .................................................................................................................. +/-50mA Output Current (LVDS outputs) ................................................................................................................+/-50mA Case Temperature Under Bias ...................................................................................................... -55oC to +125oC Storage Temperature..................................................................................................................... -65oC to +150oC
NOTE: (1) Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
Recommended Operating Conditions
Power Supply Voltage (VDD)................................................................................................................. +3.3V 5 % Power Supply Voltage (VMM) .............................................................................................. (+2.0V to +2.5V) 5 % Extended Commercial Operating Temperature Range(1) (T) ...............................................................0oC to 85oC
NOTE: (1) Lower limit of specification is ambient temperature and upper limit is case temperature.
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Data Sheet
VSC880
Package Pin Descriptions
Signal
NC VSS VSS VSS NC REFCLK CCLK VSS DATA[2] DATA[5] DATA[6] DATA[10] DATA[13] DATA[14] FI[1] VSS WEN BSTRST NC VSS VSS VSS NC VSS VSS VSS NC NC NC TCLKEN VMM DATA[1] DATA[3] DATA[8] DATA[9] DATA[11] FI[0]
Pin
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14
Signal
FI[2] VMM BSTLPBK NC NC NC VSS VSS VSS NC VSS NC NC NC VSS VMM RESET DATA[0] DATA[4] DATA[7] VMM DATA[12] DATA[15] FI[3] CEN VMM VSS NC VSS NC VSS NC VMM NC VDD1 NC VSSA
Pin
B15 B16 B17 B18 B19 B20 B21 B22 B23 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D01 D02 D03 D04 D05
Signal
VDDA NC VMM VDD VMM VMM VDD1 VMM VMM VDD VMM BSTEN VDD VSS NC VDD4 NC VMM RXS[0]VSS TXS[0]+ VDD1 VDD4 TXS[15]+ VSS RXS[15]VSS RXS[0]+ VDD1 TXS[0]TXS[15]VDD4 RXS[15]+ VSS TXS[1]+ VSS RXS[1]-
Pin
D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 E01 E02 E03 E04 E20 E21 E22 E23 F01 F02 F03 F04 F20 F21 F22 F23 G01 G02 G03
Signal
VDD1 VDD4 RXS[14]VSS TXS[14]+ VDD1 TXS[1]VDD1 RXS[1]+ RXS[14]+ VDD4 TXS[14]VDD4 RXS[2]VSS TXS[2]+ VDD1 VDD4 TXS[13]+ VSS RXS[13]NC RXS[2]+ VDD1 TXS[2]TXS[13]VDD4 RXS[13]+ VSS RXS[3]RXS[3]+ NC VSS VSS NC RXS[12]+ RXS[12]-
Pin
G04 G20 G21 G22 G23 H01 H02 H03 H04 H20 H21 H22 H23 J01 J02 J03 J04 J20 J21 J22 J23 K01 K02 K03 K04 K20 K21 K22 K23 L01 L02 L03 L04 L20 L21 L22 L23
Page 24
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52191-0, Rev 4.2 01/05/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
Signal
VMM VDD1 TXS[3]TXS[3]+ TXS[12]+ TXS[12]VDD4 VMM VMM VDD2 TXS[4]TXS[4]+ TXS[11]+ TXS[11]VDD3 VMM RXS[4]RXS[4]+ VSS NC VSS NC RXS[11]+ RXS[11]NC RXS[5]+ VDD2 TXS[5]TXS[10]VDD3 RXS[10]+ VSS RXS[5]VSS TXS[5]+ VDD2 VDD3 TXS[10]+ VSS
High Performance 16x16 Serial Crosspoint Switch
Pin
M01 M02 M03 M04 M20 M21 M22 M23 N01 N02 N03 N04 N20 N21 N22 N23 P01 P02 P03 P04 P20 P21 P22 P23 R01 R02 R03 R04 R20 R21 R22 R23 T01 T02 T03 T04 T20 T21 T22
Signal
RXS[10]VDD2 TXS[6]VDD2 RXS[6]+ RXS[9]+ VDD3 TXS[9]VDD3 TXS[6]+ VSS RXS[6]VDD2 VDD3 RXS[9]VSS TXS[9]+ VSS RXS[7]+ VDD2 TXS[7]TXS[8]VDD3 RXS[8]+ VSS RXS[7]NC TXS[7]+ VMM VSS VDD
SCANOUT
Pin
T23 U01 U02 U03 U04 U20 U21 U22 U23 V01 V02 V03 V04 V20 V21 V22 V23 W01 W02 W03 W04 W20 W21 W22 W23 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14
Signal
VDD VDD CDATA[4] VDD VSS VMM TXS[8]+ NC RXS[8]VMM VDD2 VMM VSS VSCIPNC VSS VSS
LOCKDET
Pin
Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB01 AB02 AB03 AB04 AB05 AB06 AB07
Signal
VMM NC FACLPBK RESYNEN VSCTE ADDR[4] CSEL NC VMM CDATA[2] CDATA[5] CDATA[7] NC VSS VSS VSS VSS VSS VSS VSS NC BSTPASS INT VSS MEN NC CMODE ADDR[5] ADDR[2] ADDR[1] CWEN VSS CDATA[0] CDATA[3] CDATA[6] VSS VSS VSS VSS
Pin
AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23
NC SCANIN TESTEN VMM ADDR[3] ADDR[0] NC CDATA[1] VSS VSS NC NC VMM VDD3 VMM NC VSS VSS NC VSCOPNC NC WCLK
VDD VDD VMM VMM VSS VMM VMM
G52191-0, Rev 4.2 01/05/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 25
VITESSE
SEMICONDUCTOR CORPORATION
High Performance 16x16 Serial Crosspoint Switch
Data Sheet
VSC880
304 BGA Package
Package Information
Page 26
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52191-0, Rev 4.2 01/05/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
Package Thermal Characteristics
High Performance 16x16 Serial Crosspoint Switch
The VSC880 is packaged in a thermally enhanced 31mm 304TBGA with an embedded heat sink. The heat sink surface configurations are shown in the package drawings. With natural convection, the junction to case thermal resistance is estimated to be 0.45oC/W. The approximate air flow versus thermal resistance relationship is shown in Table 12.3. Note: The VSC880 is not guaranteed to operate under cold start conditions. If the ambient temperature is 0oC, 15 seconds after power is applied, the case temperature will be at least 30oC, at which point it will be at thermal equilibrium and ready for operation. Table 8: Theta Junction-to-Ambient versus Air Velocity
Air Velocity (LFPM)
0 100 200 400 600
Junction-to-Ambient Thermal Resistance (oC/W) Low Conductivity 2-Layer Board
17.5 15.0 13.0 11.0 10.0
High Conductivity 4-Layer Board
13.0 11.0 10.0 9.0 8.0
Ordering Information
The order number for this product is formed by a combination of the device number and package type.
VSC880 xx
Device Type High Performance 16x16 Serial Crosspoint Switch Package TY: 304 BGA Extended Commerical Temperature: 0C ambient to +85C case
Notice
Vitesse Semiconductor Corporation ("Vitesse") provides this document for informational purposes only. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
G52191-0, Rev 4.2 01/05/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 27
VITESSE
SEMICONDUCTOR CORPORATION
High Performance 16x16 Serial Crosspoint Switch
This page left intentionally blank.
Data Sheet
VSC880
Page 28
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52191-0, Rev 4.2 01/05/01

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