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Ordering Information
Device HV421 8-Lead SO HV421LG
LETE - OBSO
HV421
High Voltage 1 REN Ring Generator
Package Options
Features
Processed with HVCMOS(R) technology 4.75V to 9.5V operating supply voltage DC to AC conversion 1 REN load capacity Adjustable ring frequency from 15Hz to 60Hz Adjustable converter frequency Enable/Disable function
General Description
The Supertex HV421 is a high voltage ring generator designed to drive 1 North American REN (ringer equivalent number) from a 5V source. The HV421 has an internal DC-DC converter which converts the 5V DC supply to a nominal 68V DC connected to the VPP pin. The DC-DC converter frequency of the HV421 is set by an external resistor connected between RSW and VDD. The ringing signal is generated by a high voltage H-bridge which produces two square waves which are 180 degrees from each other. The ringing frequency of the H-bridge is set by an external resistor connected between RRING and VDD.
11
Absolute Maximum Ratings*
Supply Voltage, VDD Output Voltage, Vcs Operating Temperature Range Storage Temperature Range SO-8 Power Dissipation
Note: *All voltages are referenced to GND.
Pin Configuration
-0.5V to +10V -0.5V to +120V 0C to +85C -65C to +150C 400mW VDD RSW VPP Lx
1 2 3 4
8 7 6 5
Rring Gate Gate GND
Top View
SO-8
11-1
HV421
Electrical Characteristics
DC Characteristics
Symbol RDS(ON) IDDQ IDD IIN VPP FRING DRING fsw Dsw (VDD=5.0V, RRING=30M, RSW=1.3M, LX=330H, TA=25C) Parameter On-resistance of switching transistor Quiescent VDD supply current Input current going into the VDD pin Input current including inductor current Output voltage on VPP Ring frequency Ringing frequency duty cycle Switching transistor frequency Switching transistor duty cycle 65 20 170 68 25 50 35 88 30 Min Typ 3.5 Max 5 50 300 220 Units nA A mA V Hz % KHz % VIN=5.0V. See Figure 1. I=100mA RSW=Low VIN=5.0V. See Figure 1. VIN=5.0V. See Figure 1. VIN=5.0V. See Figure 1. VIN=5.0V. See Figure 1. Conditions
Recommended Operating Conditions
Symbol VDD TA Supply voltage Operating temperature Parameter Min 4.75 0 Typ Max 9.5 85 Units V C Conditions
LETE - Enable/Disable Table OBSO -
Symbol EN-L EN-H Parameter Min 0 VDD-0.5 Typ Max 0.5 VDD Units V V Logic input low voltage Logic input high voltage
Conditions
11-2
HV421
Block Diagram
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Lx VPP DC-DC Converter Gate
VDD
RSW
RRING GND
Ring Frequency
Level Translator
Gate
Typical Application
ON = 4.75V OFF = 0V
30M
0.01F
Q1
D1
11
6.8K
1
330H
VDD RSW VPP Lx
RRING Gate Gate GND HV421LG
8 7
D2
1.3M
2 3
Q2 2.2K Q3
D3
VIN
4.75V 160mA
6
1N4148
4 5
2.2K
8.0F Load
D4
1.0F
0.01F
Q4
Q1, Q3 = Supertex VN2110K1 Q2, Q4 = Supertex VP2110K1 D1-D4 = 5.1V Zener diode VOUT = 60V Freq = 25Hz
Figure 1: 1 REN Ring Generator
11-3
HV421
Application Description The Supertex HV421LG is a high voltage 1 REN ring generator. A typical application circuit is shown in Figure 1. There are four basic parts to the circuit; the DC-DC converter, level translation of the ringing frequency, enable/disable function, and an external source follower buffer stage. DC-DC converter The DC-DC converter consists of a 330H inductor, 1N4148 diode, 1.0F capacitor and 1.3M resistor. The 1.3M resistor sets the DC-DC converter frequency. Energy is stored in the 330H inductor when the switching transistor is turned on and is released into the 1.0F capacitor when the switch is in the off state. A high voltage DC will develop at VPP which is internally connected to the level translator.
Level translation of the ringing frequency The ringing frequency is set by a 30M resistor. A low voltage square wave is generated with a nominal frequency of 25Hz. Lower ringing frequencies can be obtained by using resistors greater than 30M. The signal is then level translated to swing from 0V to the VPP voltage. An inverted and a noninverted output are generated (gate and gate bar). Enable/Disable function The HV421 can be enabled by connecting the 1.3M and 30M resistors to the same potential as VDD and disabled by connecting them to ground. External source follower buffer stage The gate and gate bar are connected to an external source follower stage. Supertex transistors VP2110K1 and VN2110K1 are used for the buffering. Zener diodes clamps across the gates are recommended as a precaution but not required. The voltage seen by the load is 60V. A 6.8K resistor in series with an 8.0F capacitor is used to simulate 1 North American REN (ringer equivalent number). The main specifications for the Supertex source follower transistors are listed below.
LETE - OBSO -
Device VN2110 VP2110 Type N-Channel P-Channel Breakdown Voltage, BVDSS 100V -100V Gate Threshold Voltage, VGS(th) 0.8V to 2.4V -1.5V to -3.5V
On-Resistance, RDS(ON) 6.0 at VGS=5V 11 at VGS=-5V
Package Options TO-92, SOT-23 TO-92, SOT-23
11-4
HV430
Advanced Information
High-Voltage Ring Generator
Ordering Information
Operating Voltage VPP1 - VNN1 325V Package Options SOW-20 HV430WG
Features
100VRMS ring signal Output over current protection 5.0V CMOS logic control Logic enable/disable to save power Fault output for over-current and low voltage lockout conditions Adjustable deadband in single-control mode Power-on reset for hot-swap protection Low voltage lockout
General Description
The Supertex HV430 is a high voltage PWM ring generator integrated circuit. The high voltage outputs, Pgate and Ngate, are used to drive the gates of external high voltage P-channel, TP2640, and N-channel, TN2640, MOSFETs in a push-pull configuration. Pulse by pulse over current protection are implemented on both the P-channel and N-channel MOSFETs. The RESET inputs functions as a power-on reset and as a low voltage lockout, allowing for hot-swapping capabilities. The FAULT output indicates over-current and low voltage lockout conditions. It is active-low and open-drain to allow wire OR'ing of multiple drivers. PGATE and NGATE are controlled independently by logic inputs Pin and Nin when the mode pin is at logic high. A logic high on Pin will turn on the external P-channel MOSFET. Similarly, a logic high on Nin will turn on the external N-channel MOSFET. Lockout circuitry prevents the N and P switches from turning on simultaneously. For applications where a single control input is desired, the mode pin should be connected to Gnd. The PWM control signal is then input to the Nin pin. A user-adjustable deadband in the control logic assures break-before-make on the outputs, thus avoiding cross conduction on the high voltage output during switching. A logic high on Nin will turn the external P-Channel MOSFET on and the N-Channel off, and vice versa. The IC can be powered down by applying a logic low on the Enable pin, placing both external MOSFETs in the off state.
11
Applications
High voltage ring generator Set-top/Street box ring generator
Absolute Maximum Ratings
VPP1 - VNN1, power supply voltage VPP1, positive high voltage supply VPP2, positive gate voltage supply VNN1, negative high voltage supply VNN2, negative gate voltage supply VDD, logic supply Storage temperature Power dissipation +340V +220V +220V -220V -220V +7.5V -65C to +150C 800mW 11-5


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