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W99688CBM3 Data Sheet SYSTEM CAMERA DEVICE
Table of Contents1. 2. 3. 4. GENERAL DESCRIPTION ......................................................................................................... 2 FEATURES ................................................................................................................................. 2 APPLICATION ............................................................................................................................ 4 3.1 4.1 4.2 4.3 5. 5.1 5.2 6. 6.1 6.2 6.3 6.4 System Camera Device .................................................................................................. 4 Pin Definition (100 balls, LFBGA Package).................................................................... 5 Pin Assignment - Top View.......................................................................................... 10 Power-On Reset Initialization ....................................................................................... 11 Operation Modes .......................................................................................................... 13 Address Mapping.......................................................................................................... 13 Absolute Maximum Ratings .......................................................................................... 14 DC Characteristics........................................................................................................ 14 DAC DC Characteristics ............................................................................................... 15 AC Characteristics ........................................................................................................ 16
6.4.1 6.4.2 USB Transceiver AC Characteristics..............................................................................16 RESET Timing AC Characteristics .................................................................................17
PIN DESCRIPTION..................................................................................................................... 5
SYSTEM OVERVIEW ............................................................................................................... 12
ELECTRICAL CHARACTERISTICS......................................................................................... 14
7. 8.
PACKAGE DIMENSION ........................................................................................................... 18 REVISION HISTORY ................................................................................................................ 19
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Publication Release Date: December 17, 2003 Revision A1
W99688CBM3
1. GENERAL DESCRIPTION
W99688CBM3 is system camera device which built-in 1Mx16bit SDRAM and 128Kbyte Flash ROM. The W99688CBM3 also is a high performance and highly-integrated system camera device that it can preview, capture, compress, store, and display the digital still images or playback a short period of live video. In addition to transfer image data, the W99688 allows to download the programs of micro controller through the USB to update the external flash program ROM, which allows for end users with firmware upgrades through the Internet. W99688 supports CMOS image sensors with high performance DSP functions including missing color interpolation, AE (Auto Exposure), AWB (Auto White Balance), Gamma Correction, edge enhancement, contrast stretching, hue and saturation adjusting etc. W99688 has built-in the baseline JPEG codec for image compression and decompression, which corresponds to the ISO/IEC international standard 10918-1, with YCbCr4:2:2 or YCbCr4:2:0 components in interleaved scan. W99688 also supports the Exchangeable Image File format (EXIF) to ensure data compatibility and exchangeability. W99688 includes an 8032 compatible CPU core, a 6K-byte SRAM and two 16-bit programmable timers. It also provides the In-System-Programming (ISP) function to let users to update the firmware for external flash ROM. W99688 also supports a digital display output to directly interface with TFT-LCD, CSTN-LCD or other display device.
2. FEATURES
Sensor Interface * Direct connect to CMOS image sensor: - CMOS Image Sensor:OmniVision, IC-Media , tasc , PixArt and Motorola ........etc. * Supports real-time video resolutions up to 640X480 and still image resolutions up to 2048X2048 * High performance Sensor DSP functions (includes black level compensation, color Interpolation, false color suppression, edge enhancement, color correction, gamma correction, AEC, AWB, contrast stretching, hue and saturation adjusting) * Supports universal serial interface to program CMOS image sensor. User Interface * Built-in 8-bits 8032 compatible uC with internal 6K bytes data RAM and 128K bytes Flash ROM * Supports In-System-Programming (ISP) function for external flash ROM through USB to the internal program flash-ROM * uC can directly access the frame buffer through bank switching. Host Interface * 8/16 bits parallel Bus (Indirect access) JPEG CODEC for Image Compression and Decompression * Fully compliant with ISO/IEC 10918-1 international JPEG standard
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W99688CBM3
* JPEG compression and decompression for still images * Real-time motion JPEG (MJPEG) compression with advanced bit rate control for live video * JPEG baseline sequential mode in interleaved scan YCbCr4:2:2 or YCbCr4:2:0 format * Three programmable quantization tables for image/video quality control and bit-rate control. * Support Exchangeable Image File format (EXIF). Display Interface * Supports OSD function to display the user interface message on LCD screen * Supports a digital display output to directly interface with TFT-LCD or other display device, like electric - view finder * Supports the C-STN LCD which have the MCU interface and display data memory Power Management * Advanced power management including Power-down, Stand-by, and Operating modes. Engines are only active when they are needed Operation Modes * Preview ModeFrame rate up to 30 fps * Single Snapshot Mode * Burst Snapshot Mode - Support up to 10 frames burst snapshot at 1/30 sec interval * * * * Movie Mode (Motion JPEG) - About 15 seconds recording time with 800K bytes vedio buffer at 160x120 size @ 15 fps Playback Mode Transfer Mode Still Image Size - 640x480 (VGA) - 320x240 (QVGA) - 160x120 (QQVGA) - Subject to change by request Video Clip Size - 160x120 (QQVGA) - Subject to change by request Built-in Two PLL (Phase-Locked Loops) Clock Synthesizers 5V Core, 3.3V I/O, 5 V Input Tolerant Built-in 2Mbyte frame buffer and 128Kbyte Flash ROM. Command set: Easy for base band chip( Host ) develop Camera function through Command set protocol. Package: 10mmx10mm, 100-balls LFBGA package for fully function
*
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Publication Release Date: December 17, 2003 Revision A1
W99688CBM3
3. APPLICATION
3.1 System Camera Device
RGB/YUV CMOS Sensor
W99688CBM3 Camera Module
W99688CBM3 YUV USB
CCD Sensor
USB Interface
Parallel Interface
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W99688CBM3
4. PIN DESCRIPTION
4.1 Pin Definition (100 balls, LFBGA Package)
The following signal types are used in these descriptions. I IS B BR BU O A P G # Input pin Input pin with Schmitt trigger Bi-directional input/output pin Bi-directional input/output pin with repeater Bi-directional input/output pin with internal pull-up Output pin Analog input/output pin Power supply pin Ground pin Active low
USB Interface (2 pins) PIN NAME DP PIN NUMBER E3 TYPE A DESCRIPTION Data Plus line of differential USB upstream port. Note: provide an external 1.5 K pull-up resistor at DP so the device indicates to the host that it is a full-speed device. DM E2 A Data Minus line of differential USB upstream port.
POWER ON SETTING (1 pins) PIN NAME MD1 PIN NUMBER L4 TYPE BU ISP mode ON/OFF, DESCRIPTION Default pull up ISP is off
Sensor or Video Input Interface (17 pins) PIN NAME SVID[9:0] PIN NUMBER F11, F9, K4, G11, G9, G10, H10, H11, J5, D9 F10 J4 K3 E10 H4 E9 D9 TYPE I DESCRIPTION Sensor or Video Data Input SVID[9:0].
SPCLK SVS SHS SCLK SCK SDI/SDA SDO/SDE
I B B O B B B
Clock for Sensor or Video Data Input Vertical Sync Input. Programmable polarity. Horizontal Sync Input. Programmable polarity. Clock Output to Sensor Serial Interface Clock Serial Interface Data Input/ Serial Data Acknowledge Serial Interface Data Output / Serial Data Enable
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Publication Release Date: December 17, 2003 Revision A1
W99688CBM3
LCD Digital Display Interface (13 pins) PIN NAME DCLK / DFULL DDE / DVALID / DA0 DOCLK / DDCLK / DCS# DHSYNC / DXCLK / DWR# DVSYNC / FS / DRD# DDATA [7:0] J8, K9, K8, J7, K7, L8, K5, L9 O L11 O K11 O K10 O J9 O PIN NUMBER L10 TYPE I DESCRIPTION Clock Input for Display Controller Reflective Display Module: Full LCD: Data Enable Reflective Display Module: Data Valid M-LCD: Address-0, for LCD Controller RS signal (CMD/DAT#) Clock for Digital Display Data Output Reflective Display Module: Data Clock M-LCD: LCD Chip Select Horizontal Sync Reflective Display Module: Display Clock M-LCD: Write Enable Vertical Sync Reflective Display Module: Frame Start M-LCD: Read Enable Digital Display Output Data 8 bits
Flash Memory Host Interface (20 pins) PIN NAME FWAIT# FCD# FRESET FSCS0# / FA0 FSCS1# / FA1 FSCS2# / FA2 FSR/B# / FRDY/BSY# FWP FSRE# / FIORD# B10 BU A10 BU PIN NUMBER J3 K2 D10 B11 D8 A11 TYPE BU BU BR BR BR BR DESCRIPTION Compact Flash: WAIT# Signal Compact Flash: Card Inserted Detect Compact Flash: RESET/RESET# Signal Smart Media: Chip-0 Enable Compact Flash: Address-0 Smart Media: Chip-1 Enable Compact Flash: Address-1 Smart Media: Chip-2 Enable Compact Flash: Address-2 Smart Media: Ready/Busy Compact Flash: Ready Signal SD: Host to detect card's write protect switch is enable Smart Media: Read Enable Compact Flash: I/O Read Strobe
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W99688CBM3
Flash Memory Host Interface (20 pins), continued
PIN NAME FSWE# / FIOWR# / FCMD FSCLE / FCE2# / XCLK FSALE / FCE1# / XCMD FSWP# / FREG# / FCLK FD [3:0] / FDAT [3:0] FD [7:4] / XDAT [3:0]
PIN NUMBER B9
TYPE BU
DESCRIPTION Smart Media: Write Enable Compact Flash: I/O Write Strobe SD: Master CMD Smart Media: Command Latch Enable
C8
BR
Compact Flash: Chip Select Signal - 2 SD: Slave CLK Smart Media: Address Latch Enable
C9
BR
Compact Flash: Chip Select Signal - 1 SD: Slave CMD Smart Media: Write Protect
A9
BR
Compact Flash: Register (Attribute) Memory Access SD: Master CLK Smart Media & Compact Flash: Data Bus FD[3:0] SD: SD Master DAT [3:0] Smart Media & Compact Flash: Data Bus FD[7:4] XD: SD Slave DAT [3:0]
J2, B8, C7, H3 D4, B7, C6, A8
BR BR
Compact Flash-IDE lite "Device" Interface (20 pins) PIN NAME XWAIT# XCD# POR XRESET XA[2: 0] XRDY / XBSY# XIORD# XIOWR# XCE[2: 1]# XCS[1: 0]# XREG# XD[7:0] PIN NUMBER J3 K2 D10 A11, D8, B11 A10 B10 B9 C8, C9 A9 D4, B7,C6, A8, J2, B8, C7, H3 TYPE BU BU BR BR BU BU BU BR BR BR DESCRIPTION Compact Flash: WAIT Signal Compact Flash: Card Insert Detect (A Low level signal Output) SD: Power-On Reset (Implement For No Powered Device) Compact Flash: Card Reset Compact Flash: Address [2:0] Compact Flash: Ready Signal Compact Flash: I/O Read Strobe Compact Flash: I/O Write Strobe Compact Flash: Card Enable [2:1] Compact Flash: IDE Mode, Chip Select [1:0]
Compact Flash: Register (Attribute) Memory Access Select Compact Flash: Data Bus 16 Bits
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Publication Release Date: December 17, 2003 Revision A1
W99688CBM3
GPIO and Miscellaneous (21pins) PIN NAME GPIO[0] / PCLK-A GPIO[1] / PCLK-B GPIO[3] GPIO[10] / HCLK / XCLK GPIO[11] / HCMD / XCMD GPIO[15:12] / HDAT[3:0] / XDAT[3:0] XIN XOUT RST C4 A6 B3 I O IS B1, C2, B2, D3 BU A1 BU C3 BU PIN NUMBER B6 A5 L6 TYPE BU BU BU PCLK-A Output General Purpose I/O [1] PCLK-B Output General Purpose I/O [3] General Purpose I/O [10] HCLK for SD 2nd Host Interface Alternate Slave SD Device CLK signal General Purpose I/O [11] HCMD for SD 2nd Host Interface Alternate Slave SD Device CMD signal General Purpose I/O [15:12] HDAT[3:0] for SD 2nd Host Interface Alternate Slave SD Device XD[3:0] Reference frequency input from ext. crystal or a clock source. Oscillator output to a crystal. This pin is left unconnected if an external clock source is employed. Reset In. This pin is active high to reset W99688 chip. DESCRIPTION General Purpose I/O [0]
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W99688CBM3
Power and Ground (33 pins) PIN NAME VDDB PIN NUMBER D11, J6, L2, J1, G2, C1, A3, A7, C10 E11, J10, L7, L3, L1, H1, D2, A2, C5, C11 J11, L5, G1 H8, K1, K2 B4 A4 E1 D1 F3 G3 B5 K6 TYPE P DESCRIPTION I/O Pad Buffer Power Supply. Provide isolated power to the I/O buffers for improved noise immunity. +3.3V 0.3V. I/O Pad Buffer Ground. Internal Core Logic Power Supply. +2.5V 0.25V. Internal Core Logic Ground. PLL Power Supply. PLL Ground. USB Power Supply. +3.3V 0.3V. USB Ground. Embedded SDRAM Ground-1. Embedded SDRAM Power Supply-1. +3.3V 0.3V. Embedded Flash ROM Ground. Embedded Flash ROM Power Supply. +3.3V 0.3V. +2.5V 0.25V.
VSSB (GND) VDDI VSSI AVDDP AVSSP USBVDD USBVSS GND-D VD33-D GND-F VD33-F
G P G P G P G G P G P
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Publication Release Date: December 17, 2003 Revision A1
W99688CBM3
4.2 Pin Assignment - Top View
A1 CORNER 1 A
GPIO11 /SPI_ CMD
2
GND-3
3
VD33-3
4
AVSSP
5
GPIO1
6
XOUT
7
VD33-2
8
FD4
9
FREG#
10
FIRQ /FRB#
11
FA2
B
GPIO15 /DAT3 /SPI_ CS#
GPIO13 /DAT1
RESET
AVDDP
GND-F
GPIO0
FD6
FD2
FIOWR#
FIORD#
FA0
C
VD33-4
GPIO14 /DAT2
GPIO10 /SPI_ CLK
XIN
GND-2
FD5
FD1
FCE2#
FCE1#
VD33-1
GND-1
D
USBVSS
GND-4
GPIO12 /DAT0 /GPIO2
FD7
FA1
SDO
FRST
VD33-9
E
USBVDD
DM
DP
SDA
SCLK
GND-10
F
P31
P30
GND-D
SD8
SPCLK
SD9
G
VD25-1
VD33-5
VD33-D
SD5
SD4
SD6
H
GND-5
GND25-1
FD0
SCK
GND25-3
SD0
SD3
SD2
J
VD33-6
FD3
FWAIT#
SVS
SD1
VD33-8
DD4
DD7
DVALID
GND-9
VD25-3
K
GND25-2
FCD#
SHS
SD7
DD1
VD33-F
DD3
DD5
DD6
DOCLK
DHS
L
GND-6
VD33-7
GND-7
MD1
VD25-2
GPIO3
GND-8
DD2
DD0
DFULL
DVS
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W99688CBM3
4.3 Power-On Reset Initialization
During power-on reset, the states of MD[15:0]] are latched into the W99688s internal configuration registers (CR0000 and CR0001) as device configuration information. Since each pin of MD[15:0] has internally pulled-up. If the application needs to set the configuration to "0", some proper pull-down resistors must be added into some pins of MD[15:0]. Table 4.2 describes the power-on reset configuration definitions. Power-on Reset Configuration Definitions PINS MD1 VALUE 0 1 DEFINITION Disable internal 4KB ROM (EA# = 0) Enable internal 4KB ROM (EA# = 1) CONT'L REG CR0000_1
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Publication Release Date: December 17, 2003 Revision A1
W99688CBM3
5. SYSTEM OVERVIEW
W99688CBM3
Frame
Memory
(SDRAM 1Mx16)
Lens
CMOS Sensor YUV
Data
Image
Control
W99688
Single Chip Image Processor
Memory bus / SPI
uC F/W Flash ROM 128KB
Figure 5.1
W99688 Based DSC System Diagram
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W99688CBM3
5.1 Operation Modes
The W99688 provides seven operation modes: * * * * Real-time capture and display the images (video) on the LCD (W99688 Only). Record Mode Capture/compress/store a still image (or video) on flash memory or SDRAM Playback Mode Restore/decompress/display the stored images (single-image or thumbnails) on the LCD. Power Down System enters power down mode to reduce the power consumption. It can be waked up from power down mode by reset or INT1_ event. Preview Mode
5.2 Address Mapping
INDEX 1 1 1 1 2 C ADDRESS 0000H - 7FFFH 8000H - 97FFH A000H - A20FH A400H - A60FH B000H - B6FFH 6KBytes Data RAM 528Bytes Flash Memory Buffer-1 528Bytes Flash Memory Buffer-2 Control and Status Registers DESCRIPTION Mapping to Frame Buffer SDRAM or SRAM
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Publication Release Date: December 17, 2003 Revision A1
W99688CBM3
6. ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings
PARAMETER Ambient temperature Storage temperature DC supply voltage (2.5V) DC supply voltage (3.3V) I/O pin voltage with respect to VSS Table 6- 1 MIN. 0 -40 0 0 - 0.3 MAX. 70 125 3.5 4.6 5.25 UNIT C C V V V
6.2 DC Characteristics
SYMBOL VDDB USBVDD DACVDDB PARAMETER Power Supply for I/O Pads POWER SUPPLY FOR USB TRANSCEIVER Power Supply for DAC Output Power Supply for DAC Internal Circuit Power Supply for PLL Analog Power Supply for Core Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Leakage Current Input High Leakage Current Pull-up Current Power Down Current Active Current Table 6- 2 IOUT = 2 mA IOUT = -2 mA VIN = 0.4V VIN = 2.4V VIN = 0V 2.4 10 -10 -500 TBD TBD CONDITIONS MIN. 3.0 3.0 3.0 3.0 2.25 2.25 2.25 0 2.0 MAX. 3.6 3.6 3.6 3.6 2.75 2.75 2.75 0.8 5.25 VSS +0.4 UNIT V V V V V V V V V V V A A A A mA
DACVDDYC Power Supply for DAC Output DACVDDI AVDDP VDDI VIL VIH VOL VOH IIL IIH IUP IPD IDD
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W99688CBM3
6.3 DAC DC Characteristics
PARAMETER Integral Linearity Error Differential Linearity Error Gray Scale Error LSB Size DAC-to-DAC Matching Output Compliance Gray Scale Current Range Output Impedance Output Capacitance (f = 1 MHz; IOUT = 0 mA) Monotonicity Internal VREF Power Supply Reject Ratio (f = 1 KHz) Table 6- 3
Note 1. Measured with VREF = 1.235 V, RSET = 386 . RL = 37.5 .
MIN.
TYP. 0.5 0.5 33.28 2
MAX. 2 1 TBD 5
UNIT LSB LSB %Gray A % V mA
0 2.0
1.278 34.08 TBD TBD
pF Guaranteed V %
1.230
1.265
1.272 TBD
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Publication Release Date: December 17, 2003 Revision A1
W99688CBM3
6.4 AC Characteristics
6.4.1 USB Transceiver AC Characteristics
Rise Time CL Differential Data Lines 90% 10% 90%
Fall Time
10%
CL Full Speed: 4 to 20ns at CL = 50pF
tR
tF
Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF
Figure 6.1
Data Signal Rise and Fall Time
USB Transceiver AC Characteristics SYMBOL TR TF TRFM TDRATE PARAMETER Rise Time Fall Time Rise/Fall Time Matching Full Speed Data Rate Source Differential Driver Jitter TDJ1 TDJ2 TEOPT TDEOP To Next Transition For Paired Transitions Source EOP Width Differential to EOP Transition Skew Receiver Data Jitter Tolerance TJR1 TJR2 TEOPR1 TEOPR2 To Next Transition For Paired Transitions EOP Width at Receiver Must Reject as EOP Must Accept as EOP Table 6.4 40 82 nS nS -18.5 -9 18.5 9 nS nS -3.5 -4.0 160 -2 3.5 4.0 175 5 nS nS nS nS Average bit rate (12 Mb/s 0.25%) CONDITIONS CL = 50 pF CL = 50 pF MIN. 4 4 90 11.97 MAX. 20 20 110 12.03 UNIT nS nS % Mbps
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W99688CBM3
6.4.2 RESET Timing AC Characteristics
RSTI
TRST
Figure 6.2
RESET Timing
RESET Timing SYMBOL TRST PARAMETER Reset Pulse Width Table 6.5 CONDITIONS MIN. 100 MAX. UNIT nS
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Publication Release Date: December 17, 2003 Revision A1
W99688CBM3
7. PACKAGE DIMENSION
100L LFBGA (10x10 mm, Ball pitch: 0.8 mm, O = 0.4 mm)
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W99688CBM3
8. REVISION HISTORY
VERSION A1 DATE Dec. 17, 2003 PAGE Initial Issue DESCRIPTION
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: December 17, 2003 Revision A1

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