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MITSUBISHI LSIs
1997.01.22
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V32R16 is a family of 32768-word by 16-bit static RAMs, fabricated with the high performance CMOS process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as well. In write and read cycles, the lower and upper bytes are able to be controled either togethe or separately by /LB and /UB.
PIN CONFIGURATION (TOP VIEW)
N.C A3 A2 ADDRESS INPUTS A1 A0 CHIP SELECT /S INPUTS DQ1 DATA DQ2 INPUTS/ OUTPUTS DQ3 DQ4 (3.3V) Vcc (0V) GND DQ5 DATA DQ6 INPUTS/ OUTPUTS DQ7 DQ8 WRITE CONTROL /W INPUT A14 A13 ADDRESS INPUTS A12 A11 NC
1 2 3 4 5 6 44 43 42 41 40 39
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
38 35 36 35 34 33 32 31 30 29 28 27 26 25 24 23
FEATURES
Fast access time M5M5V32R16J,TP-10 10ns(max) M5M5V32R16J,TP-12 12ns(max) M5M5V32R16J,TP-15 15ns(max) Low power dissipation Active 297mW(typ) Stand by 0.33mW(typ) Single +3.3V power supply Fully static operation : No clocks, No refresh Common data I/O Easy memory expansion by /S Three-state outputs : OR-tie capability OE prevents data contention in the I/O bus Directly TTL compatible : All inputs and outputs Separate control of lower and upper bytes by /LB and /UB
A4 ADDRESS A5 INPUTS A6 OUTPUT /OE ENABLE BYTE /UB CONTROL /LB INPUTS DQ16 DQ15 DATA INPUTS/ DQ14 OUTPUTS DQ13 GND (0V) Vcc (3.3V) DQ12 DQ11 DATA INPUTS/ DQ10 OUTPUTS DQ9 NC A7 A8 ADDRESS INPUTS A9 A10 NC
M5M5V32R16J,TP
Outline
44P0K(J) 44P3W-H(TP)
APPLICATION
High-speed memory system
PACKAGE
M5M5V32R16J : 44pin 400mil SOJ M5M5V32R16VP: 44pin 400mil TSOP(II)
FUNCTION
The operation mode of the M5M5V32R16 is determined by a combination of the device control inputs /S, /W, /OE, /LB, and /UB. Each mode is summarized in the function table. A write cycle is executed whenever the low level /W overlaps with low level /LB and/or low level /UB and low level /S. The address must be set-up before write cycle and must be stable during the entire cycle. The data is latched into a cell on the traling edge of /W, /LB, /UB or /S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input /OE directly controls the output stage. Setting the /OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and /OE at a low level while /LB and/or /UB and /S are in an active state. (/LB and/or /UB=L, /S=L) When setting /LB at a high level and other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enable, and lower-Byte are in a non-selectable mode. And when setting /UB at a high level and other pins are in an active state, lower-Byte are in a selectable mode in which both reading and writing are enable, and upper-Byte are in a non-selectable mode. When setting /LB and /UB at a high level or /S at high level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by /LB, /UB and /S. Signal-/S controls the power-down feature. When /S goes high, power dissapation is reduced extremely. The access time from /S is equivalent to the address access time.
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MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION TABLE
/S L L L L L L L L H /W H H H L L L H X X /OE /LB /UB L L L X X X H X X L H L L H L X H X L L H L L H X H X Non selection High-impedance High-impedance Stand by Mode Read cycle All Bytes Read cycle Upper Bytes Read cycle Lower Bytes Write cycle All Bytes Write cycle Upper Bytes Write cycle Lower Bytes Output disable DQ1 - 8 D OUT High-impedance D OUT D IN High-impedance D IN High-impedance DQ9 - 16 D OUT D OUT High-impedance D IN D IN High-impedance High-impedance Icc Active Active Active Active Active Active Active
BLOCK DIAGRAM
A7 A6 A2 A1 A0 A14 A13 A12 A11 27 42 3 4 5 18 19 20 21 ROW INPUT BUFFERS 7 8 9 10 13 14 15 16 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
ROW ADDRESS DECODERS
ADDRESS INPUTS
MEMORY ARRAY 512 ROWS 1024 COLUMNS
CHIP SELECT INPUTS WRITE CONTROL INPUT
/S
6 COLUMN I/O CIRCUITS
/W 17 OUTPUT BUFFERS
DATA INPUT BUFFERS
OUTPUT BUFFERS
OUTPUT ENABLE INPUT
/OE 41
COLUMN ADDRESS DECODERS
29 30 31 32 35 36 37 38 11 33 12 34
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16
DATA INPUT BUFFERS
UPPER BYTE CONTROL INPUTS
/UB 40
COLUMN INPUT BUFFERS
Vcc GND
LOWER BYTE CONTROL INPUTS
/LB 39 24 25 26 43 44 2 A10 A9 A8 A5 A4 A3 ADDRESS INPUTS
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MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI VO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Ta=25 C With respect to GND Conditions Ratings -2.0* ~ 4.6 -2.0* ~ Vcc+0.5 -2.0* ~ Vcc 1000 0 ~ 70 -10 ~ 85 -65 ~ 150
+10% - 5%,
Unit V V V mW C C C
Tstg(bias) Storage temperature(bias) Storage temperature * Pulse width < 20ns, In case of DC: - 0.5V =
DC ELECTRICAL CHARACTERISTICS
Symbol VIH VIL VOH VOL II IOZ Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Output current in off-state Active supply current (TTL level)
(Ta=0 ~ 70 C , Vcc=3.3V Condition
unless otherwise noted) Min 2.0 -0.3* 2.4 Limits Typ Max Vcc+0.3 0.8 0.4 2 10 Unit V V V V A A
IOH = - 4mA IOL= 8mA V I = 0 ~ Vcc VI (/S)= VIH VO= 0 ~ Vcc VI (/S)= VIL other inputs VIH or VIL Output-open(duty 100%) AC(10ns cycle) AC(12ns cycle) AC(15ns cycle) DC AC(10ns cycle) AC(12ns cycle) AC(15ns cycle) DC
I CC1
90
I CC2
Stand-by supply current (TTL level) Stand-by current (MOS level)
VI (/S)= VIH > VI (/S)= Vcc= 0.2V other inputs VI < 0.2V = > or VI = Vcc - 0.2V
+10% - 5% ,
150 130 110 100 60 55 50 40 1
mA
mA
I CC3
0.1
mA
* Pulse width < 20ns, in case of AC : - 3.0V =
CAPACITANCE (Ta=0 ~ 70
Symbol
C, Vcc=3.3V
unless otherwise noted) Test Condition Min Limit Typ Max 6 8 Unit pF pF
Parameter
CI Input capacitance VI =GND,Vi =25mVrms,f=1MHz CO Output capacitance Vo =GND,Vo =25mVrms,f=1MHz Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is Vcc=3.3V,Ta=25 C 3: CI,CO are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C , Vcc=3.3V +10%, unless otherwise noted) - 5%
(1) MEASUREMENT CONDITION
Input pulse levels Input rise and fall time Input timing reference levels Output timing reference levels Output loads VIH =3.0V, V IL =0.0V 3ns V IH =1.5V, VIL =1.5V V OH =1.5V, V OL =1.5V Fig1,Fig2
(Including JIG ) scope and
DQ 50 VL=1.5V Fig.1 Output load DQ 255
Vcc 480
(
5pF Including scope and JIG
)
Fig.2 Output load for ten , tdis
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MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
READ CYCLE
Symbol Parameter
Limits M5M5V32R16 -10 M5M5V32R16 -12 M5M5V32R16 -15 Unit Min 10 Max 10 10 5 5 5 5 5 Min 12 Max 12 12 6 6 6 6 6 Min 15 Max 15 15 7 7 7 7 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCR ta (A) ta (S) ta (OE) ta (B) tdis (S) tdis (OE) tdis (B) ten (S) ten (OE) ten (B) tv (A) tPU tPD
Read cycle time Address access time Chip select access time Output enable access time /LB,/UB access time Output disable time after /S high Output disable time after /OE high Output disable time after /LB,/UB high Output enable time after /S low Output enable time after /OE low Output enable time after /LB,/UB low Data valid time after address change Power-up time after chip selection Power down time after chip selection
0 0 0 4 3 3 0
0 0 0 4 3 3 0
0 0 0 4 3 3 0
4 10
4 12
4 15
Write cycle
Limits
Symbol Parameter
tCW tw(W) tsu (B) tsu(A)1 tsu(A)2 tsu (S) tsu(D) th(D) trec(W) tdis (W) tdis (OE) ten (W) ten (OE) ten (B) tsu(A-WH) tsu(A-SH) tsu (A-BH)
Write cycle time Write pulse width /LB,/UB setup time Address setup time(/W) Address setup time(/S) Chip select setup time Data setup time Data hold time Write recovery time Output disable time after /W low Output disable time after /OE high Output enable time after /W high Output enable time after /OE low Output enable time after /LB,/UB low Address to /W High Address to /S High Address to /LB,/UB High
M5M5V32R16 -10 M5M5V32R16 -12 M5M5V32R16 -15 Unit Min Max Min Max Min Max 10 12 15 ns 9 10 12 ns 10 12 ns 9 0 0 0 ns 0 0 0 ns 9 10 12 ns 5 6 7 ns 0 0 ns 0 0 0 ns 0 0 6 0 7 ns 0 5 0 6 0 7 ns 0 5 0 0 ns 0 0 0 ns 0 0 0 ns 0 10 12 ns 9 10 12 ns 9 10 12 ns 9
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MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS Read cycle 1 A 0~14
VIH VIL
t CR
ta (A) tv (A) tv (A)
UNKNOWN DATA VALID PREVIOUS DATA VALID
DQ1~16
VOH VOL /W=H /S=L
/LB=L /UB=L
/OE=L
Read cycle 2 (Note 4)
t
CR
/S
VIH VIL
ta (S) ten (S)
(Note 5)
tdis(S)
(Note 5)
DQ1~16
VOH VOL
UNKNOWN
DATA VALID
tPU
tPD
50% 50%
Icc
ICC1 ICC2 /W=H /UB=L
/OE=L /LB=L
Note 4. Addresses valid prior to or coincident with /S transition low. 5. Transition is measured 500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 6) /OE
VIH VIL
t
CR
ta(OE)
(Note 5)
tdis(OE)
(Note 5)
ten (OE)
UNKNOWN DATA VALID
DQ1~16
VOH VOL /W=H /UB=L /S=L /LB=L
Note 6. Addresses and /S valid prior to /OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
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MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
Read cycle 4 (Note 7) /UB,/LB
VIH VIL
t CR
(Note 5)
ta (B)
(Note 5)
tdis (B)
ten (B)
UNKNOWN DATA VALID
DQ1~16
VOH VOL /W=H /OE=L /S=L
Note 7. Addresses , /S and /OE valid prior to /LB,/UB transition low by (ta(A)-ta(B)), (ta(S)-ta(B)), (ta(OE)-ta(B)).
Write cycle (/W control mode)
t CW
A 0~14 /S
VIH VIL VIH VIL (Note8)
tsu (S)
(Note8)
tsu (A-WH)
/OE
VIH VIL
tsu (A)
tw (W)
trec (W)
/W
VIH VIL
tsu (B)
/LB,/UB
VIH VIL
(Note8)
(Note8)
tdis (OE)
tsu (D) th (D)
DATA STABLE
DQ1~16
(Input Data)
VIH VIL
tdis (W) tdis (OE)
(Note 5)
ten (OE) ten (W)
Hi-Z
(Note 5)
DQ1~16
(Output Data)
VOH VOL
Note 8: Hatching indicates the state is don't care. 9: When the falling edge of /W is simultaneous or prior to the falling edge of /S, the output is maintained in the high impedance. 10: ten,tdis are periodically sampled and are not 100% tested.
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MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle(/S control)
t CW
A 0~14
VIH VIL
tsu (A)
tsu (S)
trec (W)
/S /W
VIH VIL
tw (W)
VIH VIL (Note7) (Note7)
tsu (B)
/LB,/UB
VIH VIL (Note7) (Note7)
tsu (D)
th (D)
DQ1~16
(Input Data)
VIH VIL
(Note5)
DATA STABLE
tdis (W)
(Note5)
DQ1~16
(Output Data)
VOH VOL
ten (S)
Hi-Z
(Note9)
Write cycle(/LB,/UB control)
t CW
A 0~14
VIH VIL
tsu (S)
/S /W
VIH VIL (Note7) VIH VIL (Note7) (Note7)
tw (W)
(Note7)
tsu (A)
tsu (B)
trec (W)
/LB,/UB
VIH VIL
tsu (D)
th (D)
DQ1~16
(iInput Data)
VIH VIL
(Note5)
DATA STABLE
tdis (W)
(Note5)
DQ1~16
(Output Data)
VOH VOL
ten (B)
Hi-Z
(Note9)
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MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
'96.11.20
P3
Vref --> 5.0V
k.kubo
'97.01.22
P3
Output loads=50
k.kubo
'97.02.04
P3
Vref --> Vcc
k.kubo
MITSUBISHI ELECTRIC

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