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IS61LP6432A IS61LP6436A
64K x 32, 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM
FEATURES
* Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * PentiumTM or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Common data inputs and data outputs * JEDEC 100-Pin TQFP package * Power-down snooze mode * Power Supply: +3.3V VDD +3.3V or 2.5V VDDQ (I/O) * Lead-free available
ISSI
SEPTEMBER 2005
(R)
DESCRIPTION The ISSI IS61LP6432A/36A is a high-speed synchronous
static RAM designed to provide a burstable, high-performance memory for high speed networking and communication applications. The IS61LP6432A is organized as 64K words by 32 bits and the IS61LP6436A is organized as 64K words by 36 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, highspeed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -166 3.5 6 166 -133 4 7.5 133 Units ns ns MHz
Copyright (c) 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
1
IS61LP6432A IS61LP6436A
BLOCK DIAGRAM
MODE Q0 A0'
ISSI
CLK A0
(R)
CLK
BINARY COUNTER
ADV ADSC ADSP CE CLR Q1 A1' A1
64K x 32 64K x 36 MEMORY ARRAY
14 16
A15-A0
16
D
Q
ADDRESS REGISTER
CE CLK x32/x36 x32/x36
GW BWE BW4
DQd BYTE WRITE REGISTERS
CLK
D
Q
BW3
D DQc Q BYTE WRITE REGISTERS CLK
BW2
DQb BYTE WRITE REGISTERS
CLK
D
Q
BW1
D DQa Q BYTE WRITE REGISTERS CLK
CE CE2 CE2 D Q
4
ENABLE REGISTER
CE CLK
INPUT REGISTERS
CLK
OUTPUT REGISTERS
CLK
x32/x36 OE DQ[31:0] DQ[35:0]
D
Q
ENABLE DELAY REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
IS61LP6432A IS61LP6436A
PIN CONFIGURATION
100-Pin TQFP
A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9
ISSI
(R)
DQPc DQc1 DQc2 VDDQ VSS DQc3 DQc4 DQc5 DQc6 VSS VDDQ DQc7 DQc8 NC VDD NC VSS DQd1 DQd2 VDDQ VSS DQd3 DQd4 DQd5 DQd6 VSS VDDQ DQd7 DQd8 DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb DQb8 DQb7 VDDQ VSS DQb6 DQb5 DQb4 DQb3 VSS VDDQ DQb2 DQb1 VSS NC VDD ZZ DQa8 DQa7 VDDQ VSS DQa6 DQa5 DQa4 DQa3 VSS VDDQ DQa2 DQa1 DQPa
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW CE, CE2, CE2 OE DQa-DQd MODE VDD Vss VDDQ ZZ DQPa-DQPd Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable Parity Data I/O
A2-A15 CLK ADSP ADSC ADV BW1-BW4 BWE
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
MODE A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 NC
64K x 36
3
IS61LP6432A IS61LP6436A
PIN CONFIGURATION
100-Pin TQFP
A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9
ISSI
(R)
NC DQc1 DQc2 VDDQ VSS DQc3 DQc4 DQc5 DQc6 VSS VDDQ DQc7 DQc8 NC VDD NC VSS DQd1 DQd2 VDDQ VSS DQd3 DQd4 DQd5 DQd6 VSS VDDQ DQd7 DQd8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC DQb8 DQb7 VDDQ VSS DQb6 DQb5 DQb4 DQb3 VSS VDDQ DQb2 DQb1 VSS NC VDD ZZ DQa8 DQa7 VDDQ VSS DQa6 DQa5 DQa4 DQa3 VSS VDDQ DQa2 DQa1 NC
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW CE, CE2, CE2 OE DQa-DQd MODE VDD Vss VDDQ ZZ Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable
A2-A15 CLK ADSP ADSC ADV BW1-BW4 BWE
MODE A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 NC
64K x 32
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
IS61LP6432A IS61LP6436A
TRUTH TABLE
Operation Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L X X L L L X X H H X H X X H H X H CE2 X X L X L H H H X X X X X X X X X X X X CE2 X H X H X L L L X X X X X X X X X X X X ADSP ADSC X L L X L X H L H L L X H L H L H H H H X H X H H H X H H H H H X H X H H H X H ADV WRITE X X X X X X X X X X X X X Read X Write L Read L Read L Read L Read L Write L Write H Read H Read H Read H Read H Write H Write
ISSI
OE X X X X X X X X L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z Q Q D Q High-Z Q High-Z D D Q High-Z Q High-Z D D
(R)
PARTIAL TRUTH TABLE
Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BW1 X H L L X BW2 X H H L X BW3 X H H L X BW4 X H H L X
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
5
IS61LP6432A IS61LP6436A
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00
ISSI
(R)
LINEAR BURST ADDRESS TABLE (MODE = Vss)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TSTG PD IOUT VIN, VOUT VIN VDD Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to Vss for I/O Pins Voltage Relative to Vss for for Address and Control Inputs Voltage on VDD Supply Relative to Vss Value -55 to +150 1.6 100 -0.5 to VDDQ + 0.3 -0.5 to VDD + 0.5 -0.5 to 4.6 Unit C W mA V V V
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
IS61LP6432A IS61LP6436A
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V + 5% 3.3V + 5% VDDQ 3.3V + 5% 2.5V + 5% 3.3V + 5% 2.5V + 5%
ISSI
(R)
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Vss VIN VDD
(1)
Test Conditions IOH = -4.0 mA (3.3V) IOH = 1.0 mA (2.5V) IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V)
2.5V (I/O) Min. Max. 2.0 -- 1.7 -0.3 -5 -5 -- 0.4 VDD + 0.3 0.7 5 5
3.3V (I/O) Min. Max. 2.4 -- 2.0 -0.3 -5 -5 -- 0.4 VDD + 0.3 0.8 5 5
Unit V V V V A A
Vss VOUT VDDQ, OE = VI
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-166 Max. 190 200 -133 Max. 180 190
Symbol ICC
Parameter AC Operating Supply Current
ISB1
Standby Current
IZZ
Power-down Mode Current
Test Conditions Device Selected, Com. All Inputs = VIL or VIH Ind. OE = VIH, VDD = Max. Cycle Time tKC min. Device Deselected, Com. VDD = Max., Ind. All Inputs = VIH or VIL CLK Cycle Time tKC min. ZZ = VDD Com. Clock Running Ind. All Inputs VSS + 0.2V or VDD - 0.2V
Unit mA mA
70 80
70 80
mA mA
35 40
35 40
mA mA
Notes: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to Vss, or tied to VDD. 2. The MODE pin should be tied to VDD or Vss. It exhibits 10 A maximum leakage current when tied to Vss + 0.2V or VDD - 0.2V.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
7
IS61LP6432A IS61LP6436A
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
ISSI
(R)
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1ns 1.5V See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317
ZO = 50 OUTPUT
+3.3V
OUTPUT
50
351
5 pF Including jig and scope
1.5V
Figure 1 Figure 2
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
IS61LP6432A IS61LP6436A
2.5V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1 ns 1.25V See Figures 3 and 4
ISSI
(R)
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667
ZO = 50 OUTPUT
+2.5V
OUTPUT
50
1,538
5 pF Including jig and scope
1.25V
Figure 3 Figure 4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
9
IS61LP6432A IS61LP6436A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
ISSI
-133 Max. 166 -- -- -- 3.5 -- -- 3.5 3.5 -- -- 4.5 -- -- -- -- -- -- -- -- -- -- Min. -- 7.5 2.8 2.8 -- 3 0 1.5 -- 0 0 2 2.1 1.5 1.5 1.5 1.5 1.0 0.5 0.5 0.5 0.5 Max. 133 -- -- -- 4 -- -- 3.5 3.8 -- -- 5 -- -- -- -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. -- 6 2.4 2.4 -- 3 0 1.5 -- 0 0 2 2.1 1.5 1.5 1.5 1.5 1.0 0.5 0.5 0.5 0.5
(R)
Symbol fMAX(3) tKC(3) tKH tKL(3) tKQ(3) tKQX(1) tKQLZ(1,2) tKQHZ(1,2) tOEQ(3) tOEQX(1) tOELZ(1,2) tOEHZ(1,2) tAS(3) tSS(3) tWS(3) tCES(3) tAVS(3) tAH(3) tSH(3) tWH(3) tCEH(3) tAVH(3)
Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time
Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Tested with load in Figure 1.
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
IS61LP6432A IS61LP6436A
READ/WRITE CYCLE TIMING
tKC
ISSI
tKH tKL
(R)
CLK
tSS tSH
ADSP is blocked by CE inactive
tSH
ADSP
tSS
ADSC initiate read
tAVH
ADSC
tAVS
Suspend Burst
ADV
tAS tAH
A15-A0
RD1
tWS tWH
RD2
RD3
GW
tWS tWH
BWE
BW4-BW1
tCES tCEH
CE Masks ADSP
CE
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
CE2
tCES tCEH
CE2
tOEQ tOEHZ
OE
tOELZ tOEQX tKQX
DATAOUT
High-Z
tKQLZ tKQ
1a
2a
2b
2c
2d
3a
tKQHZ
DATAIN
High-Z Pipelined Read Single Read Burst Read Unselected
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
11
IS61LP6432A IS61LP6436A
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
ISSI
Min. 6 2.4 2.4 2.1 1.5 1.5 1.5 1.5 1.5 1.0 0.5 1.0 0.5 0.5 0.5 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -133 Min. Max. 7.5 -- 2.8 2.8 2.1 1.5 1.5 1.5 1.5 1.5 1.0 0.5 1.0 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(R)
Symbol tKC(1) tKH(1) tKL(1) tAS(1) tSS(1) tWS(1) tDS(1) tCES(1) tAVS(1) tAH(1) tSH(1) tDH(1) tWH(1) tCEH(1) tAVH(1)
Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time
Note: 1. Tested with load in Figure 1.
12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
IS61LP6432A IS61LP6436A
WRITE CYCLE TIMING
tKC
ISSI
tKH tKL
(R)
CLK
tSS tSH
ADSP is blocked by CE inactive ADSC initiate Write
ADSP ADSC ADV must be inactive for ADSP Write tAVS ADV
tAS tAH tAVH
A15-A0
WR1
tWS tWH
WR2
WR3
GW
tWS tWH
BWE
tWS tWH tWS tWH
BW4-BW1
tCES tCEH
WR1
WR2 CE Masks ADSP
WR3
CE
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
CE2
tCES tCEH
CE2
OE High-Z
tDS tDH
DATAOUT
BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d 3a
DATAIN
High-Z
1a
Single Write
Burst Write
Write
Unselected
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
13
IS61LP6432A IS61LP6436A
ISSI
-166
(R)
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-133 Max. -- -- -- 3.5 -- -- 3.5 3.5 -- -- 4.5 -- -- -- -- -- -- -- -- Min. 7.5 2.8 2.8 -- 1.5 0 1.5 -- 0 0 2 2.1 1.5 1.5 1.0 0.5 0.5 2 2 Max. -- -- -- 4 -- -- 3.5 3.9 -- -- 5.0 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc Symbol tKC(3) tKH(3) tKL(3) tKQ(3) tKQX(1) tKQLZ(1,2) tKQHZ(1,2) tOEQ(3) tOEQX(1) tOELZ(1,2) tOEHZ(1,2) tAS(3) tSS(3) tCES(3) tAH(3) tSH(3) tCEH(3) tZZS tZZREC Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby ZZ Recovery Min. 6 2.4 2.4 -- 1.5 0 1.5 -- 0 0 2 2.1 1.5 1.5 1.0 0.5 0.5 2 2
Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Tested with load in Figure 1.
14
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
IS61LP6432A IS61LP6436A
SNOOZE AND RECOVERY CYCLE TIMING
tKC
ISSI
tSH tKH tKL
(R)
CLK
tSS
ADSP ADSC
ADV
tAS tAH
A15-A0
RD1
RD2
GW
BWE
BW4-BW1
tCES tCEH
CE
tCES tCEH
CE2
tCES tCEH
CE2
tOEQ tOEHZ
OE
tOELZ tOEQX
DATAOUT
High-Z
tKQLZ tKQ
1a
tKQX tKQHZ tZZS tZZREC
DATAIN ZZ
High-Z
Single Read
Snooze with Data Retention
Read
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
15
IS61LP6432A IS61LP6436A
ISSI
Order Part Number IS61LP6432A-133TQ Package TQFP
(R)
ORDERING INFORMATION: IS61LP6432A Commercial Range: 0C to +70C
Speed 133 MHz
Industrial Range: -40C to +85C
Speed 133 MHz 133 MHz Order Part Number IS61LP6432A-133TQI IS61LP6432A-133TQLI Package TQFP TQFP, Lead-free
ORDERING INFORMATION: IS61LP6436A Commercial Range: 0C to +70C
Speed 166 MHz 133 MHz Order Part Number IS61LP6436A-166TQ IS61LP6436A-133TQ Package TQFP TQFP
Industrial Range: -40C to +85C
Speed 166 MHz 166 MHz 133 MHz 133 MHz Order Part Number IS61LP6436A-166TQI IS61LP6436A-166TQLI IS61LP6436A-133TQI IS61LP6436A-133TQLI Package TQFP TQFP, Lead-free TQFP TQFP, Lead-free
16
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/02/05
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package) Package Code: TQ
ISSI
D D1
(R)
E
E1
N
1
C e SEATING PLANE
L1 L
A2 A1 b
A
Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A -- 1.60 -- 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. C 0o 7o 0o 7o
Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max 128 -- 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o
Inches Min Max
-- 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o
Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PK13197LQ Rev. D 05/08/03

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