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HY57V64820HGTP
4 Banks x 2M x 8Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V64820HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V64820HG is organized as 4banks of 2,097,152x8. HY57V64820HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a 2N rule.)
FEATURES
* * * Single 3.30.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operation * * * * Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst * - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks
* *
ORDERING INFORMATION
Part No.
HY57V64820HGTP-5/55/6/7 HY57V64820HGTP-K HY57V64820HGTP-H HY57V64820HGTP-8 HY57V64820HGTP-P HY57V64820HGTP-S HY57V64820HGLTP-5/55/6/7 HY57V64820HGLTP-K HY57V64820HGLTP-H HY57V64820HGLTP-8 HY57V64820HGLTP-P HY57V64820HGLTP-S
Clock Frequency
200/183/166/143MHz 133MHz 133MHz
Power
Organization
Interface
Package
Normal 125MHz 100MHz 100MHz 4Banks x 2Mbits x8 200/183/166/143MHz 133MHz 133MHz Low power 125MHz 100MHz 100MHz LVTTL 400mil 54pin TSOP II (Pb free)
Note) Hynix supports lead free part for each speed grade with same specification.
This document is a general product description and is subject to change without notice.Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/ Nov. 03 1
HY57V64820HGTP
PIN CONFIGURATION
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54pin TSOP II 400mil x 875mil 0.8mm pin pitch
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
PIN DESCRIPTION
PIN CLK CKE CS BA0, BA1 A0 ~ A11 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
RAS, CAS, WE DQM DQ0 ~ DQ7 VDD/VSS VDDQ/VSSQ NC
Rev. 0.1/ Nov. 03
2
HY57V64820HGTP
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 8 I/O Synchronous DRAM
Self refresh logic & timer
Internal Row counter
CLK
Row active
2Mx8 Bank3 Row Pre Decoders 2Mx8 Bank 2 X decoders 2Mx8 Bank 1 X decoders 2Mx8 Bank 0 X decoders DQ0 DQ1 I/O Buffer & Logic Sense AMP & I/O Gate
CKE CS RAS CAS WE DQM
State Machine Address buffers
X decoders
refresh
Column Active
Memory Cell Array
Column Pre Decoders
DQ6 DQ7
Y decoders
Bank Select
Column Add Counter
A0 A1
Address Registers Burst Counter
A11 BA0 BA1
Mode Registers
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.1/ Nov. 03
3
HY57V64820HGTP
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Rating Unit C C
Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature Time
TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER
0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 10
V V mA W
C Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70C)
Parameter Symbol Min Typ. Max Unit Note
Power Supply Voltage Input High Voltage Input Low Voltage
VDD, VDDQ VIH VIL
3.0 2.0 VSSQ - 2.0
3.3 3.0 0
3.6 VDDQ + 2.0 0.8
V V V
1 1,2 1,3
Note : 1.All voltages are referenced to VSS = 0V 2.VIH (max) is acceptable 5.6V AC pulse width with 3ns of duration 3.VIL (min) is acceptable -2.0V AC pulse width with 3ns of duration
AC OPERATING CONDITION (TA=0 to 70C, VDD=3.3 0.3V, VSS=0V)
Parameter Symbol Value Unit Note
AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Output Load Capacitance for Access Time Measurement
VIH / VIL Vtrip tR / tF Voutref CL
2.4/0.4 1.4 1 1.4 50
V V ns V pF 1
Note : 1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuit
Rev. 0.1/ Nov. 03
4
HY57V64820HGTP
CAPACITANCE (TA=25C, f=1MHz)
Parameter Pin Symbol Min Max Unit
Input capacitance
CLK A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM
CI1 CI2
2 2.5
4 5
pF pF
Data input / output capacitance
DQ0 ~ DQ7
CI/O
2
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Output
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA=0 to 70C, VDD=3.30.3V)
Parameter Symbol Min. Max Unit Note
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
ILI ILO VOH VOL
-1 -1 2.4 -
1 1 0.4
uA uA V V
1 2 IOH = -4mA IOL = +4mA
Note : 1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 0.1/ Nov. 03
5
HY57V64820HGTP
DC CHARACTERISTICS II (TA=0 to 70C, VDD=3.30.3V, VSS=0V)
Speed Parameter Symbol Test Condition -6 -7
85
Unit -K
85 2 2
Note
-H
85
-8
85
-P/S
80 mA mA mA 1
Operating Current
IDD1 IDD2P IDD2PS
Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = min CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = min CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active CL=3 CL=2
90
Precharge Standby Current in Power Down Mode
IDD2N Precharge Standby Current in Non Power Down Mode IDD2NS IDD3P IDD3PS
15
mA
12 6 5
mA mA mA
Active Standby Current in Power Down Mode
IDD3N Active Standby Current in Non Power Down Mode IDD3NS
30
mA
20 150 NA 150 NA 160 1 150 150 120 130 120
mA mA mA mA mA uA 2 3 4 1
Burst Mode Operating Current Auto Refresh Current
IDD4
IDD5
tRRC tRRC(min), All banks active CKE 0.2V
Self Refresh Current
IDD6
400
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V64820HGTP-7/K/H/8/P/S 4.HY57V64820HGLTP-7/K/H/8/P/S
Rev. 0.1/ Nov. 03
6
HY57V64820HGTP
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-6 Parameter Symbol Min CAS Latency = 3 CAS Latency = 2 tCK3 6 1000 tCK2 tCHW tCLW tAC3 10 2.5 2.5 5.4 10 2.5 2.5 5.4 Max Min 7 1000 7.5 2.5 2.5 5.4 Max Min 7.5 1000 10 2.5 2.5 5.4 Max Min 7.5 1000 10 3 3 6 Max Min 8 1000 10 3 3 6 Max Min 10 1000 12 3 3 6 Max Min 10 1000 ns ns ns ns 2 CAS Latency = 2 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 6 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 6 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 5.4 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 6 3 2 1 2 1 2 1 2 1 1 6 3 2 1 2 1 2 1 2 1 1 6 3 2 1 2 1 2 1 2 1 2 8 ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 Max ns -7 -K -H -8 -P -S Unit Note
System clock cycle time
Clock high pulse width Clock low pulse width CAS Latency = 3
Access time from clock
Data-out hold time Data-Input setup time Data-Input hold time Address setup time Address hold time CKE setup time CKE hold time Command setup time Command hold time CLK to data output in low Z-time CAS Latency = 3 CLK to data output in high Z-time CAS Latency = 2
tOHZ3 5.4 tOHZ2 5.4 5.4 5.4 6 6 6
ns
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 0.1/ Nov. 03
7
HY57V64820HGTP
AC CHARACTERISTICS II
-6 Parameter Symbol Min Operation RAS Cycle Time Auto Refresh Max 100K Min 62 62 20 42 20 14 1 0 Max 120K Min 65 65 15 45 15 15 1 0 Max 120K Min 65 65 20 45 20 15 1 0 Max 120K Min 68 68 20 48 20 16 1 0 Max 120K Min 70 70 20 50 20 20 1 0 Max 120K Min 70 70 20 50 20 20 1 0 Max 120K ns ns ns ns ns ns CLK CLK -7 -K -H -8 -P -S Unit Note
tRC tRRC tRCD tRAS tRP
60 60 18 42 18 12 1 0
RAS to CAS Delay RAS Active Time RAS Precharge Time
RAS to RAS Bank Active tRRD Delay CAS to CAS Delay
tCCD
Write Command to DatatWTL In Delay Data-In to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask
tDPL tDAL tDQZ tDQM
2
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
5 2 0 2 3
-
4 2 0 1 3
-
4 2 0 1 3
-
4 2 0 1 3
-
4 2 0 1 3
-
3 2 0 1 3
-
3 2 0 1 3
-
CLK CLK CLK CLK CLK
MRS to New Command tMRD CAS tPROZ3 Precharge Latency = 3 to Data Output Hi-Z CAS tPROZ2 Latency = 2 Power Down Exit Time Self Refresh Exit Time Refresh Time
2 1 1 -
64
2 1 1 -
64
2 1 1 -
64
2 1 1 -
64
2 1 1 -
64
2 1 1 -
64
2 1 1 -
64
CLK CLK CLK ms 1
tPDE tSRE tREF
Note : 1. A new command can be given tRRC after self refresh exit
Rev. 0.1/ Nov. 03
8
HY57V64820HGTP
DEVICE OPERATING OPTION TABLE
HYHY57V64820(L)TP-6
CAS Latency 166MHz(6ns) 143MHz(7ns) 133MHz(7.5ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 3CLKs 2CLKs
3CLKs 3CLKs 3CLKs
7CLKs 6CLKs 6CLKs
10CLKs 9CLKs 9CLKs
3CLKs 3CLKs 3CLKs
5.4ns 5.4ns 5.4ns
2.7ns 2.7ns 2.7ns
57V64820HG(L)TP-7
CAS Latency 143MHz(7ns) 133MHz(7.5ns) 100MHz(10ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 3CLKs 2CLKs
3CLKs 3CLKs 2CLKs
6CLKs 6CLKs 5CLKs
9CLKs 9CLKs 7CLKs
3CLKs 3CLKs 2CLKs
5.4ns 5.4ns 6ns
2.7ns 2.7ns 3ns
HY57V64820HG(L)TP-K
CAS Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) tRCD tRAS tRC tRP tAC tOH
2CLKs 3CLKs 2CLKs
2CLKs 3CLKs 2CLKs
6CLKs 6CLKs 5CLKs
8CLKs 9CLKs 7CLKs
2CLKs 3CLKs 2CLKs
5.4ns 6ns 6ns
2.7ns 3ns 3ns
HY57V64820HG(L)TP-H
CAS Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 3CLKs 2CLKs
3CLKs 3CLKs 2CLKs
6CLKs 6CLKs 5CLKs
9CLKs 9CLKs 7CLKs
3CLKs 3CLKs 2CLKs
5.4ns 6ns 6ns
2.7ns 3ns 3ns
HY57V64820HG(L)TP-8
CAS Latency 125MHz(8ns) 100MHz(10ns) 83MHz(12ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 2CLKs 2CLKs
3CLKs 2CLKs 2CLKs
7CLKs 5CLKs 5CLKs
10CLKs 7CLKs 7CLKs
3CLKs 2CLKs 2CLKs
6ns 6ns 6ns
3ns 3ns 3ns
HY57V64820HG(L)TP-P
CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) tRCD tRAS tRC tRP tAC tOH
2CLKs 2CLKs 2CLKs
2CLKs 2CLKs 2CLKs
5CLKs 5CLKs 4CLKs
7CLKs 7CLKs 6CLKs
2CLKs 2CLKs 2CLKs
6ns 6ns 6ns
3ns 3ns 3ns
HY57V64820HG(L)TP-S
CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 2CLKs 2CLKs
2CLKs 2CLKs 2CLKs
5CLKs 5CLKs 4CLKs
7CLKs 7CLKs 6CLKs
2CLKs 2CLKs 2CLKs
6ns 6ns 6ns
3ns 3ns 3ns
Rev. 0.1/ Nov. 03
9
HY57V64820HGTP
COMMAND TRUTH TABLE
Command CKEn-1 CKEn CS RAS CAS WE DQM
ADDR
A10/ AP
BA
Note
Mode Register Set No Operation Bank Active Read
H H H H
X X
L H L
L X H L H
L X H H L
L X
X X
OP code X RA L CA H L V V
H H H X X
X X
L L
Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop DQM Auto Refresh Burst-READ-Single-WRITE Entry Self Refresh1 Exit L H L H Entry Precharge power down Exit L H L H Clock Suspend Entry Exit
Note :
X
L
H
L
L
X
CA H H
V X V
X X
L L
L H X
H H
L L
X X V
X L X X X A9 Pin High (Other Pins OP code)
H H H H H
H X L
L L L H
L L L X H X H X H X V X
L L L X H X H X H X V
H L H X
X X X
X X
H X X H X X X H X X V X X
H
L L H
H L
L L H
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Dont care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation
Rev. 0.1/ Nov. 03
10
HY57V64820HGTP
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
UNIT : mm(inch)
11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 1.194(0.0470) 0.991(0.0390)
0.80(0.0315)BSC
0.400(0.016) 0.300(0.012)
5deg 0deg
0.597(0.0235) 0.406(0.0160)
0.210(0.0083) 0.120(0.0047)
Rev. 0.1/ Nov. 03
11

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