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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
High Performance CHMOS 16-bit CPU 16 MHz Operating Frequency 32 Kbytes of On-chip OTPROM/ROM 744 Bytes of On-chip Register RAM Register-to-register Architecture 16 Prioritized Interrupt Sources Peripheral Transaction Server (PTS) with 15 Prioritized Sources Up to 52 I/O Lines 3-phase Complementary Waveform Generator 8-channel 8- or 10-bit A/D with Sample and Hold 2-channel UART Event Processor Array (EPA) with 2 Highspeed Capture/Compare Modules and 4 Highspeed Compare-only Modules Two Programmable 16-bit Timers with Quadrature Counting Inputs Two Pulse-width Modulator (PWM) Outputs with High Drive Capability Flexible 8- or 16-bit External Bus 1.75 s 16 x 16 Multiply 3 s 32/16 Divide Extended Temperature Available Idle and Powerdown Modes Watchdog Timer
The 8XC196MH is a member of Intel's family of 16-bit MCS(R) 96 microcontrollers. It is designed primarily to control three-phase AC induction and DC brushless motors. It features an enhanced three-phase waveform generator specifically designed for use in "inverter" motor-control applications. This peripheral provides pulsewidth modulation and three-phase sine wave generation with minimal CPU intervention. It generates three complementary non-overlapping PWM pulses with resolutions of 0.125 s (edge triggered) or 0.250 s (centered). The 8XC196MH has two dedicated serial port peripherals, allowing less software overhead. The watchdog timer can be programmed with one of four time options. The 8XC196MH is available as the 80C196MH, which does not have on-chip ROM, the 87C196MH, which contains 32 Kbytes of on-chip OTPROM* or factory programmed ROM, and the 83C196MH, which contains 32 Kbytes of factory programmed MASK ROM. It is available in 84-lead PLCC, 80-lead Shrink EIAJ/QFP, and 64-lead SDIP. The 64-lead package does not contain pins for the P5.1/INST and P6.7/PWM1 signals. Operational characteristics are guaranteed over the temperature range of - 40C to + 85C.
*One-Time Programmable Read-Only Memory (OTPROM) is similar to EPROM but comes in an unwindowed package and cannot be erased. It is user programmable.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. (c) INTEL CORPORATION, 2004 August 2004 Order Number: 272543-003
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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CPU
16
32K On-chip ROM/ OTPROM Interrupt Controller 8 Memory Controller 8 Queue Port 5 Control Signals Port 3 AD7:0 Port 4 AD15:8 Watchdog Timer
744 Byte Register File 8/10-Bit A/D Converter
RALU
24 Bytes CPU SFRs
Microcode Engine
Peripheral Transaction Server
8 S/H
Mux
Port 0
Baud Rate Generator 4
SIO 0 SIO 1
Timer 1 Timer 2
Event Processor Array
3-Phase Waveform Generator 6
PWM0 PWM1
2 Port 1 Port 2
6 Port 6
2
8 4 A/D Port 0 Port 1 Serial I/O 8 Port 2 SIO, EPA 2 Capture/Compare 4 Compare EXTINT 8 Port 6 Waveform Generator
A2542-01
Figure 1. 8XC196MH Block Diagram
2
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER the application. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. Table 1. Thermal Characteristics Package Type 84-lead PLCC 80-lead QFP 64-lead SDIP 33C/W 56C/W 56C/W JA 11C/W 12C/W N/A JC
PROCESS INFORMATION
This device is manufactured on PX29.5, a CHMOS IV process. Additional process and reliability information is available in Intel's Components Quality and Reliability Handbook (order number 210997). All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values will change depending on operating conditions and
X XX 8 X C 196 XX XX
Device Speed: Product Family: CHMOS Technology Program Memory Options: Package - Type Options: Temperature and Burn In Options: 0 = ROMless, 3 = ROM, 7 = OTPROM x = SDIP, x = PLCC, x = QFP x = -40C - +85C Ambient with Intel Standard Burn-In
A2759-01
No Mark = 16 MHz Kx, Mx, Nx
Figure 2. The 8XC196MH Family Nomenclature
NOTE:
To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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Table 2. 8XC196MH Memory Map Address (1) 0FFFFH 0A000H 09FFFH 02080H 0207FH 0205EH 0205DH 02040H 0203FH 02030H 0202FH 02020H 0201FH 0201CH 0201BH 0201AH 02019H 02018H 02017H 02014H 02013H 02000H 01FFFH 01F00H 1EFFH 300H 2FFH 18H 17H 00H External Memory Internal ROM/OTPROM or External Memory Reserved PTS Vectors Interrupt Vectors (upper) ROM/OTPROM Security Key Reserved Reserved (must contain 20H) CCB1 Reserved (must contain 20H) CCB0 Reserved Interrupt Vectors (lower) Internal SFRs External Memory Register RAM CPU SFRs 3 1 1 1, 2 1, 2 Description Notes
NOTES: 1. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits. 2. WARNING: The contents and/or function of reserved locations may change with future revisions of the device. 3. Code executed in locations 0000H to 02FFH will be forced external.
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 3. Signals Arranged by Functional Categories Address & Data AD15:0 Programming Control AINC# CPVER Bus Control & Status ALE/ADV# BHE#/WRH# BUSWIDTH INST READY RD# WR#/WRL# Processor Control EA# Power & Ground ANGND VCC VPP VREF VSS NOTE: EXTINT NMI ONCE# RESET# XTAL1 XTAL2 PACT# PALE# PBUS15:0 PMODE.3:0 PROG# PVER Input/Output P0.0/ACH0 P0.1/ACH1 P0.2/ACH2 P0.3/ACH3 P0.4/ACH4 P0.5/ACH5 P0.6/ACH6/T1CLK P0.7/ACH7/T1DIR P1.0/TXD0 P1.1/RXD0 P1.2/TXD1 P1.3/RXD1 P2.0/EPA0 P2.1/SCLK0#/BCLK0 P2.2/EPA1 P2.3/COMP3 P2.4/COMP0 Input/Output (Cont'd) P2.5/COMP1 P2.6/COMP2 P2.7/SCLK1#/BCLK1 P3.7:0 P4.7:0 P5.7:0 P6.0/WG1# P6.1/WG1 P6.2/WG2# P6.3/WG2 P6.4/WG3# P6.5/WG3 P6.6/PWM0 P6.7/PWM1
The following signals are not available in the 64-pin package: P5.1, P6.7, INST, and PWM1.
5
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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VSS
P5.0/ALE/ADV#
VPP
P5.3/RD# P5.5/BHE#/WRH# P5.2/WR#/WRL# P5.7/BUSWIDTH P4.6/AD14/PBUS.14 P4.5/AD13/PBUS.13 P4.7/AD15/PBUS.15
VCC
P4.4/AD12/PBUS.12 P4.3/AD11/PBUS.11 P4.2/AD10/PBUS.10 P4.1/AD9/PBUS.9 P4.0/AD8/PBUS.8 P3.7/AD7/PBUS.7 P3.6/AD6/PBUS.6 P3.5/AD5/PBUS.5 P3.4/AD4/PBUS.4 P3.3/AD3/PBUS.3 P3.2/AD2/PBUS.2 P3.1/AD1/PBUS.1 P3.0/AD0/PBUS.0 RESET# NMI EA#
VSS VCC
P6.5/WG3 P6.4/WG3# P6.3/WG2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
xx8XC196MH
TOP VIEW (Looking down on component side of PC board)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P5.6/READY P5.4/ONCE# EXTINT
VSS
XTAL1 XTAL2 P6.6/PWM0 P2.7/SCLK1#/BCLK1 P2.6/COMP2/CPVER P2.5/COMP1/PACT# P2.4/COMP0/AINC# P2.3/COMP3 P2.2/EPA1/PROG# P2.1/SCLK0#/BCLK0/PALE# P2.0/EPA0/PVER P0.0/ACH0 P0.1/ACH1 P0.2/ACH2 P0.3/ACH3 P0.4/ACH4/PMODE.0 P0.5/ACH5/PMODE.1
VREF
ANGND P0.6/ACH6/T1CLK/PMODE.2 P0.7/ACH7/T1DIR/PMODE.3 P1.0/TXD0 P1.1/RXD0 P1.2/TXD1 P1.3/RXD1 P6.0/WG1# P6.1/WG1 P6.2/WG2#
A2572-01
Figure 3. 8XC196MH 64-lead Shrink DIP (SDIP) Package
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER Table 4. 64-lead Shrink DIP (SDIP) Pin Assignment
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS
Name
Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Name P3.7/AD7 /PBUS.7 P3.6/AD6 /PBUS.6 P3.5/AD5 /PBUS.5 P3.4/AD4 /PBUS.4 P3.3/AD3 /PBUS.3 P3.2/AD2 /PBUS.2 P3.1/AD1 /PBUS.1 P3.0/AD0 /PBUS.0 RESET# NMI EA# VSS VCC P6.5/WG3 P6.4/WG3# P6.3/WG2
Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Name P6.2/WG2# P6.1/WG1 P6.0/WG1# P1.3/RXD1 P1.2/TXD1 P1.1/RXD0 P1.0/TXD0 P0.7/ACH7/T1DIR /PMODE.3 P0.6/ACH6 /T1CLK/PMODE.2 ANGND VREF P0.5/ACH5 /PMODE.1 P0.4/ACH4 /PMODE.0 P0.3/ACH3 P0.2/ACH2 P0.1/ACH1
Pin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Name P0.0/ACH0 P2.0/EPA0/PVER P2.1/SCLK0# /BCLK0/PALE# P2.2/EPA1 /PROG# P2.3/COMP3 P2.4/COMP0 /AINC# P2.5/COMP1 /PACT# P2.6/COMP2 /CPVER P2.7/SCLK1# /BCLK1 P6.6/PWM0 XTAL2 XTAL1 VSS EXTINT P5.4/ONCE# P5.6/READY
P5.0/ALE/ADV# VPP P5.3/RD# P5.5/BHE#/WRH# P5.2/WR#/WRL# P5.7/BUSWIDTH P4.6/AD14 /PBUS.14 P4.5/AD13 /PBUS.13 P4.7/AD15 /PBUS.15 VCC P4.4/AD12 /PBUS.12 P4.3/AD11 /PBUS.11 P4.2/AD10 /PBUS.10 P4.1/AD9/PBUS.9 P4.0/AD8/PBUS.8
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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P4.7/AD15/PBUS.15 P4.6/AD14/PBUS.14 VCC P4.5/AD13/PBUS.13 NC P4.4/AD12/PBUS.12 P4.3/AD11/PBUS.11 P4.2/AD10/PBUS.10 P4.1/AD9/PBUS.9 P4.0/AD8/PBUS.8 NC NC P3.7/AD7/PBUS.7 P3.6/AD6/PBUS.6 P3.5.AD5/PBUS.5 P3.4/AD4/PBUS.4 P3.3/AD3/PBUS.3 P3.2/AD2/PBUS.2 P3.1/AD1/PBUS.1 P3.0/AD0/PBUS.0 NC
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
P5.7/BUSWIDTH P5.2/WR#/WRL# NC P5.5/BHE#/WRH# P5.3/RD# VPP P5.0/ALE/ADV# VSS P5.1/INST P5.6/READY P5.4/ONCE# EXTINT VSS XTAL1 XTAL2 NC NC NC P6.6/PWM0 P6.7/PWM1 P2.6/COMP2/CPVER
xx8XC196MH
TOP VIEW (Looking down on component side of PC board)
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
P2.5/COMP1/PACT# P2.4/COMP0/AINC# NC NC P2.7/SCLK1#/BCLK1 P2.3/COMP3 P2.2/EPA1/PROG# NC NC P2.1/SCLK0#/BCLK0/PALE# P2.0/EPA0/PVER NC P0.0/ACH0 P0.1/ACH1 P0.2/ACH2 P0.3/ACH3 P0.4/ACH4/PMODE.0 P0.5/ACH5/PMODE.1 VREF ANGND P0.6/ACH6/T1CLK/PMODE.2
RESET# NMI NC EA# VSS NC VCC P6.5/WG3 P6.4/WG3# P6.3/WG2 VSS P6.2/WG2# P6.1/WG1 P6.0/WG1# P1.3/RXD1 P1.2/TXD1 NC NC P1.1/RXD0 P1.0/TXD0 P0.7/ACH7/T1DIR/PMODE.3
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
A2573-02
Figure 4. 8XC196MH 84-lead PLCC Package
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER Table 5. 84-lead PLCC Pin Assignment
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Name P5.4/ONCE# P5.6/READY P5.1/INST VSS P5.0/ALE/ADV# VPP P5.3/RD# P5.5/BHE#/WRH# NC P5.2/WR#/WRL# P5.7/BUSWIDTH P4.7/AD15 /PBUS.15 P4.6/AD14 /PBUS.14 VCC P4.5/AD13 /PBUS.13 NC P4.4/AD12 /PBUS.12 P4.3/AD11 /PBUS.11 P4.2/AD10 /PBUS.10 P4.1/AD9/PBUS.9 P4.0/AD8/PBUS.8
Pin 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NC NC
Name
Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 VSS
Name
Pin 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Name P2.0/EPA0/PVER P2.1/SCLK0# /BCLK0/PALE# NC NC P2.2/EPA1 /PROG# P2.3/COMP3 P2.7/SCLK1# /BCLK1 NC NC P2.4/COMP0 /AINC# P2.5/COMP1 /PACT# P2.6/COMP2 /CPVER P6.7/PWM1 P6.6/PWM0 NC NC NC XTAL2 XTAL1 VSS EXTINT
P6.2/WG2# P6.1/WG1 P6.0/WG1# P1.3/RXD1 P1.2/TXD1 NC NC P1.1/RXD0 P1.0/TXD0 P0.7/ACH7 /T1DIR/PMODE.3 P0.6/ACH6 /T1CLK/PMODE.2 ANGND VREF P0.5/ACH5 /PMODE.1 P0.4/ACH4 /PMODE.0 P0.3/ACH3 P0.2/ACH2 P0.1/ACH1 P0.0/ACH0 NC
P3.7/AD7 /PBUS.7 P3.6/AD6 /PBUS.6 P3.5/AD5 /PBUS.5 P3.4/AD4 /PBUS.4 P3.3/AD3 /PBUS.3 P3.2/AD2 /PBUS.2 P3.1/AD1 /PBUS.1 P3.0/AD0 /PBUS.0 NC RESET# NMI NC EA# VSS NC VCC P6.5/WG3 P6.4/WG3# P6.3/WG2
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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P5.5/BHE#/WRH#
P5.0/ALE/ADV#
P5.6/READY
P5.4/ONCE#
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P6.6/PWM0
P5.1/INST
P5.3/RD#
EXTINT
XTAL1
XTAL2
VPP
VSS
VSS
NC
NC
NC
P5.2/WR#/WRL# P5.7/BUSWIDTH P4.7/AD15/PBUS.15 P4.6/AD14/PBUS.14 V CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
64 63 62 61 60 59 58 57 56
P6.7/PWM1 P2.6/COMP2/CPVER P2.5/COMP1/PACT# P2.4/COMP0/AINC# NC NC P2.7/SCLK1#/BCLK1 P2.3/COMP3 P2.2/EPA1/PROG# NC NC P2.1/SCLK0#/BCLK0/PALE# P2.0/EPA0/PVER NC P0.0/ACH0 P0.1/ACH1 P0.2/ACH2 P0.3/ACH3 P0.4/ACH4/PMODE.0 P0.5/ACH5/PMODE.1 VREF ANGND P0.6/ACH6/T1CLK/PMODE.2 P0.7/ACH7/T1DIR/PMODE.3
P4.5/AD13/PBUS.13 NC P4.4/AD12/PBUS.12 P4.3/AD11/PBUS.11 P4.2/AD10/PBUS.10 P4.1/AD9/PBUS.9 P4.0/AD8/PBUS.8 P3.7/AD7/PBUS.7 P3.6/AD6/PBUS.6 P3.5/AD5/PBUS.5 P3.4/AD4/PBUS.4 P3.3/AD3/PBUS.3 P3.2/AD2/PBUS.2 P3.1/AD1/PBUS.1 P3.0/AD0/PBUS.0 NC RESET# NMI EA#
xx8XC196MH
TOP VIEW (Looking down on component side of PC board)
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
26 27 28
P6.5/WG3 NC VCC
29
P6.4/WG3#
30 31 32 33 34 35 36 37 38 39
P1.3/RXD1 P6.2/WG2# P6.0/WG1# P1.1/RXD0 NC P6.3/WG2 P1.2/TXD1 P6.1/WG1 NC SS
40
P1.0/TXD0
V
A2574-01
Figure 5. 8XC196MH 80-lead Shrink EIAJ/QFP Package
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER Table 6. 80-lead Shrink EIAJ/QFP Pin Assignment
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Name P5.2/WR#/WRL# P5.7/BUSWIDTH P4.7/AD15 /PBUS.15 P4.6/AD14 /PBUS.14 VCC P4.5/AD13 /PBUS.13 NC P4.4/AD12 /PBUS.12 P4.3/AD11 /PBUS.11 P4.2/AD10 /PBUS.10 P4.1/AD9/PBUS.9 P4.0/AD8/PBUS.8 P3.7/AD7/PBUS.7 P3.6/AD6/PBUS.6 P3.5/AD5/PBUS.5 P3.4/AD4/PBUS.4 P3.3/AD3/PBUS.3 P3.2/AD2/PBUS.2 P3.1/AD1/PBUS.1 P3.0/AD0/PBUS.0
Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC
Name
Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Name P0.7/ACH7/T1DIR /PMODE.3 P0.6/ACH6 /T1CLK/PMODE.2 ANGND VREF P0.5/ACH5 /PMODE.1 P0.4/ACH4 /PMODE.0 P0.3/ACH3 P0.2/ACH2 P0.1/ACH1 P0.0/ACH0 NC P2.0/EPA0/PVER P2.1/SCLK0# /BCLK0/PALE# NC NC P2.2/EPA1 /PROG# P2.3/COMP3 P2.7/SCLK1# /BCLK1 NC NC
Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Name P2.4/COMP0 /AINC# P2.5/COMP1 /PACT# P2.6/COMP2 /CPVER P6.7/PWM1 P6.6/PWM0 NC NC NC XTAL2 XTAL1 VSS EXTINT P5.4/ONCE# P5.6/READY P5.1/INST VSS P5.0/ALE/ADV# VPP P5.3/RD# P5.5/BHE#/WRH#
RESET# NMI EA# VSS NC VCC P6.5/WG3 P6.4/WG3# P6.3/WG2 VSS P6.2/WG2# P6.1/WG1 P6.0/WG1# P1.3/RXD1 P1.2/TXD1 NC NC P1.1/RXD0 P1.0/TXD0
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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PIN DESCRIPTIONS
Table 7. Signal Descriptions Signal Name ACH7 ACH6 ACH5 ACH4 ACH3:0 Type I Description Analog Channels. These pins are analog inputs to the A/D converter. These pins are multiplexed with the port 0 pins. While it is possible for the pins to function simultaneously as analog and digital inputs, this is not recommended because reading the port while a conversion is in process can produce unreliable conversion results. The ANGND and VREF pins must be connected for the A/D converter and the multiplexed port pins to function. AD15:8 AD7:0 I/O Address/Data Lines. These pins provide a multiplexed address and data bus. During the address phase of the bus cycle, address bits 0-15 are presented on the bus and can be latched using ALE or ADV#. During the data phase, 8- or 16-bit data is transferred. Address Valid. This active-low output signal is asserted only during external memory accesses. ADV# indicates that valid address information is available on the system address/data bus. The signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes. An external latch can use the ADV# signal to demultiplex the address from the address/data bus. Used with a decoder, ADV# can generate chip-selects for external memory. AINC# I Auto Increment. In slave programming mode, this active-low input signal enables the autoincrement mode. Auto increment allows reading from or writing to sequential OTPROM locations without requiring address transactions across the programming bus for each read or write. Address Latch Enable. This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus. ALE differs from ADV# in that it is not returned high until a new bus cycle is to begin. An external latch can use ALE to demultiplex the address from the address/data bus. Analog Ground. Reference ground for the A/D converter and the logic used to read port 0. ANGND must be held at nominally the same potential as VSS. Serial Communications Baud Clock 0 and 1. BCLK0 and 1 are alternate clock sources for the serial ports. The maximum input frequency is FOSC/4. P2.4/COMP0 P4.7:0/PBUS.15:8 P3.7:0/PBUS.7:0 Multiplexed With P0.7/T1DIR/PMODE.3 P0.6/T1CLK/PMODE.2 P0.5/PMODE.1 P0.4/PMODE.0 P0.3:0
ADV#
O
P5.0/ALE
ALE
O
P5.0/ADV#
ANGND
GND
--
BCLK1 BCLK0
I
P2.7/SCLK1# P2.1/SCLK0#/PALE#
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER Table 7. Signal Descriptions (Continued)
Signal Name BHE#
Type O
Description Byte High Enable. During 16-bit bus cycles, this active-low output signal is asserted for word reads and writes and for high-byte reads and writes to external memory. BHE# indicates that valid data is being transferred over the upper half of the system address/data bus. BHE#, in conjunction with A0, selects the memory byte to be accessed: BHE# 0 0 1 A0 0 1 0 Byte(s) Accessed both bytes high byte only low byte only P5.7
Multiplexed With P5.5/WRH#
BUSWIDTH
I
Bus Width. When enabled in the chip configuration register, this active-high input signal dynamically selects the bus width of the bus cycle in progress. When BUSWIDTH is high, a 16bit bus cycle occurs; when BUSWIDTH is low, an 8-bit bus cycle occurs. BUSWIDTH is active during a CCR fetch. Event Processor Array (EPA) Compare Pins. These signals are the output of the EPA compare modules. These pins are multiplexed with other signals and may be configured as standard I/O. Cumulative Program Verification. This active-high output signal indicates whether any verify errors have occurred since the device entered programming mode. CPVER remains high until a verify error occurs, at which time it is driven low. Once an error occurs, CPVER remains low until the device exits programming mode. When high, CPVER indicates that all locations have programmed correctly since the device entered programming mode. External Access. This active-low input signal directs memory accesses to on-chip or off-chip memory. If EA# is low, the memory access is off-chip. If EA# is high and the memory address is within 2000H-2FFFH, the access is to on-chip ROM or OTPROM. Otherwise, an access with EA# high is to off-chip memory. EA# is sampled only on the rising edge of RESET#. If EA# = VEA on the rising edge of RESET#, the device enters the programming mode selected by PMODE.3:0. For devices without ROM, EA# must be tied low. Event Processor Array (EPA) Input/Output pins. These are the high-speed input/output pins for the EPA capture/compare modules. These pins are multiplexed with other signals and may be configured as standard I/O.
COMP3 COMP2 COMP1 COMP0 CPVER
O
P2.3 P2.6/CPVER P2.5/PACT# P2.4/AINC# P2.6/COMP2
O
EA#
I
--
EPA1 EPA0
I/O
P2.2/PROG# P2.0/PVER
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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Table 7. Signal Descriptions (Continued) Signal Name EXTINT Type I Description External Interrupt. This programmable interrupt is controlled by the WG_PROTECT register. This register controls whether the interrupt is edge triggered or sampled and whether a rising edge/high level or falling edge/low level activates the interrupt. This interrupt vectors through memory location 203CH. If the chip is in idle mode and if EXTINT is enabled, a valid EXTINT interrupt brings the chip back to normal operation, where the first action is to execute the EXTINT service routine. After completion of the service routine, execution resumes at the instruction following the one that put the chip into idle mode. In powerdown mode, a valid EXTINT interrupt causes the chip to return to normal operating mode. If EXTINT is enabled, the EXTINT service routine is executed. Otherwise, execution continues at the instruction following the IDLPD instruction that put the chip into powerdown mode. Instruction Fetch. This active-high output signal is valid only during external memory bus cycles. When high, INST indicates that an instruction is being fetched from external memory. The signal remains high during the entire bus cycle of an external instruction fetch. INST is low for data accesses, including interrupt vector fetches and chip configuration byte reads. INST is low during internal memory fetches. Nonmaskable Interrupt. In normal operating mode, a rising edge on NMI causes a vector through the NMI interrupt at location 203EH. NMI must be asserted for greater than one state time to guarantee that it is recognized. In idle mode, a rising edge on NMI brings the chip back to normal operation, where the first action is to execute the NMI service routine. After completion of the service routine, execution resumes at the instruction following the one that put the chip into idle mode. In powerdown mode, NMI causes a return to normal operating mode only if it is tied to EXTINT. -- Multiplexed With
INST
O
P5.1
NMI
I
--
ONCE#
I
P5.4 On-circuit Emulation. Holding this pin low while the RESET# signal transitions from a low to a high places the device into on-circuit emulation (ONCE) mode. ONCE mode isolates the device from other components in the system to allow the use of a clip-on emulator for system debugging. This mode puts all pins except XTAL1 and XTAL2 into a highimpedance state. To exit ONCE mode, reset the device by pulling the RESET# signal low.
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER Table 7. Signal Descriptions (Continued)
Signal Name P0.7 P0.6 P0.5 P0.4 P0.3:0
Type I
Description Port 0. This is a high-impedance, input-only port. Port 0 pins should not be left floating. These pins may individually be used as analog inputs (ACHx) or digital inputs (P0.x). While it is possible for the pins to function simultaneously as analog and digital inputs, this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results. ANGND and VREF must be connected for port 0 and the A/D converter to function.
Multiplexed With ACH7/T1DIR/PMODE.3 ACH6/T1CLK/PMODE.2 ACH5/PMODE.1 ACH4/PMODE.0 ACH3:0
P1.3 P1.2 P1.1 P1.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P3.7:0
I
Port 1. This is a 4-bit, bidirectional, standard I/O port that is multiplexed with individually selectable special-function signals. (Used as PBUS.15:12 in Auto-programming Mode.) Port 2. This is an 8-bit, bidirectional, standard I/O port that is multiplexed with individually selectable special-function signals. P2.6 is multiplexed with a special test mode function. To prevent accidental entry into test modes, always configure P2.6 as an output.
RXD1 TXD1 RXD0 TXD0 SCLK1#/BCLK1 COMP2/CPVER COMP1/PACT# COMP0/AINC# COMP3 EPA1/PROG# SCLK0#/BCLK0/PALE# EPA0/PVER AD7:0/PBUS.7:0
I/O
I/O
Port 3. This is an 8-bit, bidirectional, memory-mapped I/O port with open-drain outputs. The pins are shared with the multiplexed address/data bus, which has complementary drivers. In programming modes, port 3 serves as the low byte of the programming bus (PBUS).
P4.7:0
I/O
Port 4. This is an 8-bit, bidirectional, memory-mapped I/O port with open-drain outputs. The pins are shared with the multiplexed address/data bus, which has complementary drivers. In programming modes, port 4 serves as the high byte of the programming bus (PBUS).
AD15:8/PBUS.15:8
P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0
I/O
Port 5. This is an 8-bit, bidirectional, standard I/O port that is multiplexed with individually selectable control signals. Because P5.4 is multiplexed with the ONCE# function, always configure it as an output to prevent accidental entry into ONCE mode.
BUSWIDTH READY BHE#/WRH# ONCE# RD# WR#/WRL# INST ALE/ADV#
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Table 7. Signal Descriptions (Continued) Signal Name P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 PACT# PALE# Type O Description Port 6. This is an 8-bit output port that is multiplexed with the special functions of the waveform generator and PWM peripherals. The WG_OUT register configures the pins, establishes the output polarity, and controls whether changes to the outputs are synchronized with an event or take effect immediately. Multiplexed With PWM1 PWM0 WG3 WG3# WG2 WG2# WG1 WG1# P2.5/COMP1 P2.1/SCLK0#/BCLK0
O I
Programming Active. In auto-programming mode, PACT# low indicates that programming activity is occurring. Programming ALE. In slave programming mode, this activelow input indicates that ports 3 and 4 contain a command/address. When PALE# is asserted, data and commands on ports 3 and 4 are read into the device. Programming Bus. In programming modes, used as a bidirectional port with open-drain outputs to pass commands, addresses, and data to or from the device. Used as a regular system bus to access external memory during autoprogramming mode. When using slave programming mode, the PBUS is used in open-drain I/O port mode (not as a system bus). In slave programming mode, you must add external pull-up resistors to read data from the device during the dump word routine. Programming Mode Select. Determines the OTPROM programming algorithm that is to be performed. PMODE is sampled after a device reset when EA# = VEA and must be stable while the device is operating. Programming Start. This active-low input is valid only in slave programming mode. The rising edge of PROG# latches data on the PBUS and begins programming. The falling edge of PROG# ends programming. Program Verification. In programming modes, this activehigh output signal is asserted to indicate that the word has programmed correctly. (PVER low after the rising edge of PROG# indicates an error.) Pulse Width Modulator Outputs. These are PWM output pins with high-current drive capability. The duty cycle and frequency-pulse-widths are programmable. Read. Read-signal output to external memory. RD# is asserted only during external memory reads.
PBUS.15:8 PBUS.7:0
I/O
P4.7:0/AD15:8 P3.7:0/AD7:0
PMODE.3 PMODE.2 PMODE.1 PMODE.0 PROG#
I
P0.7/ACH7/T1DIR P0.6/ACH6/T1CLK P0.5/ACH5 P0.4/ACH4 P2.2/EPA1
I
PVER
O
P2.0/EPA0
PWM1:0
O
P6.7:6
RD#
O
P5.3
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER Table 7. Signal Descriptions (Continued)
Signal Name READY
Type I
Description Ready Input. This active-high input signal is used to lengthen external memory cycles for slow memory by generating wait states. When READY is high, CPU operation continues in a normal manner. If READY is low, the memory controller inserts wait states until the READY signal goes high or until the number of wait states is equal to the number programmed into the chip configuration register. READY is ignored for all internal memory accesses. Reset. Reset input to and open-drain output from the chip. A falling edge on RESET# initiates the reset process. When RESET# is first asserted, the chip turns on a pull-down transistor connected to the RESET pin for 16 state times. This function can also be activated by execution of the RST instruction. In the powerdown and idle modes, asserting RESET# causes the chip to reset and return to normal operating mode. RESET# is a level-sensitive input. Receive Serial Data 0 and 1. In modes 1, 2, and 3, RXD0 and 1 are used to receive serial port data. In mode 0, they function as either inputs or open-drain outputs for data. Synchronous Clock Pin 0 and 1. In mode 4, these are the bidrectional, shift clock signals that synchronize the serial data transfer. Data is transferred 8 bits at a time with the LSB first. The DIR bit (SP_CONx.7) controls the direction of SCLKx signal. DIR = 0 DIR = 1 The internal shift clock is output on SCLKx. An external shift clock is input on SCLKx. P5.6
Multiplexed With
RESET#
I/O
--
RXD1 RXD0 SCLK1# SCLK0#
I/O
P1.3 P1.1 P2.7/BCLK1 P2.1/BCLK0
I/O
T1CLK
I
External Clock. External clock for timer 1. Timer 1 increments (or decrements) on both rising and falling edges of T1CLK. Also used in conjunction with T1DIR for quadrature counting mode. Timer 1 External Direction. External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high and decrements when it is low. Also used in conjunction with T1CLK for quadrature counting mode. Transmit Serial Data 0 and 1. In serial I/O modes 1, 2, and 3, TXD0 and 1 are used to transmit serial port data. In mode 0, they are used as the serial clock output. Digital Supply Voltage. Connect each VCC pin to the digital supply voltage. Programming Voltage. Set to 12.5 V when programming the on-chip OTPROM. Also the timing pin for the "return from power-down" circuit.
P0.6/ACH6/PMODE.2
T1DIR
I
P0.7/ACH7/PMODE.3
TXD1 TXD0 VCC VPP
O
P1.2 P1.0 -- --
PWR PWR
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Table 7. Signal Descriptions (Continued) Signal Name VREF Type PWR Description Reference Voltage for the A/D Converter. VREF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. VREF must be connected for the A/D and port 0 to function. Digital Circuit Ground (0 volts). Connect each VSS pin to ground. Waveform Generator Phase 1-3 Positive Outputs. 3-phase output signals used in motion-control applications. Waveform Generator Phase 1-3 Negative Outputs. Complementary 3-phase output signals used in motioncontrol applications. Write. This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. Write High. During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for all write operations. Write Low. During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes. During 8-bit bus cycles, WRL# is asserted for all write operations. Clock/Oscillator Input. Input to the on-chip oscillator inverter and the internal clock generator. Also provides the clock input for the serial I/O baud-rate generator, timers, and PWM unit. If an external oscillator is used, connect the external clock input signal to XTAL1 and ensure that the XTAL1 VIH specification is met. Oscillator Output. Output of the on-chip oscillator inverter. When using the on-chip oscillator, connect XTAL2 to an external crystal or resonator. When using an external clock source, let XTAL2 float. -- Multiplexed With
VSS WG3 WG2 WG1 WG3# WG2# WG1# WR#
GND O
-- P6.5 P6.3 P6.1 P6.4 P6.2 P6.0 P5.2/WRL#
O
O
WRH#
O
P5.5/BHE#
WRL#
O
P5.2/WR#
XTAL1
I
--
XTAL2
O
--
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature ................................ - 65C to + 150C Ambient Temperature under Bias.............................................. - 40C to + 85C Voltage from VPP or EA# to VSS or ANGND (Note 1) ...................... - 0.5 V to + 13.0 V Voltage with respect to VSS or ANGND (Note 1) ........................ - 0.5 V to + 7.0 V (This includes VPP on ROM and CPU devices.) Power Dissipation .......................................................... 1.5 W (based on package heat transfer limitations, not device power consumption)
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice.
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
OPERATING CONDITIONS*
TA (Ambient Temperature Under Bias) .........- 40C to + 85C VCC (Digital Supply Voltage) .......................... 4.50 V to 5.50 V VREF (Analog Supply Voltage) ....................... 4.50 V to 5.50 V FOSC (Oscillator Frequency) (Note 2) ........... 8 MHz to 16 MHz
NOTES: 1. ANGND and VSS should be at nominally the same potential. 2. Testing is performed down to 8 MHz, although the device is static by design and will typically operate below 1 Hz.
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DC CHARACTERISTICS
Table 8. DC Characteristics over Specified Operating Conditions Symbol VIL VIL1 Parameter Input Low Voltage (standard inputs (1)) Input Low Voltage (RESET#, ports 3, 4, and 5) Input High Voltage (standard inputs (1)) Input High Voltage (RESET#, ports 3, 4, and 5) Output Low Voltage (RESET#, ports 1, 2, 5, P6.6, P6.7, and XTAL2) Output Low Voltage (ports 3, 4) Output Low Voltage (P6.5:0) Output High Voltage (output pins and I/O configured as push/pull outputs) Hysteresis voltage width on RESET# pin Input Leakage Current (standard inputs (1)) Input Leakage Current (port 0 - A/D inputs) Input High Current (NMI) Input Low Current (port 2, except P2.6) VCC - 0.3 VCC - 0.7 VCC - 1.5 0.2 10 3 300 - 70 Min - 0.5 - 0.5 Typ (4) Max 0.3 VCC 0.8 Units V V Test Conditions
VIH VIH1
0.7 VCC 0.2 VCC + 1.0
VCC + 0.5 VCC + 0.5
V V
VOL
0.3 0.45 1.5 1.0 0.45
V V V V V V V V V A A A A
IOL = 200 A IOL = 3.2 mA IOL = 7.0 mA IOL = 7 mA IOL = 10 mA IOH = - 200 A IOH = - 3.2 mA IOH = - 7.0 mA
VOL1 VOL2 VOH
VTH+ - VTH- ILI ILI1 IIH IIL
VSS < VIN < VCC - 0.3V VSS < VIN < VREF VIN = 0.7 VCC VIN = 0.3 VCC
NOTES: 1. Standard input pins include XTAL1, EA#, and Ports 1 and 2 when configured as inputs. 2. Maximum current that an external device must sink to ensure test mode entry. 3. Violating these specifications during reset may cause the device to enter test modes. 4. Typical values are based on a limited number of samples and are not guaranteed. Operating conditions for typical values are room temperature and V REF = VCC = 5.5 V. 5. Testing is performed down to 8 MHz, although the device is static by design and will typically operate below 1 Hz. 6. All voltages are referenced relative to VSS. When used, VSS refers to the device pin. 7. Table 9 lists the total current limits during normal (non-transient conditions). The total current listed is the sum of the pins listed for each specification value.
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER Table 8. DC Characteristics over Specified Operating Conditions (Continued)
Symbol IIL1 IIL2 IIL3 IOH IOH1 ICC
Parameter Input Low Current (P5.4 and P2.6 during reset) (2) Input Low Current (ports 3, 4, and 5, except P5.4) Input Low Current (port 1) Output High Current (P5.4 and P2.6 during reset) (3) Output High Current (P6.5:0 during reset) VCC Supply Current
Min
Typ (4)
Max - 10 - 300 - 300
Units mA A A mA
Test Conditions VIN = 0.8 V VIN = 0.8 V VIN = 0.3 VCC 0.7 VCC 0.7 VCC XTAL1 = 16 MHz VCC = 5.5 V VPP = 5.5 V VREF = 5.5 V
- 0.2 -6 50 - 40 70
A mA
IREF IIDLE IPD RRST CS
A/D Reference Supply Current Idle Mode Current Powerdown Mode Current (4) Reset Pull-up Resistor Pin Capacitance (any pin to VSS) 6
2 15 5
5 30 50 65 10
mA mA A k pF FTEST = 1.0 MHz
NOTES: 1. Standard input pins include XTAL1, EA#, and Ports 1 and 2 when configured as inputs. 2. Maximum current that an external device must sink to ensure test mode entry. 3. Violating these specifications during reset may cause the device to enter test modes. 4. Typical values are based on a limited number of samples and are not guaranteed. Operating conditions for typical values are room temperature and V REF = VCC = 5.5 V. 5. Testing is performed down to 8 MHz, although the device is static by design and will typically operate below 1 Hz. 6. All voltages are referenced relative to VSS. When used, VSS refers to the device pin. 7. Table 9 lists the total current limits during normal (non-transient conditions). The total current listed is the sum of the pins listed for each specification value.
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70 60 50 ICC 40 (mA) 30 20
ICC Max
ICC Typ
IIDLE Max
IIDLE Typ 10 0 0 4 10 16 Frequency (MHz)
A2711-01
Table 9. Total Current Limits During Normal (Non-transient) Conditions Signal Names Port 1 Port 2, P6.6, P6.7 Port 3 Port 4 Port 5 P6.5:0 Maximum IOL Limits 25 mA 40 mA 40 mA 40 mA 40 mA 40 mA Figure 6. ICC, IIDLE versus Frequency Maximum IOH Limits - 25 mA - 40 mA - 30 mA - 30 mA - 30 mA - 30 mA
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
EXPLANATION OF AC SYMBOLS
Each symbol consists of two pairs of letters prefixed by "T" (for time). The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. For example, TRHDZ is the time between signal R (RD#) condition H (high) and signal D (Input Data) condition Z (floating). Table 10 defines the signal and condition codes. Table 10. AC Timing Symbol Definitions
Signals
A B D G I K L Address BHE# Data In BUSWIDTH T1DIR/AINC# T1CLK ALE/ADV#/PALE# P Q R V W X Y PROG# Data Out RD# PVER WR#/WRH#/WRL# XTAL1 READY H L V X Z
Conditions
High Low Valid No Longer Valid Floating
AC CHARACTERISTICS (OVER SPECIFIED OPERATION CONDITIONS)
Table 11 defines the AC timing specifications that the external memory system must meet and those that the 8XC196MH will provide. Table 11. AC Timing Definitions (1) Symbol FOSC TOSC TAVYV TLLYV TYLYH TLLYX TAVGV TLLGV Parameter Frequency on XTAL1 1/FOSC Address Valid to READY Setup ALE/ADV# Low to READY Setup Non READY Time READY Hold after ALE/ADV# Low Address Valid to BUSWIDTH Setup ALE/ADV# Low to BUSWIDTH Setup Min 8 62.5 Max 16 125 Units MHz ns Notes 4
The External Memory System Must Meet These Specifications 2TOSC - 75 TOSC - 70 No Upper Limit TOSC - 15 2TOSC - 40 2TOSC - 75 TOSC - 60 ns ns ns ns ns ns 2
NOTES: 1. Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, FOSC = 16 MHz. 2. Exceeding the maximum specification causes additional wait states. 3. If wait states are used, add 2TOSC x n, where n = number of wait states. 4. Testing is performed down to 8 MHz, although the device is static by design and will typically operate below 1 Hz. 5. Assuming back-to-back bus cycles. 6. 8-bit bus only.
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Table 11. AC Timing Definitions (1) (Continued) Symbol Parameter Min Max Units Notes
The External Memory System Must Meet These Specifications (Continued) TLLGX TLHDV TAVDV TRLDV TRHDZ TRXDX TXHLH TXHLL TLHLH TLHLL TAVLH TAVLL TLLAX TLLRL TRLRH TRHLH TRLAZ TLLWL TQVWH TWLWH TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX BUSWIDTH Hold after ALE/ADV# Low ALE/ADV# High to Input Data Valid Address Valid to Input Data Valid RD# Active to Input Data Valid End of RD# to Input Data Float Data Hold after RD# Inactive 0 TOSC 3TOSC - 55 3TOSC - 55 TOSC - 30 TOSC ns ns ns ns ns ns 3 3
The 8XC196MH will Meet These Specifications XTAL1 Rising Edge to ALE Rising XTAL1 Rising Edge to ALE Falling ALE/ADV# Cycle Time ALE/ADV# High Period Address Valid to ALE/ADV# High Address Valid to ALE/ADV# Low Address Hold after ALE/ADV# Low ALE/ADV# Low to RD# Low RD# Low Period RD# High to ALE/ADV# High RD# Low to Address Float ALE/ADV# Low to WR# Low Data Valid before WR# High WR# Low Period Data Hold after WR# High WR# High to ALE/ADV# High BHE#, INST Hold after WR# High A15:8 Hold after WR# High BHE#, INST Hold after RD# High A15:8 Hold after RD# High TOSC - 10 TOSC - 23 TOSC - 30 TOSC - 25 TOSC - 10 TOSC - 10 TOSC - 30 TOSC - 10 TOSC - 30 TOSC + 15 TOSC - 10 TOSC - 17 TOSC - 17 TOSC - 40 TOSC - 30 TOSC - 5 TOSC TOSC + 25 TOSC + 25 5 20 20 4TOSC TOSC + 10 110 110 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 6 5 3 3 5 3
NOTES: 1. Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, FOSC = 16 MHz. 2. Exceeding the maximum specification causes additional wait states. 3. If wait states are used, add 2TOSC x n, where n = number of wait states. 4. Testing is performed down to 8 MHz, although the device is static by design and will typically operate below 1 Hz. 5. Assuming back-to-back bus cycles. 6. 8-bit bus only.
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
SYSTEM BUS TIMINGS
TOSC XTAL1 TXHLL TLHLH ALE TLHDV TLHLL TLLRL TRLRH TRHLH TXHLH
RD# TAVLH TLLAX TRLDV TRHDZ TRXDX Data
TAVLL BUS
TRLAZ
Address Out TAVDV TLLWL TWLWH
TWHLH
WR# TQVWH TWHQX
BUS
Address Out
Data Out TRHBX TWHBX
Address Out
INST
Valid TRHAX TWHAX
A15:8 (8-bit Bus)
Address Out
A2543-01
Figure 7. System Bus Timing Diagram
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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READY TIMING (ONE WAIT STATE)
TOSC XTAL1
TLHLH + 2TOSC ALE TLLYX(Max) TLLYX(Min) TCLYX(Max) TCLYX(Min) TLLYV READY 16 MHz TAVYV RD# TRLDV + 2TOSC TAVDV + 2TOSC Bus Address Out TWLWH + 2TOSC WR# TRLDV + 2TOSC TQVWH + 2TOSC Bus Address Out Data Out Address Data In 8 MHz TRLRH + 2TOSC
A2544-01
Figure 8. READY Timing Diagram (One Wait State)
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
BUSWIDTH TIMING
TOSC XTAL1
ALE Bus Address Out TAVGV BUSWIDTH TLLGV TLLGX
A2545-01
Data In
Figure 9. BUSWIDTH Timing Diagram
EXTERNAL CLOCK DRIVE
Table 12. External Clock Drive Timing Symbol 1/TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency Oscillator Period (TOSC) High Time Low Time Rise Time Fall Time Min 8 62.5 22 22 10 10 Max 16 125 Units MHz ns ns ns ns ns
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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TXLXH TXHXX 0.7 VCC 0.7 VCC
XLXX
TXHXL
0.7 VCC 0.8 V
T
XTAL1
0.8 V T
XLXL A2578-01
Figure 10. External Clock Drive Waveforms
VCC 4.7k* XTAL1 Clock Driver No Connect 8XC196 Device XTAL2
External Clock Input
Note: *Required if TTL driver is used. Not needed if CMOS driver is used.
A0274-01
Figure 11. External Clock Connections
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
C1 XTAL1 VSS 8XC196 Device XTAL2 C2 Quartz Crystal Note: Keep oscillator components close to the chip and use short, direct traces to XTAL1, XTAL2, and Vss. When using crystals, C1=C220pF. When using ceramic resonators, consult the manufacturer for recommended oscillator circuitry.
A0273-01
Figure 12. External Crystal Connections
3.5 V
2.0 V 0.8 V
Test Points
2.0 V 0.8 V
0.45 V
AC testing inputs are driven at 3.5 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0".
A2120-02
Figure 13. AC Testing Input, Output Waveforms
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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VLOAD + 0.1 V VLOAD VLOAD - 0.1 V Timing Reference Points
VOH - 0.1 V
VOL + 0.1 V
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs 15 with IOL/IOH mA.
A2579-01
Figure 14. Float Waveforms
AC CHARACTERISTICS -- SERIAL PORT, SHIFT REGISTER MODE
Table 13. Serial Port Timing -- Shift Register Mode (Mode 0) Symbol TXLXL Parameter Serial Port Clock Period (Baud-raten 8002H) (Baud-raten = 8001H) Serial Port Clock Low Period (Baud-raten 8002H) (Baud-raten = 8001H) Output Data Setup to Clock High Output Data Hold after Clock High Next Output Data Valid after Clock High Input Data Setup to Clock High Input Data Hold after Clock High Last Clock High to Output Float TOSC + 50 0 TOSC Min 6TOSC 4TOSC 4TOSC - 50 2TOSC - 50 2TOSC - 50 2TOSC - 50 2TOSC + 50 4TOSC + 50 2TOSC + 50 Max Units ns ns ns ns ns ns ns ns ns ns Notes
1, 2
TXLXH
1, 2
TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ
NOTES: 1. n for Baud-raten signifies Serial Port 0 or 1. 2. Maximum Serial Port Mode 0 reception is with Baud-raten 8002H.
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
TXLXL TXDn TQVXH RXDn (Out) RXDn (In)
0 1
TXLXH
2 3
TXHQV
4
TXHQX
5 6
TXHQZ
7
TDVXH
Valid Valid Valid
TXHDX
Valid Valid Valid Valid Valid
A2080-01
Figure 15. Serial Port Waveform -- Shift Register Mode (Mode 0) Table 14. Serial Port Timing -- Mode 4 Symbol TXLXL TXLXX TXHXX TXLXL TXHXL TXLXH TXLQV TXLQX TXHQX TDVXX TXHDH Parameter Serial Port Clock Period (DIR=0) Serial Port Clock Low Period (DIR=0/1) Serial Port Clock High Period (DIR=0/1) Serial Port Clock Period (DIR=1) Serial Clock Falling Time (DIR=1) Serial Clock Rising Time (DIR=1) Clock Low to Output Data Setup Output Data Hold after Clock Low Last Output Data Hold after Clock High (DIR=1) Input Data Setup to Clock Low Invalid Input Data Hold after Clock High 0 13.7TOSC 0 6TOSC Min 16TOSC (TXLXL/2) - 30 (TXLXL/2) - 30 16TOSC 0 0 20 20 7.5TOSC - 50 Max 131072TOSC Units ns ns ns ns ns ns ns ns ns ns ns
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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TXLXL TXLXX SCKn# TXHXX
TDVXX RXDn TXLQV
TXHDH
TXLQX TXHQX
TXDn
A2550-01
Figure 16. Serial Port Waveform -- Mode 4
TXHXX VIH VIL
TXLXH
TXHXL
TXLXX
SCKn#
TXLXL
A2582-01
Figure 17. Serial Port Waveform -- Clock Drive (DIR = 1)
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
BAUD-RATE CLOCK DRIVE TABLE
Table 15. Baud Rate Clock Drive Symbol TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Baud Rate Clock Period Baud Rate Clock High Time Baud Rate Clock Low Time Baud Rate Clock Rise Time Baud Rate Clock Fall Time 2TOSC - 30 2TOSC - 30 20 20 Min Max 4TOSC Units ns ns ns ns ns
TXHXX VIH
TXLXH
TXHXL
BCLKn
VIL
TXLXX
TXLXL
A2551-01
Figure 18. Baud-Rate Clock Drive Waveforms
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A/D SAMPLE AND CONVERSION TIMES
Two parameters, sample time and conversion time, control the time required for an A/D conversion. The sample time is the length of time that the analog input voltage is actually connected to the sample capacitor. If this time is too short, the sample capacitor will not charge completely. If the sample time is too long, the input voltage may change and cause conversion errors. The conversion time is the length of time required to convert the analog input voltage stored on the sample capacitor to a digital value. The conversion time must be long enough for the comparator and circuitry to settle and resolve the voltage. Excessively long conversion times allow the sample capacitor to discharge, degrading accuracy. The AD_TIME register programs the A/D sample and conversion times. Use the TSAM and TCONV specifications in Tables 16 and 18 to determine appropriate values for SAM and CONV; otherwise, erroneous conversion results may occur.
Use the following formulas to determine the SAM and CONV values: T SAM x F OSC - 2 SAM = ---------------------------------------8 CONV = TCONV x F OSC - 3
------------------------------------------- - 1 2xB
where: SAM = 1 to 7 CONV = 2 to 31 TSAM is the sample time, in sec (Tables 16 and 18) TCONV is the conversion time, in sec (Tables 16 and 18) FOSC is the XTAL1 frequency, in MHz B is the number of bits to be converted (8 or 10) When the SAM and CONV values are known, write them to the AD_TIME register. Do not write to this register while a conversion is in progress; the results are unpredictable.
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
AC CHARACTERISTICS -- A/D CONVERTER
Table 16. 10-bit A/D Operating Conditions (1) Symbol TA VCC VREF TSAM TCONV FOSC Description Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency Min - 40 4.50 4.50 1.0 10.0 8 20.0 16 Max + 85 5.50 5.50 Units Notes
C
V V
s s
2 3 3
MHz
NOTES: 1. ANGND and VSS should nominally be at the same potential. 2. VREF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and the analog portion of the converter and input port pins. 3. Program the AD_TIME register to meet the TSAM and TCONV specifications.
Table 17. 10-bit Mode A/D Characteristics Over Specified Operating Conditions (1) Parameter Resolution Absolute Error Full-scale Error Zero Offset Error Nonlinearity Differential Nonlinearity Channel-to-channel Matching Repeatability 0.1 0.25 0.25 0.5 0.25 0.5 1.0 2.0 - 0.75 0 0 3 + 0.75 1 Typical (3) Min 1024 10 0 Max 1024 10 3 Units (2) Levels Bits LSBs LSBs LSBs LSBs LSBs LSBs LSBs Notes
NOTES: 1. Testing is performed with VREF = 5.12 V and FOSC = 16 MHz. 2. An LSB, as used here, has a value of approximately 5 mV. 3. Typical values are based on a limited number of samples and are not guaranteed. Operating conditions for typical values are room temperature and VREF = VCC = 5.5 V. 4. DC to 100 KHz. 5. Multiplexer break-before-make guaranteed. 6. Resistance from device pin, through internal multiplexer, to sample capacitor. 7. These values may be exceeded if the pin current is limited to 2mA. 8. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 9. All conversions were performed with processor in idle mode.
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Table 17. 10-bit Mode A/D Characteristics Over Specified Operating Conditions (1) (Continued) Parameter Temperature Coefficients: Offset Full-scale Differential Nonlinearity Off-isolation Feedthrough VCC Power Supply Rejection Input Series Resistance Voltage on Analog Input Pin Sampling Capacitor DC Input Leakage 3 1.0 0 3 - 60 - 60 750 ANGND - 0.5 1.2K VREF + 0.5 Typical (3) 0.009 0.009 0.009 - 60 Min Max Units (2) LSB/C LSB/C LSB/C dB dB dB
Notes
4, 5 4 6 4 7, 8
V pF
A
NOTES: 1. Testing is performed with VREF = 5.12 V and FOSC = 16 MHz. 2. An LSB, as used here, has a value of approximately 5 mV. 3. Typical values are based on a limited number of samples and are not guaranteed. Operating conditions for typical values are room temperature and VREF = VCC = 5.5 V. 4. DC to 100 KHz. 5. Multiplexer break-before-make guaranteed. 6. Resistance from device pin, through internal multiplexer, to sample capacitor. 7. These values may be exceeded if the pin current is limited to 2mA. 8. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 9. All conversions were performed with processor in idle mode.
Table 18. 8-bit A/D Operating Conditions (1) Symbol TA vCC vREF TSAM TCONV FOSC Description Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency Min - 40 4.50 4.50 1.0 7.0 8 20.0 16 Max + 85 5.50 5.50 Units Notes
C
V V
s s
2 3 3
MHz
NOTES: 1. ANGND and VSS should nominally be at the same potential. 2. VREF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and the analog portion of the converter and input port pins. 3. Program the AD_TIME register to meet the TSAM and TCONV specifications.
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 19. 8-bit Mode A/D Characteristics Over Specified Operating Conditions (1) Parameter Resolution Absolute Error Full-scale Error Zero Offset Error Nonlinearity Differential Nonlinearity Channel-to-channel Matching Repeatability Temperature Coefficients: Offset Full-scale Differential Nonlinearity Off Isolation Feedthrough VCC Power Supply Rejection Input Series Resistance Voltage on Analog Input Pin Sampling Capacitor DC Input Leakage 3 1 0 3 - 60 - 60 750 ANGND - 0.5 1.2K VREF + 0.5 0.25 0.003 0.003 0.003 - 60
0.5
Typical (3)
Min 256 8 0
Max 256 8 1
Units (2) Levels Bits LSBs LSBs LSBs
Notes
0.5 0 - 0.5 0 0 1 + 0.5 1
LSBs LSBs LSBs LSBs LSB/C LSB/C LSB/C dB dB dB V pF
A
4, 5 4 4 6 7, 8
NOTES: 1. Testing is performed with VREF = 5.12 V and FOSC = 16 MHz. 2. An LSB, as used here, has a value of approximately 20 mV. 3. Typical values are based on a limited number of samples and are not guaranteed. Operating conditions for typical values are room temperature and VREF = VCC = 5.5 V. 4. DC to 100 KHz. 5. Multiplexer break-before-make guaranteed. 6. Resistance from device pin, through internal multiplexer, to sample capacitor. 7. These values may be exceeded if the pin current is limited to 2mA. 8. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 9. All conversions were performed with processor in idle mode.
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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OTPROM SPECIFICATIONS
Table 20. Programming Operating Conditions Symbol TA vCC vREF VPP VEA FOSC Description Ambient Temperature Supply Voltage During Programming Reference Supply Voltage During Programming Programming Voltage EA Pin Voltage Oscillator Frequency During Auto and Slave Mode Programming Oscillator Frequency During Run-Time Programming Min 20 4.50 4.50 12.25 12.25 6 6 Max 30 5.50 5.50 12.75 12.75 8 12 Units Notes
C
V V V V MHz MHz 3 3 2 2
NOTES: 1. VCC and VREF should be at nominally the same voltage during programming. 2. If VPP and VEA exceed the maximum specification, the device may be damaged. 3. VSS and ANGND should be at nominally the same potential (0 volts). 4. Load capacitance during auto and slave mode programming = 150 pF.
Table 21. AC OTPROM Programming Characteristics Symbol TAVLL TLLAX TDVPL TPLDX TLLLH TPLPH TPHLL TPHDX TPHPL TLHPL TPLDV TSHLL TPHIL TILIH Description Address Setup Time Address Hold Time Data Setup Time Data Hold Time PALE# Pulse Width PROG# Pulse Width (1) PROG# High to Next PALE# Low Word Dump Hold Time PROG# High to Next PROG# Low PALE# High to PROG# Low PROG# Low to Word Dump Valid RESET# High to First PALE# Low PROG# High to AINC# Low AINC# Pulse Width 1100 0 240 220 220 50 Min 0 100 0 400 50 50 220 50 Max Units TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC
NOTE: 1. This specification is for Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm explained in the User's Manual.
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER Table 21. AC OTPROM Programming Characteristics (Continued)
Symbol TILVH TILPL TPHVL
Description PVER Hold after AINC# Low AINC# Low to PROG# Low PROG# High to PVER Valid
Min 50 170
Max
Units TOSC TOSC
220
TOSC
NOTE: 1. This specification is for Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm explained in the User's Manual.
Table 22. DC OTPROM Programming Characteristics Symbol IPP NOTE: Parameter VPP Supply Current (when programming) Min Max 100 Units mA
Do not apply VPP until VCC is stable and within specifications and the oscillator/clock has stabiliized. Otherwise, the device may be damaged.
OTPROM PROGRAMMING WAVEFORMS
RESET# TAVLL PORTS 3/4 TSHLL PALE# TLLLH PROG# PVER TPHVL
A2549-01 Address/Command Data Address/Command
TLLAX
TDVPL TPLDX TPHLL
TLHPL
TPLPH
Figure 19. Slave Programming Mode Data Program Mode with Single Program Pulse
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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RESET# Address PORTS 3/4 Address/Command TSHLL TPLDV Ver Bits/Word Dump TPHDX Address + 2 Ver Bits/Word Dump TPLDV TPHDX PALE#
PROG# TILPL AINC# Note: P3.0 must be low ("0")
A2546-01
TPHPL
Figure 20. Slave Programming Mode in Word Dump with Autoincrement Timing
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTOINCREMENT
RESET# Address PORTS 3/4 PALE# TPHPL PROG# P1 PN TILVH PVER
Valid for P1 Valid for PN
Address Data
Address + 2 Data
Address/Command
Data
TILPL
TILIH AINC# TPHIL
A2547-01
Figure 21. Slave Programming Mode in Data Program with Repeated Program Pulse and Autoincrement
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
8XC196MC/MD TO 8XC196MH DESIGN CONSIDERATIONS
The 8XC196MH is not pin compatible with the 8XC196MC or the 8XC196MD. Be aware that signal multiplexing sometimes differs between the 8XC196MH and the 8XC196MC/MD. For example, P2.7 is multiplexed with COMP3 on the 8XC196MC/MD and with SCLK1# and BCLK1 on the 8XC196MH.
DATA SHEET REVISION HISTORY
The -003 revisions were made due to the changes required for the lead free initiative. To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
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