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KS8997
Micrel
KS8997
8-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 1.07
General Description
The KS8997 contains eight 10/100 physical layer transceivers, eight MAC (Media Access Control) units with an integrated layer 2 switch. The device runs as an eight port integrated switch The KS8997 is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through I/O strapping or EEPROM programming at system reset time. On the media side, the KS8997 supports 10BaseT and 100BaseTX through auto-negotiation as specified by the IEEE 802.3 committee. Physical signal transmission and reception are enhanced through use of analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. Data sheets and support documentation can be found on Micrel's web site at www.micrel.com.
Features
* 8-port 10/100 integrated switch with 8 physical layer transceivers * 32Kx32 of SRAM on chip for frame buffering * 2.0Gbps high performance memory bandwidth * 10BaseT and 100BaseTX modes of operation * Superior analog technology for reduced power and die size * Single 2.0V power supply with options for 2.5V and 3.3V I/O * 900mA (1.80 W) including physical transmit drivers * Supports port based VLAN * Supports DiffServ priority, 802.1p based priority or port based priority * Indicators for link, activity, full/half-duplex and speed * Unmanaged operation via strapping or EEPROM at system reset time
Functional Diagram
Look Up Engine (1K Entries)
Queue Priority Management
Buffer Management
SRAM Buffers
FIFO, Flow Control, VLAN and Priority Processing
Media Access Controller 1
Media Access Controller 2
Media Access Controller 3
Media Access Controller 4
Media Access Controller 5
Media Access Controller 6
Media Access Controller 7 Physical Layer Transceiver 7
RXP[7], RXM[7] RXP[8], RXM[8] TXP[7], TXM[7]
Physical Layer Transceiver 1
Physical Layer Transceiver 2
Physical Layer Transceiver 3
Physical Layer Transceiver 4
Physical Layer Transceiver 5
Physical Layer Transceiver 6
RXP[1], RXM[1]
RXP[2], RXM[2]
RXP[3], RXM[3]
RXP[4], RXM[4]
RXP[5], RXM[5]
RXP[6], RXM[6]
TXP[2], TXM[2]
TXP[3], TXM[3]
TXP[1], TXM[1]
TXP[5], TXM[5]
TXP[4], TXM[4]
TXP[6], TXM[6]
EEPROM / Interface
SCL SDA
LED and Programming Interface
LED[1][3,2,0] LED[2][3,2,0] LED[3][3,2,0] LED[4][3,2,0] LED[5][3,2,0] LED[6][3,2,0] LED[7][3,2,0] LED[8][3,2,0]
Micrel, Inc. * 1849 Fortune Drive * San Jose, CA 95131 * USA * tel + 1 (408) 944-0800 * fax + 1 (408) 944-0970 * http://www.micrel.com
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TXP[8], TXM[8]
Physical Layer Transceiver 8
Media Access Controller 8
KS8997
KS8997
Micrel
Features (continued)
* Hardware based 10/100, full/half, flow control and auto negotiation * Wire speed reception and transmission * Integrated address look-up engine, supports 1K absolute MAC addresses * Automatic address learning, address aging and address migration * Broadcast storm protection * Full-duplex IEEE 802.3x flow control * Half-duplex back pressure flow control * Comprehensive LED support * Supports MDI/MDI-X auto crossover * Commercial temperature range: 0C to +70C * Available in 128-pin PQFP package
Applications
* Small workgroup switches * VoIP infrastructure switches
Ordering Information
Part Number KS8997 Temperature Range 0C to +70C Package 128-Pin PQFP
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Revision History
Revision 1.00 1.01 Date 11/27/00 04/02/01 Summary of Changes Document origination Update maximum frame size Update EEPROM priority descriptions Update I/O descriptions Update Electrical Characteristics Add MDI/MDI-X description Change electrical requirements Correct I/O descriptions Update PLL clock information Correct LED[1:8][3] mode 2 description Convert to new format.
1.02 1.03 1.04 1.05 1.06 1.07
05/11/01 06/22/01 06/25/01 07/25/01 05/29/02 8/29/03
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Table of Contents
System Level Applications .............................................................................................................................................................. 6 Pin Description I/O Grouping .............................................................................................................................................................................. 7 ............................................................................................................................................................................ 10
I/O Descriptions ............................................................................................................................................................................ 11 Pin Configuration ........................................................................................................................................................................... 14 Functional Overview: Physical Layer Transceiver ..................................................................................................................... 15 100BaseTX Transmit ............................................................................................................................................................... 15 100BaseTX Receive ................................................................................................................................................................ 15 PLL Clock Synthesizer ............................................................................................................................................................ 15 Scrambler/De-scrambler (100BaseTX only) ............................................................................................................................ 15 10BaseT Transmit ................................................................................................................................................................... 15 10BaseT Receive .................................................................................................................................................................... 15 Power Management ................................................................................................................................................................ 15 Power Save Mode ........................................................................................................................................................... 15 MDI/MDI-X Auto Crossover ..................................................................................................................................................... 15 Auto-Negotiation ...................................................................................................................................................................... 16 Functional Overview: Switch Core .............................................................................................................................................. 17 Address Look-Up ..................................................................................................................................................................... 17 Learning Migration Aging ............................................................................................................................................................................ 17 ............................................................................................................................................................................ 17 ............................................................................................................................................................................ 17
Forwarding ............................................................................................................................................................................ 17 Switching Engine ..................................................................................................................................................................... 17 MAC Operation ........................................................................................................................................................................ 17 Inter Packet Gap (IPG) ................................................................................................................................................... 17 Backoff Algorithm ............................................................................................................................................................ 17 Late Collision .................................................................................................................................................................. 18 Illegal Frames ................................................................................................................................................................. 18 Flow Control .................................................................................................................................................................... 18 Half-Duplex Back Pressure ............................................................................................................................................. 18 Broadcast Storm Protection ............................................................................................................................................ 18 Prorammable Features .................................................................................................................................................................. 18 Priority Schemes ..................................................................................................................................................................... 18 Per Port Method ...................................................................................................................................................................... 18 802.1p Method ......................................................................................................................................................................... 18 IPv4 DSCP Method ................................................................................................................................................................. 19 Other Priority Considerations .................................................................................................................................................. 19 VLAN Operation ............................................................................................................................................................................ 20 Station MAC Address .................................................................................................................................................................... 20 EEPROM Operation ........................................................................................................................................................................ 21 EEPROM Memory Map ........................................................................................................................................................... 21 General Conrol Register ................................................................................................................................................. 21 Priority Classification Control: 802.1p Tag Field ............................................................................................................ 21 Port 1 Control Register ................................................................................................................................................... 21 Port 2 Control Register ................................................................................................................................................... 22 Port 3 Control Register ................................................................................................................................................... 22 Port 4 Control Register ................................................................................................................................................... 23 Port 5 Control Register ................................................................................................................................................... 23 Port 6 Control Register ................................................................................................................................................... 23 Port 7 Control Register ................................................................................................................................................... 24
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Port 8 Control Register ................................................................................................................................................... 24 Reserved Register .......................................................................................................................................................... 24 Port 1 VLAN Mask Register ............................................................................................................................................ 25 Port 2 VLAN Mask Register ............................................................................................................................................ 25 Port 3 VLAN Mask Register ............................................................................................................................................ 25 Port 4 VLAN Mask Register ............................................................................................................................................ 26 Port 5 VLAN Mask Register ............................................................................................................................................ 26 Port 6 VLAN Mask Register ............................................................................................................................................ 27 Port 7 VLAN Mask Register ............................................................................................................................................ 27 Port 8 VLAN Mask Register ............................................................................................................................................ 28 Reserved Register .......................................................................................................................................................... 28 Port 1 VLAN Tag Insertion Value Registers .................................................................................................................... 28 Port 2 VLAN Tag Insertion Value Registers .................................................................................................................... 28 Port 3 VLAN Tag Insertion Value Registers .................................................................................................................... 28 Port 4 VLAN Tag Insertion Value Registers .................................................................................................................... 29 Port 5 VLAN Tag Insertion Value Registers .................................................................................................................... 29 Port 6 VLAN Tag Insertion Value Registers .................................................................................................................... 29 Port 7 VLAN Tag Insertion Value Registers .................................................................................................................... 29 Port 8 VLAN Tag Insertion Value Registers .................................................................................................................... 29 Reserved Register .......................................................................................................................................................... 29 Diff Serve Code Point Registers ..................................................................................................................................... 29 Station MAC Address Registers ..................................................................................................................................... 29
Absolute Maximum Ratings .......................................................................................................................................................... 30 Operating Ratings .......................................................................................................................................................................... 30 Electrical Characteristics .............................................................................................................................................................. 30 Timing Diagrams ............................................................................................................................................................................ 32 Reference Circuit ........................................................................................................................................................................... 32 Qualified Magnetic Lists ................................................................................................................................................................ 33 4B/5B Coding .................................................................................................................................................................................. 34 MLT Coding .................................................................................................................................................................................... 35 MAC Frame for 802.3 ..................................................................................................................................................................... 35 Selection of Isolation Transformers ............................................................................................................................................. 36 Selection of Reference Oscillator/Crystal .................................................................................................................................... 36 Package Information ...................................................................................................................................................................... 37
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configuration, built in frame buffering, VLAN abilities and traffic priority control. An application is depicted below.
System Level Application
The KS8997 can be configured to fit in an eight port 10/100 application. The major benefits of using the KS8997 are the lower power consumption, unmanaged operation, flexible
KS8997 8 Port Switch with PHY
8X Transformer Interface 8 Port Stand Alone
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Pin Description
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Note 1.
Pin Name VDD_RX GND_RX GND_RX VDD_RX RXP[3] RXM[3] GND-ISO TXP[3] TXM[3] GND_TX VDD_TX TXP[4] TXM[4] GND_TX RXP[4] RXM[4] GND_RX VDD_RX ISET GND-ISO VDD_RX GND_RX RXP[5] RXM[5] GND_TX TXP[5] TXM[5] VDD_TX GND_TX TXP[6] TXM[6] GND-ISO RXP[6] RXM[6] VDD_RX GND_RX GND_RX VDD_RX
Type(Note 1) Pwr Gnd Gnd Pwr I I Gnd O O Gnd Pwr O O Gnd I I Gnd Pwr
Port
Pin Function 2.0V for equalizer Ground for equalizer Ground for equalizer 2.0V for equalizer
3 3
Physical receive signal + (differential) Physical receive signal - (differential) Analog ground
3 3
Physical transmit signal + (differential) Physical transmit signal - (differential) Ground for transmit circuitry 2.0V for transmit circuitry
4 4
Physical transmit signal + (differential) Physical transmit signal - (differential) Ground for transmit circuitry
4 4
Physical receive signal + (differential) Physical receive signal - (differential) Ground for equalizer 2.0V for equalizer Set physical transmit output current
Gnd Pwr Gnd I I Gnd O O Pwr Gnd O O Gnd I I Pwr Gnd Gnd Pwr 6 6 6 6 5 5 5 5
Analog ground 2.0V for equalizer Ground for equalizer Physical receive signal + (differential) Physical receive signal - (differential) Ground for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) 2.0V for transmit circuitry Ground for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) Analog ground Physical receive signal + (differential) Physical receive signal - (differential) 2.0V for equalizer Ground for equalizer Ground for equalizer 2.0V for equalizer
Pwr = power supply Gnd = ground I = input O = output I/O = bi-directional
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Pin Number 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77
Note 1.
Micrel
Pin Name GND-ISO RXP[7] RXM[7] GND_TX TXP[7] TXM[7] VDD_TX VDD_TX TXP[8] TXM[8] GND_TX RXP[8] RXM[8] GND_RX VDD_RX GND_RCV VDD_RCV GND_RCV VDD_RCV RLPBK T[1] EN1P SDA SCL VDD GND VDD-IO GND GND VDD BIST RST# LED[1][3] LED[1][2] LED[1][0] LED[2][3] LED[2][2] LED[2][0] VDD-IO Type(Note 1) Gnd I I Gnd O O Pwr Pwr O O Gnd I I Gnd Pwr Gnd Pwr Gnd Pwr I I I I/O I/O Pwr Gnd Pwr Gnd Gnd Pwr I I I/O I/O I/O I/O I/O I/O Pwr 1 1 1 2 2 2 8 8 8 8 7 7 7 7 Port Pin Function Analog ground Physical receive signal + (differential) Physical receive signal - (differential) Ground for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) 2.0V for transmit circuitry 2.0V for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) Ground for transmit circuitry Physical receive signal + (differential) Physical receive signal - (differential) Ground for equalizer 2.0V for equalizer Ground for clock recovery circuit 2.0V for clock recovery circuit Ground for clock recovery circuit 2.0V for clock recovery circuit Enable loop back for testing Factory test pin - float for normal operation Enable 802.1p for all ports Serial data from EEPROM or processor Clock for EEPROM or from processor 2.0V for core digital circuitry Ground for core digital circuitry 2.0V, 2.5V or 3.3V for I/O circuitry Ground for digital circuitry Ground for core digital circuitry 2.0V for core digital circuitry Built-in self test-tie low for normal operation Reset LED indicator 3 LED indicator 2 LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 0 2.0V, 2.5V or 3.3V for I/O circuitry
Pwr = power supply Gnd = ground I = input O = output I/O = bi-directional
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Pin Number 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116
Note 1.
Micrel
Pin Name GND LED[3][3] LED[3][2] LED[3][0] LED[4][3] LED[4][2] LED[4][0] VDD GND LED[5][3] LED[5][2] LED[5][0] LED[6][3] LED[6][2] LED[6][0] LED[7][3] LED[7][2] VDD-IO LED[7][0] LED[8][3] LED[8][2] LED[8][0] GND GND VDD MODESEL[1] MODESEL[0] T[5] X1 X2 VDD_PLLTX GND_PLLTX VDD_RCV GND_RCV VDD_RCV GND_RCV VDD_RX GND_RX RXP[1] Type(Note 1) Gnd I/O I/O I/O I/O I/O I/O Pwr Gnd I/O I/O I/O I/O I/O I/O I/O I/O Pwr I/O I/O I/O I/O Gnd Gnd Pwr I I I I O Pwr Gnd Pwr Gnd Pwr Gnd Pwr Gnd I 1 7 8 8 8 5 5 5 6 6 6 7 7 3 3 3 4 4 4 Port Pin Function Ground for digital circuitry LED indicator 3 LED indicator 2 LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 0 2.0V for core digital circuitry Ground for core digital circuitry LED indicator 3 LED indicator 2 LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 0 LED indicator 3 LED indicator 2 2.0V, 2.5V or 3.3V for I/O circuitry LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 0 Ground for digital circuitry Ground for core digital circuitry 2.0V for core digital circuitry Selects LED modes Selects LED modes Factory test pin - float for normal operation Crystal or clock input Connect to crystal 2.0V for phase locked loop circuit Ground for phase locked loop circuit 2.0V for clock recovery circuit Ground for clock recovery circuit 2.0V for clock recovery circuit Ground for clock recovery circuit 2.0V for equalizer Ground for equalizer Physical receive signal + (differential)
Pwr = power supply Gnd = ground I = input O = output I/O = bi-directional
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Pin Number 117 118 119 120 121 122 123 124 125 126 127 128
Note 1.
Micrel
Pin Name RXM[1] GND_TX TXP[1] TXM[1] VDD_TX VDD_TX TXP[2] TXM[2] GND_TX RXP[2] RXM[2] GND-ISO Type(Note 1) I Gnd O O Pwr Pwr O O Gnd I I Gnd 2 2 2 2 1 1 Port 1 Pin Function Physical receive signal - (differential) Ground for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) 2.0V for transmit circuitry 2.0V for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) Ground for transmit circuitry Physical receive signal + (differential) Physical receive signal - (differential) Analog ground
Pwr = power supply Gnd = ground I = input O = output I/O = bi-directional
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I/O Grouping
Group Name PHY IND UP CTRL TEST PWR/GND Description Physical Interface LED Indicators Unmanaged Programmable Control and Miscellaneous Test (Factory) Power and Ground
I/O Descriptions
Group PHY I/O Names RXP[1:8] RXM[1:8] TXP[1:8] TXM[1:8] ISET Active Status Analog Analog Analog Description(Note 1) Differential inputs (receive) for connection to media transformer. Differential outputs (transmit) for connection to media transformer. Transmit Current Set. Connect an external reference resistor to set transmitter output current. This pin is connected to a 1% 3k resistor to ground if a transformer with 1:1 turn ratio is used. Output (after reset) Mode 0: Speed (on = 100/off = 10) Mode 1: Reserve Mode 2: Collision (on = collision/off = no collision) Mode 3: Speed (on = 100/off = 10) Output (after reset) Mode 0: Collision (on = collision/off = no collision) Mode 1: Reserve Mode 2: Link activity (10Mb mode) Mode 3: Full Duplex + Collision (constant on = full-duplex; intermittent on = collision; off = half-duplex with no collision) Output (after reset) Mode 0: Link + Activity Mode 1: Reserve Mode 2: Link activity (100Mb mode) Mode 3: Link + Activity
IND
LED[1:8][0]
L
LED[1:8][2]
L
LED[1:8][3]
L
Note: Mode is set by MODESEL[1:0] ; See description in UP (unmanaged programming) section
UP MODESEL[1:0] H Mode select at reset time. LED mode is selected by using the table below. MODESEL [1] [0] 0 0 1 1 LED[1][3] LED[1][2] LED[1][0] LED[2][3] LED[2][2]
Note 1.
Operation LED mode 0 LED mode 1 LED mode 2 LED mode 3
0 1 0 1
Reserved - use float configuration Reserved - use float configuration Reserved - use float configuration Reserved - use float configuration Reserved - use float configuration
All unmanaged programming takes place at reset time only. For unmanaged programming: F = Float, D = Pull-down, U = Pull-up, H = Hold pin state after reset.
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Group I/O Names LED[2][0] LED[3][3] LED[3][2] LED[3][0] LED[4][3] LED[4][2] LED[4][0] LED[5][3] LED[5][2] LED[5][0] LED[6][3] Active Status Description(Note 1) Reserved - use float configuration Reserved - use float configuration Reserved - use float configuration Reserved - use float configuration Reserved - use float configuration Reserved - use float configuration Reserved - use float configuration Reserved - use float configuration Reserved - use float configuration Reserved - use float configuration Programs back-off aggressiveness for half-duplex mode. D = Less aggressive back-off F/U = More aggressive back-off (default) LED[6][2] Programs retries for frames that encounter collisions. D = Drop frame after 16 collisions F/U = Continue sending frame regardless of the number of collisions (default) LED[6][0] LED[7][3] Reserved - use float configuration Programs flow control. D = No flow control F/U = Flow control enabled (default) LED[7][2] Programs broadcast storm protection. D = 5% broadcast frames allowed F/U = Unlimited broadcast frames (default) LED[7][0] LED[8][3] Reserved - use float configuration Programs address aging. D = Aging disabled F/U = Enable 5 minute aging (default) LED[8][2] Programs frame length enforcement. D = Max length for VLAN is 1522 bytes and without VLAN is 1518 bytes F/U = Max length is 1536 bytes (default) LED[8][0] Programs half-duplex back pressure. D = No half-duplex back pressure F/U = Half duplex back pressure enabled (default) CTRL EN1P H
Micrel
Enable 802.1p for all ports: this enables QoS based on the priority field in the layer 2 header. 0 = 802.1p selected by port in EEPROM 1 = Use 802.1p priority field unless disabled in EEPROM
Note: This is also controlled by the EEPROM registers (registers 4-11 bit 4). The values in the EEPROM supercede this pin. Also, if the priority selection is unaltered in the EEPROM registers (register 3 bits 0-7) then values of '100' and above are considered high priorty and values of '011' and below are low priority.
X1 X2 SCL SDA RST#
Note 1.
Clock Clock Clock
External crystal or clock input Used when other polarity of crystal is needed. This is unused for a normal clock input. Clock for EEPROM Serial data for EEPROM
L
System reset
All unmanaged programming takes place at reset time only. For unmanaged programming: F = Float, D = Pull-down, U = Pull-up, H = Hold pin state after reset. See "Reference Circuits" section.
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Group TEST I/O Names T[1], T[5] RLPBK BIST PWR/GND VDD_RX GND_RX VDD_TX GND_TX VDD_RCV GND_RCV VDD_PLLTX GND_PLLTX GND-ISO VDD VDD-IO GND
Note 1.
Micrel
Active Status Description(Note 1) Factory test inputs: leave open (float) for normal operation H H Factory test input: tie low for normal operation Factory test input: tie low for normal operation 2.0V for equalizer Ground for equalizer 2.0V for transmit circuitry Ground for transmit circuitry 2.0V for clock recovery circuitry Ground for clock recovery 2.0V for phase locked loop circuitry Ground for phase locked loop circuitry Analog ground 2.0V for core digital circuitry 2.0V, 2.5V or 3.3V digital for I/O circuitry Ground for digital circuitry
All unmanaged programming takes place at reset time only. For unmanaged programming: F = Float, D = Pull-down, U = Pull-up, H = Hold pin state after reset. See "Reference Circuits" section.
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MODESEL[1] MODESEL[0] T[5] X1 X2 VDD_PLLTX GND_PLLTX VDD_RCV GND_RCV VDD_RCV GND_RCV VDD_RX GND_RX RXP[1] RXM[1] GND_TX TXP[1] TXM[1] VDD_TX VDD_TX TXP[2] TXM[2] GND_TX RXP[2] RXM[2] GND-ISO 103 1
KS8997
Pin Configuration
128-Pin PQFP (PQ)
14
39
65
VDD_RX GND_RX GND_RX VDD_RX RXP[3] RXM[3] GND-ISO TXP[3] TXM[3] GND_TX VDD_TX TXP[4] TXM[4] GND_TX RXP[4] RXM[4] GND_RX VDD_RX ISET GND-ISO VDD_RX GND_RX RXP[5] RXM[5] GND_TX TXP[5] TXM[5] VDD_TX GND_TX TXP[6] TXM[6] GND-ISO RXP[6] RXM[6] VDD_RX GND_RX GND_RX VDD_RX
VDD GND GND LED[8][0] LED[8][2] LED[8][3] LED[7][0] VDD-IO LED[7][2] LED[7][3] LED[6][0] LED[6][2] LED[6][3] LED[5][0] LED[5][2] LED[5][3] GND VDD LED[4][0] LED[4][2] LED[4][3] LED[3][0] LED[3][2] LED[3][3] GND VDD-IO LED[2][0] LED[2][2] LED[2][3] LED[1][0] LED[1][2] LED[1][3] RST# BIST VDD GND GND VDD-IO
GND VDD SCL SDA EN1P T[1] RLPBK VDD_RCV GND_RCV VDD_RCV GND_RCV VDD_RX GND_RX RXM[8] RXP[8] GND_TX TXM[8] TXP[8] VDD_TX VDD_TX TXM[7] TXP[7] GND_TX RXM[7] RXP[7] GND-ISO
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Functional Overview: Physical Layer Transceiver
100BaseTX Transmit
The 100BaseTX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 3.01k resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-shaped 10BaseT output is also incorporated into the 100BaseTX transmitter.
100BaseTX Receive
The 100BaseTX receiver function performs adaptive equalization, DC restoration, MLT3 to NRZI conversion, data and clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding and serial to parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then it tunes itself for optimization. This is an ongoing process and can self adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KS8997 generates 125MHz, 62MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal.
Scrambler/De-Scrambler (100BaseTX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit nonrepetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter.
10BaseT Transmit
The output 10BaseT driver is incorporated into the 100BaseT driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude.
10BaseT Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8997 decodes a data frame. The receiver clock is maintained active during idle periods in between data reception.
Power Management
Power Save Mode
The KS8997 will turn off everything except for the Energy Detect and PLL circuits when the cable is not installed on an individual port basis. In other words, the KS8997 will shutdown most of the internal circuits to save power if there is no link.
MDI/MDI-X Auto Crossover
The KS8997 supports MDI/MDI-X auto crossover. This facilitates the use of either a straight connection CAT-5 cable or a crossover CAT-5 cable. The auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmit and receive pairs from the Micrel device. This can be highly useful when end users are unaware of cable types and can also save on an additional uplink configuration connection. The auto MDI/MDI-X is achieved by the Micrel device listening for the far end transmission channel and assigning transmit/ receive pairs accordingly.
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Auto-Negotiation
The KS8997 conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows UTP (Unshielded Twisted Pair) link partners to select the best common mode of operation. In auto-negotiation the link partners advertise capabilities across the link to each other. If auto-negotiation is not supported or the link partner to the KS8997 is forced to bypass auto-negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto-negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. The flow for the link set up is depicted below. Note that the KS8997 only supports auto-negotiation and not forced modes.
Start Auto Negotiation
Force Link Setting
No
Parallel Operation
Yes
Bypass Auto-Negotiation and Set Link Mode
Attempt Auto-Negotiation
Listen for 100BaseTX Idles
Listen for 10BaseT Link Pulses
No
Join Flow
Link Mode Set ?
Yes
Link Mode Set
Figure 1. Auto-Negotiation
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Functional Overview: Switch Core
Address Look-Up
The internal look-up table stores MAC addresses and their associated information. It contains 1K full CAM with 48-bit address plus switching information. The KS8997 is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup tables which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn.
Learning
The internal look-up engine will update its table with a new entry if the following conditions are met: * The received packet's SA does not exist in the look-up table. * The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will insert the qualified SA into the table, along with the port number, time stamp. If the table is full, the last entry of the table will be deleted first to make room for the new entry.
Migration
The internal look-up engine also monitors whether a station is moved. If it happens, it will update the table accordingly. Migration happens when the following conditions are met: * The received packet's SA is in the table but the associated source port information is different. * The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will update the existing record in the table with the new source port information.
Aging
The look-up engine will update time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will then remove the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging records. The aging period is 300 seconds. This feature can be enabled or disabled by external pull-up or pull-down resistors.
Forwarding
The KS8997 will forward packets as follows: * If the DA look-up results is a "match", the KS8997 will use the destination port information to determine where the packet goes. * If the DA look-up result is a "miss", the KS8997 will forward the packet to all other ports except the port that received the packet. * All the multicast and broadcast packets will be forwarded to all other ports except the source port. The KS8997 will not forward the following packets: * Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors. * 802.3x pause frames. The KS8997 will intercept these packets and do the appropriate actions. * "Local" packets. Based on destination address (DA) look-up. If the destination port from the look-up table matches the port where the packet was from, the packet is defined as "local".
Switching Engine
The KS8997 has a very high performance switching engine to move data to and from the MAC's, packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KS8997 has an internal buffer for frames that is 32Kx32 (128KB). This resource could be shared between the nine ports and is programmed at system reset time by using the unmanaged program mode (I/O strapping). Each buffer is sized at 128B and therefore there are a total of 1024 buffers available. The buffers are adaptively allocated up to 512 to a single port based on loading.
MAC (Media Access Controller) Operation
The KS8997 strictly abides by IEEE 802.3 standards to maximize compatibility.
Inter Packet Gap (IPG)
If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN.
Backoff Algorithm
The KS8997 implements the IEEE Std 802.3 binary exponential back-off algorithm, and optional "aggressive mode" back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration. August 2003 17 KS8997
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Late Collision
If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped.
Illegal Frames
The KS8997 discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes. Since the KS8997 supports VLAN tags, the maximum sizing is adjusted when these tags are present.
Flow Control
The KS8997 supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KS8997 receives a pause control frame, the KS8997 will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being flow controlled), only flow control packets from the KS8997 will be transmitted. On the transmit side, the KS8997 has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KS8997 will flow control a port, which just received a packet, if the destination port resource is being used up. The KS8997 will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8997 will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent flow control mechanism from being activated and deactivated too many times. The KS8997 will flow control all ports if the receive queue becomes full.
Half-Duplex Back Pressure
Half duplex back pressure option (Note: not in 802.3 standards) is also provided. The activation and deactivation conditions are the same as the above in full-duplex mode. If back pressure is required, the KS8997 will send preambles to defer other stations' transmission (carrier sense deference). To avoid jabber and excessive deference defined in 802.3 standard, after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in carrier sense deferred state. If the port has packets to send during a back pressure situation, the carrier sense type back pressure will be interrupted and those packets will be transmitted instead. If there are no more packets to send, carrier sense type back pressure will be active again until switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets.
Broadcast Storm Protection
The KS8997 has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets will be forwarded to all ports except the source port, and thus will use too many switch resources (bandwidth and available space in transmit queues). The KS8997 will discard broadcast packets if the number of those packets exceeds the threshold (configured by strapping during reset and EEPROM settings) in a preset period of time. If the preset period expires it will then resume receiving broadcast packets until the threshold is reached. The options are 5% of network line rate for the maximum broadcast receiving threshold or unlimited (feature off).
Programmable Features
Priority Schemes The KS8997 can determine priority through three different means at the ingress point. The first method is a simple per port method, the second is via the 802.1p frame tag and the third is by viewing the DSCP (TOS) field in the IPv4 header. Of course for the priority to be effective, the high and low priority queues must be enabled on the destination port or egress point. Per Port Method General priority can be specified on a per port basis. In this type of priority all traffic from the specified input port is considered high priority in the destination queue. This can be useful in IP phone applications mixed with other data types of traffic where the IP phone connects to a specific port. The IP phone traffic would be high priority (outbound) to the wide area network. The inbound traffic to the IP phone is all of the same priority to the IP phone. 802.1p Method This method works well when used with ports that have mixed data and media flows. The inbound port examines the priority field in the tag and determines the high or low priority. Priority profiles are setup in the Priority Classification Control in the "EEPROM Memory Map" section.
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IPv4 DSCP Method This is another per frame way of determining outbound priority. The DSCP (Differentiated Services Code Point- RFC#2474) method uses the TOS field in the IP header to determine high and low priority on a per code point basis. Each fully decoded code point can have either a high or low priority. A larger spectrum of priority flows can be defined with this larger code space. More specific to implementation, the most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is compared against the corresponding bit in the DSCP register. If the register bit is a 1, the priority is high and if 0, the priority is low. Other Priority Considerations When setting up the priority scheme, one should consider other available controls to regulate the traffic. One of these is Priority Control Scheme (register 2 bits 2-3) which controls the interleaving of high and low priority frames. Options allow from a 2:1 ratio up to a setting that sends all the high priority first. This setting controls all ports globally. Another global feature is Priority Buffer Reserve (register 2 bit 1). If this is set, there is a 6KB (10%) buffer dedicated to high priority traffic, otherwise if cleared the buffer is shared between all traffic. On an individual port basis there are controls that enable DSCP, 802.1p, port based and high/low priority queues. These are contained in registers 4-11 bits 5-3 and 0. It should be noted that there is a special pin that generally enables the 802.1p priority for all ports (pin 60). When this pin is active (high) all ports will have the 802.1p priority enabled unless specifically disabled by EEPROM programming (bit 4 of registers 4-11). Default high priority is a value of '100' and above in the VLAN tag with low priority being a value of '011' and below. The table below briefly summarizes priority features. For more detailed settings see "EEPROM Memory Map" section.
Register(s) Bit(s) Global/Port Description
General
2 2 4-11 3-2 1 0 Global Global Port Priority Control Scheme: Transmit buffer high/low interleave control Priority Buffer Reserve: Reserves 6KB of the buffer for high priority traffic Enable Port Queue Split: Splits the transmit queue on the desired port for high and low priority traffic
DSCP Priority
4-11 40-47 5 7-0 Port Global Enable Port DSC: Looks at DSCP field in IP header to decide high or low priority DSCP Priority Points: Fully decoded 64 bit register used to determine priority from DSCP field (6 bits) in the IP header 802.1p Priority 4-11 3 4 7-0 Port Global Enable Port 802.1p Priority: Uses the 802.1p priority tag (3 bits) to determine frame priority Priority Classification: Determines which tag values have high priority Per Port Priority 4-11 3 Port Enable Port Priority: Determines which ports have high priority traffic
Table 1. Priority Control
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VLAN Operation
The VLAN's are setup by programming the VLAN Mask Registers in the "EEPROM Memory Map" section. The perspective of the VLAN is from the input port and which output ports it sees directly through the switch. For example if port 1 only participated in a VLAN with ports 2 and 8 then one would set bits 0 and 6 in register 13 (Port 1 VLAN Mask Register). Note that different ports can be setup independently. An example of this would be where a router is connected to port 8 and each of the other ports would work autonomously. In this configuration ports 1 through 7 would only set the mask for port 8 and port 8 would set the mask for ports 1 through 7. In this way the router could see all ports and each of the other individual ports would only communicate with the router. All multicast and broadcast frames adhere to the VLAN configuration. Unicast frame treatment is a function of register 2 bit 0. If this bit is set then unicast frames only see ports within their VLAN. If this bit is cleared unicast frames can traverse VLAN's. VLAN tags can be added or removed on a per port basis. Further, there are provisions to specify the tag value to be inserted on a per port basis. The table below briefly summarizes VLAN features. For more detailed settings see "EEPROM Memory Map" section.
Register(s) 4-11 4-11 2 13-20 22-38 Bit(s) 2 1 0 7-0 7-0 Global/Port Port Port Global Port Port Description Insert VLAN Tags: If specified, will add VLAN tags to frames without existing tags Strip VLAN Tags: If specified, will remove VLAN tags from frames if they exist VLAN Enforcement: Allows unicast frames to adhere or ignore the VLAN configuration VLAN Mask Registers: Allows configuration of individual VLAN grouping. VLAN Tag Insertion Values: Specifies the VLAN tag to be inserted if enabled (see above)
Table 2. VLAN Control
Station MAC Address (control frames only)
The MAC source address can be programmed as used in flow control frames. The table below briefly summarizes this progammable feature.
Register(s) 48-53 Bit(s) 7-0 Global/Port Global Description Station MAC Address: Used as source address for MAC control frames as used in fullduplex flow control mechanisms.
Table 3. Misc. Control
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EEPROM Operation
The EEPROM interface utilizes 2 pins that provide a clock and a serial data path. As part of the initialization sequence, the KS8997 reads the contents of the EEPROM and loads the values into the appropriate registers. Note that the first two bytes in the EEPROM must be "55" and "99" respectively for the loading to occur properly. If these first two values are not correct, all other data will be ignored. Data start and stop conditions are signaled on the data line as a state transition during clock high time. A high to low transition indicates start of data and a low to high transition indicates a stop condition. The actual data that traverses the serial line changes during the clock low time. The KS8997 EEPROM interface is compatible with the Atmel AT24C01A part. Further timing and data sequences can be found in the Atmel AT24C01A specification.
EEPROM Memory Map
Address 0 1 Name 7-0 7-0 Description Signature byte 1. Value = "55" Signature byte 2. Value = "99" Default (chip) Value 0x55 0x99
General Control Register 2 2 7-4 3-2 Reserved - set to zero Priority control scheme (all ports) 00 = Transmit all high priority before any low priority 01= Transmit high and low priority at a 10:1 ratio 10 = Transmit high and low priority at a 5:1 ratio 11 = Transmit high and low priority at a 2:1 ratio Priority buffer reserve for high priority traffic 1 = Reserve 6KB of buffer space for high priority 0 = None reserved VLAN enforcement 1 = All unicast frames adhere to VLAN configuration 0 = Unicast frames ignore VLAN configuration 0000 00
2
1
0
2
0
0
Priority Classification Control - 802.1p tag field 3 3 3 3 3 3 3 3 7 6 5 4 3 2 1 0 1 = State "111" is high priority 0 = State "111" is low priority 1 = State "110" is high priority 0 = State "110" is low priority 1 = State "101" is high priority 0 = State "101" is low priority 1 = State "100" is high priority 0 = State "100" is low priority 1 = State "011" is high priority 0 = State "011" is low priority 1 = State "010" is high priority 0 = State "010" is low priority 1 = State "001" is high priority 0 = State "001" is low priority 1 = State "000" is high priority 0 = State "000" is low priority 1 1 1 1 0 0 0 0
Port 1 Control Register 4 4 7-6 5 Reserved - set to zero TOS priority classification enable for port 1 1 = Enable 0 = Disable 802.1p priority classification enable for port 1 1 = Enable 0 = Disable 00 0
4
4
0
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Address 4 Name 3 Description Port based priority classification for port 1 1 = High priority 0 = Low priority Insert VLAN tags for port 1 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 1 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 1 1 = Enable 0 = Disable Default (chip) Value 0
Micrel
4
2
0
4
1
0
4
0
0
Port 2 Control Register 5 5 7-6 5 Reserved - set to zero TOS priority classification enable for port 2 1 = Enable 0 = Disable 802.1p priority classification enable for port 2 1 = Enable 0 = Disable Port based priority classification for port 2 1 = High priority 0 = Low priority Insert VLAN tags for port 2 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 2 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 2 1 = Enable 0 = Disable 00 0
5
4
0
5
3
0
5
2
0
5
1
0
5
0
0
Port 3 Control Register 6 6 7-6 5 Reserved - set to zero TOS priority classification enable for port 3 1 = Enable 0 = Disable 802.1p priority classification enable for port 3 1 = Enable 0 = Disable Port based priority classification for port 3 1 = High priority 0 = Low priority Insert VLAN tags for port 3 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 3 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 3 1 = Enable 0 = Disable 00 0
6
4
0
6
3
0
6
2
0
6
1
0
6
0
0
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Address Name Description Default (chip) Value
Micrel
Port 4 Control Register 7 7 7-6 5 Reserved - set to zero TOS priority classification enable for port 4 1 = Enable 0 = Disable 802.1p priority classification enable for port 4 1 = Enable 0 = Disable Port based priority classification for port 4 1 = High priority 0 = Low priority Insert VLAN tags for port 4 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 4 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 4 1 = Enable 0 = Disable 00 0
7
4
0
7
3
0
7
2
0
7
1
0
7
0
0
Port 5 Control Register 8 8 7-6 5 Reserved - set to zero TOS priority classification enable for port 5 1 = Enable 0 = Disable 802.1p priority classification enable for port 5 1 = Enable 0 = Disable Port based priority classification for port 5 1 = High priority 0 = Low priority Insert VLAN tags for port 5 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 5 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 5 1 = Enable 0 = Disable 00 0
8
4
0
8
3
0
8
2
0
8
1
0
8
0
0
Port 6 Control Register 9 9 7-6 5 Reserved - set to zero TOS priority classification enable for port 6 1 = Enable 0 = Disable 802.1p priority classification enable for port 6 1 = Enable 0 = Disable Port based priority classification for port 6 1 = High priority 0 = Low priority 00 0
9
4
0
9
3
0
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Address 9 Name 2 Description Insert VLAN tags for port 6 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 6 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 6 1 = Enable 0 = Disable Default (chip) Value 0
Micrel
9
1
0
9
0
0
Port 7 Control Register 10 10 7-6 5 Reserved - set to zero TOS priority classification enable for port 7 1 = Enable 0 = Disable 802.1p priority classification enable for port 7 1 = Enable 0 = Disable Port based priority classification for port 7 1 = High priority 0 = Low priority Insert VLAN tags for port 7 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 7 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 7 1 = Enable 0 = Disable 00 0
10
4
0
10
3
0
10
2
0
10
1
0
10
0
0
Port 8 Control Register 11 11 7-6 5 Reserved - set to zero TOS priority classification enable for port 8 1 = Enable 0 = Disable 802.1p priority classification enable for port 8 1 = Enable 0 = Disable Port based priority classification for port 8 1 = High priority 0 = Low priority Insert VLAN tags for port 8 if non-existent| 1 = Enable 0 = Disable Strip VLAN tags for port 8 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 8 1 = Enable 0 = Disable 00 0
11
4
0
11
3
0
11
2
0
11
1
0
11
0
0
Reserved Register 12 7-0 Reserved 0x00
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Address Name Description Default (chip) Value
Micrel
Port 1 VLAN Mask Register 13 13 7 6 Reserved Port 8 inclusion 1 = Port 8 in the same VLAN as port 1 0 = Port 8 not in the same VLAN as port 1 Port 7 inclusion 1 = Port 7 in the same VLAN as port 1 0 = Port 7 not in the same VLAN as port 1 Port 6 inclusion 1 = Port 6 in the same VLAN as port 1 0 = Port 6 not in the same VLAN as port 1 Port 5 inclusion 1 = Port 5 in the same VLAN as port 1 0 = Port 5 not in the same VLAN as port 1 Port 4 inclusion 1 = Port 4 in the same VLAN as port 1 0 = Port 4 not in the same VLAN as port 1 Port 3 inclusion 1 = Port 3 in the same VLAN as port 1 0 = Port 3 not in the same VLAN as port 1 Port 2 inclusion 1 = Port 2 in the same VLAN as port 1 0 = Port 2 not in the same VLAN as port 1 1 1
13
5
1
13
4
1
13
3
1
13
2
1
13
1
1
13
0
1
Port 2 VLAN Mask Register 14 14 7 6 Reserved Port 8 inclusion 1 = Port 8 in the same VLAN as port 2 0 = Port 8 not in the same VLAN as port 2 Port 7 inclusion 1 = Port 7 in the same VLAN as port 2 0 = Port 7 not in the same VLAN as port 2 Port 6 inclusion 1 = Port 6 in the same VLAN as port 2 0 = Port 6 not in the same VLAN as port 2 Port 5 inclusion 1 = Port 5 in the same VLAN as port 2 0 = Port 5 not in the same VLAN as port 2 Port 4 inclusion 1 = Port 4 in the same VLAN as port 2 0 = Port 4 not in the same VLAN as port 2 Port 3 inclusion 1 = Port 3 in the same VLAN as port 2 0 = Port 3 not in the same VLAN as port 2 Port 1 inclusion 1 = Port 1 in the same VLAN as port 2 0 = Port 1 not in the same VLAN as port 2 1 1
14
5
1
14
4
1
14
3
1
14
2
1
14
1
1
14
0
1
Port 3 VLAN Mask Register 15 15 7 6 Reserved Port 8 inclusion 1 = Port 8 in the same VLAN as port 3 0 = Port 8 not in the same VLAN as port 3 1 1
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Address 15 Name 5 Description Port 7 inclusion 1 = Port 7 in the same VLAN as port 3 0 = Port 7 not in the same VLAN as port 3 Port 6 inclusion 1 = Port 6 in the same VLAN as port 3 0 = Port 6 not in the same VLAN as port 3 Port 5 inclusion 1 = Port 5 in the same VLAN as port 3 0 = Port 5 not in the same VLAN as port 3 Port 4 inclusion 1 = Port 4 in the same VLAN as port 3 0 = Port 4 not in the same VLAN as port 3 Port 2 inclusion 1 = Port 2 in the same VLAN as port 3 0 = Port 2 not in the same VLAN as port 3 Port 1 inclusion 1 = Port 1 in the same VLAN as port 3 0 = Port 1 not in the same VLAN as port 3 Default (chip) Value 1
Micrel
15
4
1
15
3
1
15
2
1
15
1
1
15
0
1
Port 4 VLAN Mask Register 16 16 7 6 Reserved Port 8 inclusion 1 = Port 8 in the same VLAN as port 4 0 = Port 8 not in the same VLAN as port 4 Port 7 inclusion 1 = Port 7 in the same VLAN as port 4 0 = Port 7 not in the same VLAN as port 4 Port 6 inclusion 1 = Port 6 in the same VLAN as port 4 0 = Port 6 not in the same VLAN as port 4 Port 5 inclusion 1 = Port 5 in the same VLAN as port 4 0 = Port 5 not in the same VLAN as port 4 Port 3 inclusion 1 = Port 3 in the same VLAN as port 4 0 = Port 3 not in the same VLAN as port 4 Port 2 inclusion 1 = Port 2 in the same VLAN as port 4 0 = Port 2 not in the same VLAN as port 4 Port 1 inclusion 1 = Port 1 in the same VLAN as port 4 0 = Port 1 not in the same VLAN as port 4 1 1
16
5
1
16
4
1
16
3
1
16
2
1
16
1
1
16
0
1
Port 5 VLAN Mask Register 17 17 7 6 Reserved Port 8 inclusion 1 = Port 8 in the same VLAN as port 5 0 = Port 8 not in the same VLAN as port 5 Port 7 inclusion 1 = Port 7 in the same VLAN as port 5 0 = Port 7 not in the same VLAN as port 5 Port 6 inclusion 1 = Port 6 in the same VLAN as port 5 0 = Port 6 not in the same VLAN as port 5 1 1
17
5
1
17
4
1
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Address 17 Name 3 Description Port 4 inclusion 1 = Port 4 in the same VLAN as port 5 0 = Port 4 not in the same VLAN as port 5 Port 3 inclusion 1 = Port 3 in the same VLAN as port 5 0 = Port 3 not in the same VLAN as port 5 Port 2 inclusion 1 = Port 2 in the same VLAN as port 5 0 = Port 2 not in the same VLAN as port 5 Port 1 inclusion 1 = Port 1 in the same VLAN as port 5 0 = Port 1 not in the same VLAN as port 5 Default (chip) Value 1
Micrel
17
2
1
17
1
1
17
0
1
Port 6 VLAN Mask Register 18 18 7 6 Reserved Port 8 inclusion 1 = Port 8 in the same VLAN as port 6 0 = Port 8 not in the same VLAN as port 6 Port 7 inclusion 1 = Port 7 in the same VLAN as port 6 0 = Port 7 not in the same VLAN as port 6 Port 5 inclusion 1 = Port 5 in the same VLAN as port 6 0 = Port 5 not in the same VLAN as port 6 Port 4 inclusion 1 = Port 4 in the same VLAN as port 6 0 = Port 4 not in the same VLAN as port 6 Port 3 inclusion 1 = Port 3 in the same VLAN as port 6 0 = Port 3 not in the same VLAN as port 6 Port 2 inclusion 1 = Port 2 in the same VLAN as port 6 0 = Port 2 not in the same VLAN as port 6 Port 1 inclusion 1 = Port 1 in the same VLAN as port 6 0 = Port 1 not in the same VLAN as port 6 1 1
18
5
1
18
4
1
18
3
1
18
2
1
18
1
1
18
0
1
Port 7 VLAN Mask Register 19 19 7 6 Reserved Port 8 inclusion 1 = Port 8 in the same VLAN as port 7 0 = Port 8 not in the same VLAN as port 7 Port 6 inclusion 1 = Port 6 in the same VLAN as port 7 0 = Port 6 not in the same VLAN as port 7 Port 5 inclusion 1 = Port 5 in the same VLAN as port 7 0 = Port 5 not in the same VLAN as port 7 Port 4 inclusion 1 = Port 4 in the same VLAN as port 7 0 = Port 4 not in the same VLAN as port 7 Port 3 inclusion 1 = Port 3 in the same VLAN as port 7 0 = Port 3 not in the same VLAN as port 7 1 1
19
5
1
19
4
1
19
3
1
19
2
1
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Address 19 Name 1 Description Port 2 inclusion 1 = Port 2 in the same VLAN as port 7 0 = Port 2 not in the same VLAN as port 7 Port 1 inclusion 1 = Port 1 in the same VLAN as port 7 0 = Port 1 not in the same VLAN as port 7 Default (chip) Value 1
Micrel
19
0
1
Port 8 VLAN Mask Register 20 20 7 6 Reserved Port 7 inclusion 1 = Port 7 in the same VLAN as port 8 0 = Port 7 not in the same VLAN as port 8 Port 6 inclusion 1 = Port 6 in the same VLAN as port 8 0 = Port 6 not in the same VLAN as port 8 Port 5 inclusion 1 = Port 5 in the same VLAN as port 8 0 = Port 5 not in the same VLAN as port 8 Port 4 inclusion 1 = Port 4 in the same VLAN as port 8 0 = Port 4 not in the same VLAN as port 8 Port 3 inclusion 1 = Port 3 in the same VLAN as port 8 0 = Port 3 not in the same VLAN as port 8 Port 2 inclusion 1 = Port 2 in the same VLAN as port 8 0 = Port 2 not in the same VLAN as port 8 Port 1 inclusion 1 = Port 1 in the same VLAN as port 8 0 = Port 1 not in the same VLAN as port 8 1 1
20
5
1
20
4
1
20
3
1
20
2
1
20
1
1
20
0
1
Reserved Register 21 7-0 Reserved 0xFF
Port 1 VLAN Tag Insertion Value Registers 22 22 22 23 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00
Port 2 VLAN Tag Insertion Value Registers 24 24 24 25 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00
Port 3 VLAN Tag Insertion Value Registers 26 26 26 27 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00
Port 4 VLAN Tag Insertion Value Registers 28 7-5 User priority [2:0] 000
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Address 28 28 29 Name 4 3-0 7-0 Description CFI VID [11:8] VID [7:0] Default (chip) Value 0 0x0 0x00
Micrel
Port 5 VLAN Tag Insertion Value Registers 30 30 30 31 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00
Port 6 VLAN Tag Insertion Value Registers 32 32 32 33 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00
Port 7 VLAN Tag Insertion Value Registers 34 34 34 35 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00
Port 8 VLAN Tag Insertion Value Registers 36 36 36 37 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00
Reserved Register 38 7-0 Reserved 0x00
Diff Serv Code Point Registers 40 41 42 43 44 45 46 47 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 DSCP[63:56] DSCP[55:48] DSCP[47:40] DSCP[39:32] DSCP[31:24] DSCP[23:16] DSCP[15:8] DSCP[7:0] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Station MAC Address Registers (all ports - MAC control frames only) 48 49 50 51 52 53
Note.
7-0 7-0 7-0 7-0 7-0 7-0
MAC address [47:40] MAC address [39:32] MAC address [31:24] MAC address [23:16] MAC address [15:8] MAC address [7:0]
0x00 0x40 0x05 0x43 0x5E 0xFE
The MAC address is reset to the value in the above table, but can set to any value via the EEPROM interface. This MAC address is used as the source address in MAC control frames that execute flow control between link peers.
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Micrel
Absolute Maximum Ratings (Note 1)
Supply Voltage (VDD_RX, VDD_TX, VDD_RCV, VDD, VDD_PLLTX) .............................................. -0.5V to +2.3V (VDDIO) .................................................... -0.5V to +3.8V Input Voltage ............................................... -0.5V to +4.0V Output Voltage ............................................ -0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..................... 270C Storage Temperature (TS) ....................... -55C to +150C
Operating Ratings (Note 2)
Supply Voltage (VDD_RX, VDD_TX, VDD_RCV, VDD, VDD_PLLTX) .............................................. +2.0V to +2.3V (VDDIO) ....................... +2.0V to +2.3V or +3.0V to +3.6V Ambient Temperature (TA) ............................. 0C to +70C Package Thermal Resistance (Note 3) PQFP (JA) No Air Flow ................................. 42.91C/W
Electrical Characteristics (Note 4)
VDD = 2.0V to 2.3V; TA = 0C to +70; unless noted. Symbol VDD Parameter Supply Voltage Condition Min 2.00 Typ 2.10 Max 2.30 Units V
100BaseTX Operation 100BaseTX (Total) IDX IDA IDD 100BaseTX (Transmitter) 100BaseTX (Analog) 100BaseTX (Digital) 0.61 0.35 0.18 0.08 A A A A
10BaseTX Operation 10BaseTX (Total) IDX IDDC IDDIO TTL Inputs VIH VIL IIN TTL Outputs VOH VOL |IOZ| VO VIMB tr, tt Output High Voltage Output Low Voltage Output Tri-State Leakage IOH = -4mA IOL = 4mA VDDIO -0.4 0.4 10 V V A Input High Voltage Input Low Voltage Input Current VIN = GND ~ VDD -10 (1/2 VDDIO) +0.4V (1/2 VDDIO) -0.4V 10 V V A 10BaseTX (Transmitter) 10BaseTX (Analog) 10BaseTX (Digital) 0.90 0.72 0.11 0.07 A A A A
100BaseTX Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance
Note 1. Note 2. Note 3. Note 4. Exceeding the absolute maximum rating may damage the device. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground to VDD). No HS (heat spreader) in package. Specification for packaged product only.
50 from each output to VDD 50 from each output to VDD
0.95
1.05 2
V % ns ns
3 0
5 0.5
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Symbol Parameter Condition Min Typ Max 0.5 5 0.75 Peak-to-peak 0.7 1.4
Micrel
Units
100BaseTX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot VSET Reference Voltage of ISET Output Jitters 10BaseT Receive VSQ VP Squelch Threshold 5MHz square wave 400 mV ns % V ns
10BaseT Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage Jitters Added Rise/Fall Times 50 from each output to VDD 50 from each output to VDD 28 2.3 3.5 V V ns
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Timing Diagrams
tcyc SCL
ts SDA
th
Figure 2. EEPROM Input Timing Diagram
Symbol tCYC tS tH Parameter Clock Cycle Set-Up Time Hold Time 20 20 Min Typ 16384 Max Units ns ns ns
Table 4. EEPROM Timing Parameters
tcyc SCL tov
SDA
Figure 3. EEPROM Output Timing Diagram
Symbol tCYC tOV Parameter Clock Cycle Set-Up Time 4096 Min Typ 16384 4112 4128 Max Units ns ns
Table 5. EEPROM Output Timing Parameters
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Reference Circuit
See "I/O Description" section for pull-up/pull-down and float information.
VDD-IO
Pull-Up
10k
220
LED pin
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VDD-IO
Float
220
LED pin
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VDD-IO
Pull Down Pull down
220
LED pin
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1k
Reference circuits for unmanaged programming through LED ports
Note: For brighter LED operation use VDD-IO = 3.3V
Figure 4. Unmanaged Programming Circuit
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4B/5B Coding
In 100BaseTX and 100BaseFX the data and frame control are encoded in the transmitter (and decoded in the receiver) using a 4B/5B code. The extra code space is required to encode extra control (frame delineation) points. It is also used to reduce run length as well as supply sufficient transitions for clock recovery. The table below provides the translation for the 4B/5B coding.
Code Type Data 4B Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Control Not defined 0101 0101 Not defined Not defined Not defined Invalid Not defined Not defined Not defined Not defined Not defined Not defined Not defined Not defined Not defined Not defined 5B Code 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Value Data value 0 Data value 1 Data value 2 Data value 3 Data value 4 Data value 5 Data value 6 Data value 7 Data value 8 Data value 9 Data value A Data value B Data value C Data value D Data value E Data value F Idle Start delimiter part 1 Start delimiter part 2 End delimiter part 1 End delimiter part 2 Transmit error Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code
Table 6. 4B/5B Coding
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MLT3 Coding
For 100BaseTX operation the NRZI (Non-Return to Zero Invert on ones) signal is line coded as MLT3. The net result of using MLT3 is to reduce the EMI (Electro Magnetic Interference) of the signal over twisted pair media. In NRZI coding, the level changes from high to low or low to high for every "1" bit. For a "0" bit there is no transition. MLT3 line coding transitions through three distinct levels. For every transition of the NRZI signal the MLT3 signal either increments or decrements depending on the current state of the signal. For instance if the MLT3 level is at its lowest point the next two NRZI transitions will change the MLT3 signal initially to the middle level followed by the highest level (second NRZI transition). On the next NRZI change, the MLT3 level will decrease to the middle level. On the following transition of the NRZI signal the MLT3 level will move to the lowest level where the cycle repeats. The diagram below describes the level changes. Note that in the actual 100BaseTX circuit there is a scrambling circuit and that scrambling is not shown in this diagram.
Hex Value Binary 4B Binary 5B
A
3
8
E
9
4
T3
R3
I1
I1
1010 0011 1000 1110 1001 0100 UUUU UUUU UUUU UUUU 10110101011001011100100110101001101001111111111111
NRZ
NRZI
MLT3
Figure 5. MLT3 coding
MAC Frame for 802.3
The MAC (Media Access Control) fields are described in the table below.
Field Preamble/SFD DA SA 802.1p tag Length Protocol/Data Frame CRC ESD Idle Octect Length 8 6 6 4 2 46 to 1500 4 1 Variable Description Preamble and Start of Frame Delimiter 48-bit Destination MAC Address 48-bit Source MAC Address VLAN and priority tag (optional) Frame Length Higher Layer Protocol and Frame Data 32-bit Cyclical Redundancy Check End of Stream Delimiter Inter Frame Idles
Table 7. MAC Frame for 802.3
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Selection of Isolation Transformer(Note 1)
One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics.
Characteristics Name Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.)
Note 1.
Value 1 CT : 1 CT 350H 0.4H 12pF 0.9 1.0dB 1500Vrms
Test Condition
100mV, 100 KHz, 8mA 1MHz (min.)
0MHz to 65MHz
The IEEE 802.3u standard for 100BaseTX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to 1.3dB can be compensated by increasing the line drive current by means of reducing the ISET resistor value.
Selection of Reference Oscillator/Crystal
An oscillator or crystal with the following typical characteristics is recommended.
Characteristics Name Frequency Maximum Frequency Tolerance Maximum Jitter Value 25.00000 100 150 Test Condition MHz ppm ps(pk-pk)
The following transformer vendor provide compatible magnetic parts for Micrel's device: Type Transformer only 4-Port Integrated Vendor Part Pulse H1164 Single-Port Vendor Part Pulse H1102
Table 8. Qualified Magnetics Lists
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Package Information
128-Pin PQFP (PQ) MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 944-0970
WEB
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2003 Micrel, Incorporated.
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