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Global Mixed-mode Technology Inc.
G2995
DDR Termination Regulator
Features
Operation Supply Voltage: 1.6V to 5.5V Low Supply Current: 280A @ 2.5V Low Output Offset Source and Sink Current Low External Component Count No Inductor Required No external Resistors Required Thermal Shutdown Protection SOP-8L with Power-Pad package
General Description
The G2995 is a linear regulator designed to meet the JEDEC SSTL-2 and SSTL-3 (Series Stub Termination Logic) specifications for termination of DDR-SDRAM. It contains a high-speed operational amplifier that provides excellent response to the load transients. This device can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. With an independent VSENSE pin, the G2995 can provide superior load regulation. The G2995 provides a VREF output as the reference for the applications of the chipset and DIMMs. The G2995 can easily provide the accurate VTT and VREF voltages without external resistors that PCB areas can be reduced. The quiescent current is as low as 280A @ 2.5V. So the power consumption can meet the low power consumption applications.
Applications
DDR-SDRAM Termination Voltage DDR-I / DDR-II Termination Voltage SSTL-2 SSTL-3
Ordering Information
ORDER NUMBER
G2995P1U G2995F1U Note: P1:SOP-8 U: Tape & Reel
ORDER NUMBER (Pb free)
G2995P1Uf G2995F1Uf F1:SOP-8(FD) (FD): Thermal Pad
MARKING
G2995 G2995
TEMP. RANGE
-40C to 85C -40C to 85C
PACKAGE
SOP-8 SOP-8 (FD)
Pin Configuration
Typical Application Circuit
G2995
NC GND VSENSE VREF 1 2 3 4 8 7 6 5 VTT PVIN AVIN VDDQ 47F
+
VDDQ=2.5V
VDDQ
VREF
+
VREF=1.25V 0.01F
Thermal Pad
VDD=2.5V
AVIN PVIN
VSENSE VTT GND
+
VTT=1.25V 220F
SOP-8
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Absolute Maximum Ratings
(1)
G2995
Recommend Operation Range
Operating Ambient Temperature Range TA...................................................-40C to +85C AVIN to GND......................................1.6V to +5.5V PVIN, VDDQ to GND............................1.6V to AVIN
Supply Voltage PVIN, AVIN, VDDQ to GND...............-0.3V to +6V Operating Ambient Temperature Range TA..................................................-40C to +125C Maximum Junction Temperature, TJ...................150C Storage Temperature Range, TSTG........-65C to+150C Reflow Temperature (Soldering, 10 sec)............260C Electrostatic Discharge, VESD Human body mode......................................2000V(2) SOP-8L Thermal Resistance (JA)................130C/W SOP-8L (FD) Thermal Resistance (JA).........50C/W(3) SOP-8L (FD) Thermal Resistance (JA).........41C/W(4) SOP-8L (FD) Thermal Resistance (Jc)..........12C/W
Note:
(1) (2) (3) (4)
:Absolute maximum rating indicates limits beyond which damage to the device may occurs. : Human body model : C = 100pF, R = 1500, 3 positive pulses plus 3 negative pulses : The package is placed on a 2-layer PCB (2oz/2oz) with 6 vias. : The package is placed on a 2-layer PCB (2oz/2oz) with 6 vias. The airflow is used.
Electrical Characteristics
Specifications with standard typeface are for TA=25C. Unless otherwise specified, AVIN=PVIN=2.5V, VDDQ=2.5V
PARAMETER
VREF Voltage VREF Output impendence
SYMBOL
VREF ZREF
CONDITION
VDDQ=2.3V VDDQ=2.5V VDDQ=2.7V IREF =-30A to + 30A IOUT=0A VDDQ=2.3V VDDQ=2.5V VDDQ=2.7V IOUT=1.5A VDDQ=2.3V VDDQ=2.5V VDDQ=2.7V IOUT=0A IOUT=-1.5A IOUT=+1.5A IOUT=0A
MIN
1.11 1.21 1.31 --1.11 1.21 1.31 1.11 1.21 1.31 -40 -40 -40 -----------
TYP
1.145 1.245 1.345 1.15 1.152 1.252 1.352 1.152 1.252 1.352 0 0 0 280 100 20 150 25
MAX
1.19 1.29 1.39 --1.19 1.29 1.39 1.19 1.29 1.39 40 40 40 500 ---------
UNIT
V V V k V V V V V V mV mV mV A K nA C C
VTT Output voltage
VTT
VTT Output Voltage Offset (VREF- VTT) Quiescent Current VDDQ input Impedence VSENSE input current Thermal Shutdown Thermal Shutdown Hystersis
VosVtt IQ ZVDDQ ISENSE TSD THsy
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Typical Performance Characteristics
G2995
VREF vs IREF
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1F, CPVIN=47F, CVREF=0.01F, CVTT=220F, TA=25C, unless otherwise noted.
IQ vs AVIN
270 1.3
250
1.28
230
1.26
210
VREF(V)
2 2.5 3 3.5 4 4.5 5 5.5
IQ(A)
1.24
190
1.22
170
1.2
150
1.18 -30 -20 -10 0 10 20 30
AVIN(V)
IREF(A)
VREF vs VDDQ
3 1.252 2.5
VTT vs IOUT Temperature
1.248
2
VREF(V)
1.5
VTT(V)
1.244
1.24 1
0C 25C
0.5
1.236 85C 1.232 -100
0 2 2.5 3 3.5 4 4.5 5 5.5
-75
-50
-25
0
25
50
75
100
VDDQ(V)
IOUT(mA)
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Typical Performance Characteristics
G2995
IQ vs AVIN Temperature
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1F, CPVIN=47F, CVREF=0.01F, CVTT=220F, TA=25C, unless otherwise noted.
VTT vs VDDQ
3 270 25C 2.5 250 85C 2 230
VTT(V)
IQ(A)
1.5
210
0C
1
190
0.5
170
0 2 2.5 3 3.5 4 4.5 5 5.5
150 2 2.5 3 3.5 4 4.5 5 5.5
VDDQ(V)
AVIN(V)
Maximum Sourcing Current vs AVIN (VDDQ=2.5V, PVIN=1.8V)
1.4 1.2 1.8 1.7
Maximum Sourcing Current vs AVIN (VDDQ=2.5V, PVIN=2.5V)
OUTPUT CURRENT(A)
OUTPUT CURRENT(A)
2 2.5 3 3.5 4 4.5 5 5.5
1 0.8 0.6 0.4 0.2 0
1.6 1.5 1.4 1.3 1.2 1.1 2 2.5 3 3.5 4 4.5 5 5.5
AVIN(V)
AVIN(V)
Maximum Sourcing Current vs AVIN (VDDQ=2.5V, PVIN=3.3V)
3
OUTPUT CURRENT(A)
2.8
2.6
2.4
2.2
2 2 2.5 3 3.5 4 4.5 5 5.5
AVIN(V)
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Typical Performance Characteristics
G2995
Maximum Sourcing Current vs AVIN
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1F, CPVIN=47F, CVREF=0.01F, CVTT=220F, TA=25C, unless otherwise noted.
Maximum Sinking Current vs AVIN (VDDQ=2.5V)
3 2.8 1.4 1.2
(VDDQ=1.8V, PVIN=1.8V)
OUTPUT CURRENT(A)
2.6 2.4 2.2 2 1.8 1.6 1.4 2 2.5 3 3.5 4 4.5 5 5.5
OUTPUT CURRENT(A)
1 0.8 0.6 0.4 0.2 0 2 2.5 3 3.5 4 4.5 5 5.5
AVIN(V)
AVIN(V)
Maximum Sinking Current vs AVIN (VDDQ=1.8V)
2.8 2.6
Maximum Sourcing Current vs AVIN (VDDQ=1.8V, PVIN=3.3V)
3 IO=200m
OUTPUT CURRENT(A)
OUTPUT CURRENT(A)
2.4 2.2 2 1.8 1.6 1.4 1.2 1 2 2.5 3 3.5 4 4.5 5 5.5
2.8
2.6
2.4
2.2
2 2 2.5 3 3.5 4 4.5 5 5.5
AVIN(V)
AVIN(V)
VOSVTT vs Temperature(VDDQ=2.5V)
30 20 10 0 -10 -20 -30 0 25 50 75 100 125
Sourcing 1.5A
VOSVTT(mV)
No Load
Sinking 1.5A
Temperature()
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Typical Performance Characteristics (continued)
G2995
ILoad=0.5A Transient (Sourcing)
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1F/Ceramic X7R/0603/6.3V/TDK, CPVIN=68F/6.3V POSCAP Series/SANYO, CVTT=330F*2/6.3V POSCAP Series/SANYO, TA=25C, unless otherwise noted.
ILoad=0.5A Transient (Sinking)
ILoad=1A Transient (Sinking)
ILoad=1A Transient (Sourcing)
ILoad=1.5A Transient (Sinking)
ILoad=1.5A Transient (Sourcing)
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Pin Description
NUMBER
1 2 3 4 5 6 7 8
G2995
NAME
NC GND VSENSE VREF VDDQ AVIN PVIN VTT Ground
FUNCTION
Feedback pin for regulating VTT Buffered output that is a reference output of VDDQ/2 Input for internal reference which equals to VDDQ/2 Analog input pin Power input pin Output voltage for connection to termination resistors, equal to VDDQ/2
Block Diagram
VDDQ AVIN PVIN
50k
VREF
+
+
50k
-
-
VTT
VSENSE
GND
Description
The G2995 is a linear bus termination regulator designed to meet the JEDEC SSTL-2 and SSTL-3 (Series Stub Termination Logic) specifications for termination of DDR-SDRAM. The output, VTT, is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ/2. The G2995 is designed to maintain the excellent load regulation and with fast response time to minimum the transition preventing shoot-through. The G2995 also incorporates two distinct power rails that separates the analog circuitry (AVIN) from the power output stage (PVIN). This power rails split can be utilized to reduce the internal power dissipation. And this also permits G2995 to provide a termination solution for the next generation of DDR-SDRAM (DDR II). Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single parallel termination. This involves one RS series resistor from the chipset to the memory and one RT termination resistor, both 25 typically. The resistors can be changed to scale the current requirements from the G2995. This implementation can be seen below in Figure 1.
Ver: 1.7 May 10, 2005
VDD
VTT
RT RS CHIPSET
MENORY
VREF
Figure 1. SSTL-Termination Scheme
AVIN, PVIN AVIN and PVIN are two independent input supply pins for the G2995. AVIN is used to supply all the internal analog circuits. PVIN is only used to supply the output stage to create the regulated VTT. To keep the regulation successfully, AVIN should be equal to or larger than PVIN. Using a higher PVIN voltage will produce a larger sourcing capability from VTT. But the internal power loss will also increase and then the heat increases. If the junction temperature exceeds the thermal shutdown threshold than the G2995 will enter the shutdown state, where VTT is tri-state and VREF remains active. For SSTL-2 applications, the AVIN and PVIN can be short together at 2.5V to minimize the PCB complexity and to reduce the bypassing capacitors for the two supply pins separately.
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VDDQ A voltage divider of two 50k is connected between VDDQ and ground, to create the internal reference voltage (VDDQ/2). This guarantees that VTT will track VDDQ/2 precisely. The optimal implementation of VDDQ is as a remote sensing. This can be achieved by connecting VDDQ directly to the 2.5V rail (SSTL-2 applications) at the DIMM instead of AVIN and PVIN. This will ensure that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. Vsense The VSENSE pin is the feedback sensing pin of the operation amplifier which regulates the VTT voltage. In most motherboard applications, the termination resistors will connect VTT in a long plane. If using the remote sensing pin - VSENSE to the middle of the bus, the significant long-trace IR drop resulting in a termination voltage which is lower at one end than the other can be avoided. This will provide a better distribution across the entire termination bus. If the remote load regulation is not used, the VSENSE pin must still be connected to VTT for correct regulation. Care should be taken when a long VSENSE trace is implemented in close proximity to the memory. Noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A small 0.1F ceramic capacitor placed next to the VSENSE pin can help to filter any high frequency signals and preventing errors. VREF VREF provides a buffered output of the internal reference voltage (VDDQ/2). It can support the reference voltage of Northbridge chipset and memory. For better performance, using an output bypass capacitor close this pin is more helpful for the noise. A ceramic capacitor in the range of 0.1F to 0.01F is recommended. VTT VTT is the regulated output that is used to terminate the bus resistors of DDR-SDRAM. It can precisely track the VDDQ/2 voltage with the sinking and sourcing current capability. The G2995 is designed to deliver 1.5A continuous current and peak current up to 3A with a fast transient response @ 2.5V supply rail. The maximum continuous current sourcing from VTT is a function of PVIN. Using a higher PVIN will increase the source current from VTT, but it also increase the internal power dissipation and reduce the efficiency. Although the G2995 can deliver the larger current, care should be taken for the thermal dissipation when larger current is required. The G2995 is packaged with Power-Pad to increase the power dissipation capability. When driving larger current, the larger heat-sink in the PCB is strongly recommended to have a better ther-
G2995
mal performance. The RDS of MOS will increase when the junction temperature increases. If the heat is not dealt with well, the maximum output current will be degraded. When the temperature exceeds the junction temperature, the thermal shutdown protection is activated. That will drive the VTT output into tri-state until the temperature returns below the hysteretic trigger point. Capacitors The G2995 does not require the capacitors for input stability, but it is recommended for improving the performance during large load transition to prevent the input power rail from dropping, especially for PVIN. The input capacitor for PVIN should be as close as possible. The typical recommended value is 50F for AL electrolytic capacitors, 10uF with X5R for the ceramic capacitors. To prevent the excessive noise coupling into this device, an additional 0.1F ceramic capacitor can be placed on the AVIN power rail for the better performance. The output capacitor of the G2995 is suggested to use the capacitors with low ESR. Using the capacitors with low ESR (as ceramic, OS-CON, tantalum) will have the better transition performance which is with smaller voltage drop when the peak current occurring at the transition. As a general recommendation the output capacitor should be sized above 220F with the low ESR for SSTL applications with DDR-SDRAM. Thermal Dissipation When the current is sinking to or sourcing from VTT, the G2995 will generate internal power dissipation resulting in the heat. Care should be taken to prevent the device from damages caused by the junction temperature exceeding the maximum rating. The maximum allowable internal temperature rise (TRMAX) can be calculated under the given maximum ambient temperature (TAMAX) of the application and the maximum allowable junction temperature (TJMAX). TRMAX= TJMAX - TAMAX From this equation, the maximum power dissipation (PDMAX) of the G2995 can be calculated: PDMAX = TRMAX /JA JA of the G2995 will be dependent on several variables: the packages used, the thickness and size of the copper, the number of vias and the airflow. In the package, the G2995 use the SO-8 with Power-PAD to improve the JA . If the layout of the PCB can put a larger size of copper to contact the Power-PAD of this device, the JA will be further improved. The better JA is not only protecting the device well, but also increasing the maximum current capability at the same ambient temperature.
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Typical Application Circuits
There are several application circuits shown in Figure 2 through 8 to illustrate some of the possible configurations of the G2995. Figure 2~4 are the SSTL-2 applications. For the majority of applications that imple-
G2995
ment the SSTL-2 termination scheme, it is recommended to connect all the input rails to 2.5V rail, as seen in Figure 2. This provides an optimal trade-off between power dissipation and component count.
VDDQ=2.5V
VDDQ
VREF
+
VREF=1.25V CREF
VDD=2.5V
AVIN PVIN CIN
+
VSENSE VTT GND
+
VTT=1.25V COUT
Figure 2. Recommended SSTL-2 Implementation
In Figure 3, the power rails are split. The power rail of the output stage (PVIN) can be as low as 1.8V, the power rail of the analog circuit (AVIN) is operated above 2V. The lower output stage power rail can lower the internal power dissipation when sourcing from the
device and improve the efficiency, but the disadvantage is the maximum continuous current sourcing from VTT is reduced. This configuration is applied when the power dissipation and efficiency are concerned.
VDDQ=2.5V
VDDQ
VREF
+
VREF=1.25V CREF
AVIN=1.8V or 5.5V PVIN=1.8V CIN
+
AVIN PVIN
VSENSE VTT GND
+
VTT=1.25V COUT
Figure 3. Lower Power Dissipation SSTL-2 Implementation
In Figure 4, the power rail of the output stage (PVIN) is connected to 3.3V to increase the maximum continuous current sourcing from VTT. AVIN should be always equal to or larger than PVIN. This configuration can increase the source capability of this device, but the power dissipation increases at the same time. It
should be more careful to prevent the junction temperature from exceeding the maximum rating. Because of this risk, it is not recommended to supply the output stage power rail (PVIN) with a voltage higher than a nominal 3.3V rail.
VDDQ=2.5V
VDDQ
VREF
+
VREF=1.25V CREF
AVIN=3.3V or 5V PVIN=3.3V CIN
+
AVIN PVIN
VSENSE VTT GND
+
VTT=1.25V COUT
Figure 4. SSTL-2 Implementation with higher voltage rails
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In Figure 5 & 6, they are the application configurations of DDR-II SDRAM bus terminations. Figure 5 is the typical application scheme of DDR-II SDRAM. With the separate VDDQ pin and an internal resistor divider, it
G2995
is possible to use the G2995 in applications utilizing DDR-II memory. Figure 6 is used to increase the driving capability. The risk is the same as figure 4.
VDDQ=1.8V
VDDQ
VREF
+
VREF=0.9V CREF
AVIN=1.8V or 5.5V PVIN=1.8V CIN
+
AVIN PVIN
VSENSE VTT GND
+
VTT=0.9V COUT
Figure 5. Recommended DDR-II Termination
VDDQ=1.8V
VDDQ
VREF
+
VREF=0.9V CREF
AVIN=3.3V or 5.5V PVIN=3.3V CIN
+
AVIN PVIN
VSENSE VTT GND
+
VTT=0.9V COUT
Figure 6. DDR-II Termination with higher voltage rails
Figure 7 & 8 are used to scale the VTT to the wanted value when the standard voltages of SSTL-2 do not meet the requirements. Using R1 & R2, Figure 7 can
shift VTT up to VDDQ/2 * (1+R1/R2) and figure 8 can shift VTT down to VDDQ/2 * (1-R1/R2).
VDDQ VDD
VDDQ AVIN PVIN CIN
+
VTT VSENSE GND R1 R2
+
VTT COUT
Figure 7. Increasing VTT by Level Shifting
R2 VDDQ VDD VDDQ AVIN PVIN CIN
+
VSENSE R1 VTT
+
VTT COUT
GND
Figure 8. Decreasing VTT by Level Shifting
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Package Information
C
G2995
E
H
L D 7 (4X)
A2 A1 e B
A
y
SOP-8L Package Note: 1. Package body sizes exclude mold flash and gate burrs 2. Dimension L is measured in gage plane 3. Tolerance 0.10mm unless otherwise specified 4. Controlling dimension is millimeter converted inch dimensions are not necessarily exact. 5. Followed from JEDEC MS-012 SYMBOL
A A1 A2 B C D E e H L y
MIN.
1.35 0.10 ----0.33 0.19 4.80 3.80 ----5.80 0.40 ----0
DIMENSION IN MM NOM.
1.60 ----1.45 ----------------1.27 -----------------
MAX.
1.75 0.25 ----0.51 0.25 5.00 4.00 ----6.20 1.27 0.10 8
MIN.
0.053 0.004 ----0.013 0.007 0.189 0.150 ----0.228 0.016 ----0
DIMENSION IN INCH NOM.
0.063 ----0.057 ----------------0.050 -----------------
MAX.
0.069 0.010 ----0.020 0.010 0.197 0.157 ----0.244 0.050 0.004 8
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C
G2995
E1
E
H
D1
L D 7 (4X)
A2 A1 e B
A
y
SOP- 8L (FD) Package Note: 1. Package body sizes exclude mold flash and gate burrs 2. Dimension L is measured in gage plane 3. Tolerance 0.10mm unless otherwise specified 4. Controlling dimension is millimeter converted inch dimensions are not necessarily exact. 5. Followed from JEDEC MS-012 SYMBOL
A A1 A2 B C D E e H L y D1 E1
MIN.
1.45 0.00 ----0.33 0.19 4.80 3.80 ----5.80 0.40 ----0 2.22 2.60
DIMENSION IN MM NOM.
1.50 ----1.45 ----------------1.27 -------------------------
MAX.
1.55 0.10 ----0.51 0.25 5.00 4.00 ----6.20 1.27 0.10 8 2.60 2.98
MIN.
0.057 0.000 ----0.013 0.007 0.189 0.150 ----0.228 0.016 ----0 0.087 0.102
DIMENSION IN INCH NOM.
0.059 ----0.057 ----------------0.050 -------------------------
MAX.
0.061 0.004 ----0.020 0.010 0.197 0.157 ----0.244 0.050 0.004 8 0.102 0.117
Taping Specification
PACKAGE
SOP-8 SOP-8 (FD)
Q'TY/REEL
2,500 ea 2,500 ea
Feed Direction Typical SOP Package Orientation
GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications.
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