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GaAs MMIC
CGY 94
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Preliminary Datasheet
* Power amplifier for GSM or AMPS application * Fully integrated 2 stage amplifier * Operating voltage range: 2.7 to 6 V * 2 W output power at 3.6 V * Overall power added efficiency 46 % * Input matched to 50 , simple output match
ESD: Electrostatic discharge sensitive device, observe handling precautions!
Type
Marking
Ordering code (taped)
Package 1)
CGY 94
CGY 94
Q68000-A9124
MW 12
Maximum ratings Characteristics Positive supply voltage Negative supply voltage ) Supply current Channel temperature Storage temperature
2
Symbol VD VG
max. Value 9 -8 2 150 -55...+150
Unit V V A C C
ID TCh Tstg
Pulse peak power dissipation
duty cycle 12.5%, ton=0.577ms
PPulse
Ptot
9
5
W
W
Total power dissipation (Ts 81 C)
Ts: Temperature at soldering point
Thermal Resistance Channel-soldering point
RthChS
14
K/W
1) Plastic body identical to SOT 223, dimensions see chapter Package Outlines
2) VG = -8V only in combination with VTR = 0V; VG = -6V while VTR 0V
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17.10.95 HL EH PD 21
GaAs MMIC
CGY 94
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Functional block diagram:
Control circuit:
VG (1)
VD1 (7)
VD2 (12)
VTR (2)
Control Circuit
Pin (8) Pout (12)
The drain current ID of the CGY 94 is adjusted by the internal control circuit. Therefore a negative voltage (-4V...-6V) has to be supplied at VG. For transmit operation VTR must be set to 0V. During receive operation VTR should be disconnected (shut off mode).
GND1 (6, 9)
GND2 (3, 4, 5, 10)
GND3 (11)
Pin # 1 2 3,4,5,10 6,9 7 8 11 12
VG VTR GND 2 GND 1 VD1 RFin GND 3 VD2, RFout
Configuration Negative voltage at control circuit (-4V...-6V) Control voltage for transmit mode (0V) or receive mode (open) RF and DC ground of the 2nd stage RF and DC ground of the 1st stage Positive drain voltage of the 1st stage RF input power Ground for internal output matching Positive drain voltage of the 2nd stage, RF output power
DC characteristics Characteristics
Drain current
Symbol Conditions
VD=3V, VG=0V, VTR n.c.
min
0.6 2.7
typ
0.9 4.1 1.1 0.32 1.3 -2.8
max
1.3 5.9 -1.8
Unit
A A A S S V
stage 1 IDSS1 stage 2 IDSS2
Drain current with active current control Transconductance (stage 1 and 2) Pinch off voltage
ID gfs1 gfs2 Vp
VD=3V, VG=-4V, VTR=0V VD=3V, ID=350mA VD=3V, ID=700mA VD=3V, ID<500A (all stages)
0.25 1.1 -3.8
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17.10.95 HL EH PD 21
GaAs MMIC
CGY 94
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Electrical characteristics (TA = 25C , f=0.9 GHz, ZS=ZL=50 Ohm, VD=3.6V, VG=-4V, VTR pin connected to ground, unless otherwise specified; pulsed with a duty cycle of 10%, ton=0.33ms) Characteristics Supply current
VD=3.0V; Pin=10dBm
Symbol IDD
min 27.0 22.8 31.5 32.8 34.5 43 42 41 -
typ 1.18 2 400 10 29.0 23.6 32.3 33.6 35.5 48 47 46 -49 -45 1.5 : 1
max 2.0 : 1
Unit A mA
Negative supply current
(normal operation)
IG ID IG G G Po Po Po
-
Shut-off current
VTR n.c.
A A
dB dB dBm dBm dBm % % % dBc dBc -
Negative supply current
(shut off mode, VTR pin n.c.)
Gain
Pin=-5dBm
Power gain
VD=3.6V; Pin=10dBm
Output Power
VD=3.0V; Pin=10dBm
Output Power
VD=3.6V; Pin=10dBm
Output Power
VD=5V; Pin=10dBm
Overall Power added Efficiency
VD=3.0V; Pin=10dBm
Overall Power added Efficiency
VD=3.6V; Pin=10dBm
Overall Power added Efficiency
VD=5V; Pin=10dBm
Harmonics (Pin=10dBm, CW)
VD=3.6V; (Pout=33.1dBm)
2f0 3f0
Input VSWR VD=3.6V;
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17.10.95 HL EH PD 21
GaAs MMIC
CGY 94
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Pout and PAE vs. Pin
(VD=3.6V, VG=-4V, VTR=0V, f=900GHz, pulsed with a duty cycle of 10%, ton=0.33ms)
45
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60
40
50
Pout [dBm]
35
40
30
30
25
20
20
10
15 -5 0 5 10 15
0
Pin [dBm]
Pout and PAE vs. Pin
(VD=5V, VG=-4V, VTR=0V, f=900GHz, pulsed with a duty cycle of 10%, ton=0.33ms)
45
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60
40
50
Pout [dBm]
35
40
30
30
25
20
20
10
15 -5 0 5 10 15
0
Pin [dBm]
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17.10.95 HL EH PD 21
PAE [%]
PAE [%]
GaAs MMIC
S-Parameter at VD=3.6V and Pin=9dBm (VG=-4V, VTR=0V, pulsed with a duty cycle of 10%)
CGY 94
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30 25 20 15 10 Mag [dB] 5 0 -5 -10 -15 -20 -25 -30 750 770 790 810 830 850 870 890 910 930 950 MAG(s11) MAG(s21)
f [M Hz]
S-Parameter at VD=5V and Pin=9dBm (VG=-4V, VTR=0V, pulsed with a duty cycle of 10%)
30 25 20 15 10 Mag [dB] 5 0 -5 -10 -15 -20 -25 -30 750 770 790 810 830 850 870 890 910 930 950 MAG(s11) MAG(s21)
f [M Hz]
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17.10.95 HL EH PD 21
GaAs MMIC
CGY 94
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Performance of internal bias control circuit (VTR=0V)
3,0 2,8 2,6 2,4 2,2 2,0 ID / A 1,8 1,6 1,4 1,2 1,0 0,8 0,6 0,4 2,0 2,5 3,0 3,5 4,0 -Vg / V 4,5 5,0 5,5 6,0 ID (VD=3.0V) ID (VD=6.0V)
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17.10.95 HL EH PD 21
GaAs MMIC
Total Power Dissipation Ptot=f(TS)
CGY 94
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Permissible pulse load Ptot_max/Ptot_DC = f(t_p)
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GaAs MMIC
CGY 94
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Test circuit board:
Note:
43nH
By changing the position of the 6.8 pF capacitor at pin # 12 it is possible to tune the board for max. Pout or max. PAE. To achieve the maximum output power place the capacitor close to the CGY94. For a better PAE increase the distance between the capacitor and the CGY94 device (2-5mm).
Principal circuit: VG
1nF
+VD
1nF 4.7uF
43nH
VG (1) VD1 (7) VD2 (12)
VTR (2)
VTR
1nF
Control Circuit
IN
Pin (8)
Pout (12)
OUT
6.8pF
GND1 (6, 9)
GND2 (3, 4, 5, 10)
GND3 (11)
2) Coilcraft SMD Spring Inductor distribution by Ginsbury Electronic GmbH, Am Moosfeld 85 D-81829 Munchen, Tel. 089/45170-223
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GaAs MMIC
APPLICATION - HINTS
CGY 94
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1. CW - capability of the CGY94 Proving the possibility of CW - operation there must be known the total power dissipation of the device. This value can be found as a function of the temperature in the datasheet (page 7). The CGY94 has a maximum total power dissipation of Ptot = 5 W. As an example we take the operating point with a drain voltage VD = 3 V and a typical drain current of ID=1.0 A. So the maximum DC - power can be calculated to:
PDC = VD I D = 3W
This value is smaller than 5 W and CW - operation is possible. By decoupling RF power out of the CGY94 the power dissipation of the device can be further reduced. Assuming a power added efficiency (PAE) of 40 % the total power dissipation Ptot can be calculated using the following formula:
Ptot = PDC (1- PAE ) = 3W (1- 0.40) = 1.8W
2. Operation without using the internal current control If you don' t want to use the internal current control, it is recommended to connect the negative supply voltage at pin 1 (VTR) instead of pin 2 (VG). In that case VG is not connected.
3. Biasing and use considerations Biasing should be timed in such a way, that the gate voltage (VG) is always applied before the drain voltage (VD), and when returning to the standby mode, the drain voltage has to be removed before the gate voltage.
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17.10.95 HL EH PD 21

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