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SPC81A1 SP
80KB Sound Controller
SEP. 06, 2001 Version 1.3
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPC81A1
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3 2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 3. FEATURES.................................................................................................................................................................................................. 3 4. APPLICATION FIELD ................................................................................................................................................................................. 3 5. SIGNAL DESCRIPTIONS* .......................................................................................................................................................................... 4 6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 5 6.1. CPU ..................................................................................................................................................................................................... 5 6.2. OSCILLATOR .......................................................................................................................................................................................... 5 6.3. MASK OPTION ....................................................................................................................................................................................... 5 6.4. ROM AREA ........................................................................................................................................................................................... 5 6.5. RAM AREA............................................................................................................................................................................................ 5 6.6. MULTI-DUTY-CYCLE MODE..................................................................................................................................................................... 5 6.7. 1/2, 1/3, 1/4 DUTY CYCLE OUTPUTS ...................................................................................................................................................... 5 6.8. MAP OF MEMORY AND I/OS .................................................................................................................................................................... 5 6.9. I/O PORT CONFIGURATIONS* ................................................................................................................................................................. 5 6.10. SERIAL INTERFACE I/O ........................................................................................................................................................................ 6 6.11. SPEECH AND MELODY ......................................................................................................................................................................... 6 6.12. VOLUME CONTROL FUNCTION.............................................................................................................................................................. 6 6.13. POWER SAVINGS MODE ...................................................................................................................................................................... 7 6.14. LOW VOLTAGE RESET ......................................................................................................................................................................... 7 6.15. TIMER/COUNTER................................................................................................................................................................................. 8 7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 9 7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 9 7.2. AC CHARACTERISTICS (TA = 25) ........................................................................................................................................................ 9 7.3. DC CHARACTERISTICS (VDD = 3.0V, TA = 25) ................................................................................................................................... 9 7.4. DC CHARACTERISTICS (VDD = 5.0V, TA = 25) ................................................................................................................................. 10 8. APPLICATION CIRCUITS......................................................................................................................................................................... 11 8.1. APPLICATION CIRCUITS - (1)..................................................................................................................................................................11 8.2. APPLICATION CIRCUITS - (2)................................................................................................................................................................. 12 8.3. APPLICATION CIRCUITS - (3)................................................................................................................................................................. 13 8.4. APPLICATION CIRCUITS - (4)................................................................................................................................................................. 14 9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 15 9.1. PAD ASSIGNMENT ............................................................................................................................................................................... 15 9.2. ORDERING INFORMATION ..................................................................................................................................................................... 15 9.3. PAD LOCATIONS.................................................................................................................................................................................. 16 10. DISCLAIMER............................................................................................................................................................................................. 17 11. REVISION HISTORY ................................................................................................................................................................................. 18
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SPC81A1
80KB SOUND CONTROLLER
1. GENERAL DESCRIPTION
The SPC81A1 is a CPU based two-channel speech/melody synthesizer including CMOS 8-bit microprocessor with 69 instructions, 80K-byte ROM for speech and melody data (Speech is compressed by a 4-bit ADPCM with approx. 26 sec speech duration @ 6KHz sampling rate) and 128-byte working SRAM. It includes two Timer/Counters, 20 Software Selectable I/Os, two 8-bit current outputs D/A (or one PWM audio output) and serial interface I/O port. control purposes. It provides Multi-Duty-Cycle output for remote Volume control is also provided. For audio It In addition, The power
3. FEATURES
! 8-bit microprocessor ! Provides 80K-byte ROM for program and audio data ! 128-byte working SRAM ! Software-based audio processing ! Wide operating voltage: 2.4V - 3.6V @ 4.0MHz 3.6V - 5.5V @ 6.0MHz ! Supports Crystal Resonator or Rosc (with Mask option) ! Max. CPU clock: 4.0MHz @ 2.4V - 3.6V 6.0MHz @ 3.6V - 5.5V ! Standby mode (Clock Stop mode) for power savings. Max. 2A @ 5.0V ! 500ns instruction cycle time @ 4.0MHz CPU clock ! Provides 20 general I/Os ! Two 12-bit timer/counters ! 6 INT sources ! Key wake-up function ! Approx. 26 sec speech @ 6KHz sampling rate with 4-bit ADPCM ! One PWM audio output (single speaker) ! Two DA output
processing, melody and speech can be mixed into one output. operates over a wide voltage range of 2.4V - 5.5V. SPC81A1 has a Clock Stop mode for power savings. causing all other chip functions to be inoperative. clock frequency is 6.0MHz. clock cycles (min.) - 6 clock cycles (max.). commitment and technical support of Sunplus.
savings mode saves the RAM contents, but freezes the oscillator, The Max. CPU The SPC81A1 It has an Instruction Cycle Rate of 2
includes, not only the latest technology, but also the full
2. BLOCK DIAGRAM
! Serial interface I/O port ! Multi-duty-cycle mode ! Volume control function
8-bit microprocessor
80K-byte ROM
Two Timers TimeBase
! Low voltage reset function
128-byte SRAM
INT control
4. APPLICATION FIELD
XI CLK R in XO OSC Serial interface I/O Low Voltage Reset AUD1 Two 8-bit D/As (current) PWM output AUD2
! Intelligent education toys Ex. Pattern to voice (animal, car, color, etc.) Spelling (English or Chinese) Math ! High end toy controller ! Talking instrument controller ! General speech synthesizer ! Industrial controller
20
PINS
GENERAL
I/O
PORT
IOA3-0 (I/O)
IOB1,0 (II/O)
IOB5,4 (I/O)
IOC3-0 (I/O)
IOD7-0 (I/O)
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SPC81A1
5. SIGNAL DESCRIPTIONS*
Mnemonic VDD VSS XI XO TEST RESET AUD1 AUD2 IOA0 IOA1 IOA2 IOA3 PIN No. 14, 19 7, 13 16 15 17 8 18 20 Port A is a 4-bit bi-directional programmable Input / Output port with Pull-high or 6 5 4 3 I/O I/O I/O I/O Open-drain option. As inputs, Port A can be in either the Pure or Pull-high states. As outputs, Port A can be either Buffer or Open-drain NMOS types (Sink current). IOA0: SIO clock output IOA2: Multi-duty cycle output. **See note 1 and 2 below. Port B is a 4-bit bi-directional programmable Input / Output port with Pull-low or IOB0 IOB1 IOB4 IOB5 IOC0 IOC1 IOC2 IOC3 29 30 1 2 12 11 10 9 I/O I/O I/O I/O I/O I/O I/O I/O **See note 1 and 2 below. Port C is a 4-bit bi-directional programmable Input / Output port with Pull-high or Open-drain option. IOC0: SIO Data I/O IOC1: EXT INT PIN IOC2: EXT COUNT IN **See note 1 and 2 below. Port D is an 8-bit bi-directional programmable Input / Output port with Pull-low or IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 28 27 26 25 24 23 22 21 I/O I/O I/O I/O I/O I/O I/O I/O **See note 1 and 2 below. Open-drain option. As inputs, Port D can be either Pure or Pull-low states. As outputs, Port D can be either Buffer or Open-drain PMOS type (send current). Port D can be software programmed for wake-up I/O pins. (Key Change, Wake-up I/O). Also, As inputs, Port C can be in either the Pure or Pull-high states. As outputs Port C can be a Buffer or Open-drain NMOS type. Open-drain option. As inputs, Port B can be in either the Pure or Pull-low states. As outputs, Port B can be either Buffer or Open-drain NMOS types (Sink current). I O Type I I I O Power VDD Power VSS Oscillator crystal input or RESISTOR (Resistor should be connected to VDD) Oscillator crystal output TEST MODE This pin is an active low reset for the chip. AUDIO OUTPUT Description
* Refer to SPC Programming Guide for complete information. **Notes: 1.) Two input states can be specified; Pure Input, Pull-High or Pull Low. 2.) Three output states can be specified as Buffer output, Open Drain PMOS output (send), or Open Drain NMOS output (sink).
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SPC81A1
6. FUNCTIONAL DESCRIPTIONS
6.1. CPU
The SPC81A1 8-bit microprocessor is a high performance processor equipped with Accumulator, Program Counter, X Register, Stack pointer and Processor Status Register (this is the same as the 6502 instruction structure). specifications. SPC81A1 is able to the multi-duty cycle output port. Users can use the combinations of these duty cycles for remote-control purposes.
6.7. 1/2, 1/3, 1/4 Duty Cycle Outputs
Clock
perform with 6.0MHz (max.) depending on the application
1/2 duty cycle
6.2. Oscillator
1/3 duty cycle
The SPC81A1 supports AT-cut parallel resonant oscillated Crystal / Resonator or RC Oscillator or external clock sources by mask option (select one from those three types). recommendations. The design of application circuit should follow the vendors' specifications or The diagrams listed below are typical X'TAL/ROSC circuits for most applications:
1/4 duty cycle
6.8. Map of Memory and I/Os
*I/O PORT:
*MEMORY MAP (From ROM view) $0002 $0003 $0004 $0005 $00100 $00080 $00000
PORT IOA IOB
HW register, I/Os
SPC81A1
XI/R XO
VDD Rosc 20 pf 20 pf
SPC81A1
XI/R XO
IOC IOD
USER RAM and STACK
I/O CONFIG $0000 $0001
UNUSED
$00200
*NMI SOURCE:
SUNPLUS TEST PROGRAM
$00600 USER'S PROGRAM & DATA AREA ROM BANK #0
ROM BANK #1 $10000 UNUSED $14000 ROM BANK #2
(a) Crystal or Ceramic Resonator Connections
(b) RC Oscillator Connections
INTA (from TIMER A)
*INT SOURCE:
$08000
INTA (from TIMER A) INTB (from TIMER B) CPU CLK / 1024 CPU CLK / 8192 CPU CLK / 65536 EXT INT $17FFF
6.3. Mask Option
The SPC81A1 has the following mask option: hSupports Crystal Resonator or Rosc (with mask option).

6.4. ROM Area
The SPC81A1 provides an 80K-byte ROM that can be defined as the program area, audio data area, or both. and access address to fetch data. To access ROM, users should program the BANK SELECT Register, choose bank,
6.9. I/O Port Configurations*
Input/Output IOA port : IOA3 - 0 logic_1 control output data VDD 90K
6.5. RAM Area
The SPC81A1 total RAM consists of 128 bytes (including Stack) at locations from $80 through $FF.
buffer or OD-NMOS
6.6. Multi-Duty-Cycle Mode
The SPC500A1 provides three output waveforms, 1/2, 1/3, and 1/4 duty cycles. The Control Register should be used to select 1/2, 1/3 or 1/4 duty cycle and the IOA2 should be programmed as
input data OD : Open Drain
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SPC81A1
Input/Output IOB port : IOB1 - 0 input data output data logic_2 control OD : Open Drain OD-NMOS or buffer
Input/Output IOD port : IOD7 - 4 input data output data OD-PMOS or buffer
60K
logic_6 control OD : Open Drain
60K
Input/Output IOB port : IOB5 - 4 input data output data logic_3 control OD : Open Drain
Input/Output IOC port : IOC3 - 0 logic_4 control output data VDD 90K
*Values shown are for VDD = 5.0V test conditions only.
6.10. Serial Interface I/O
OD-NMOS or buffer
The SPC81A1 provides serial interface I/O mode for those applications required large ROM/RAM. Serial Interface I/O Port The can be used to read/write data from/to extra memory.
60K
interface I/O Register is the control register for programming interface I/O.
6.11. Speech and Melody
Since the SPC81A1 provides a large ROM and wide range of CPU operation speeds, it is most suitable for speech and melody synthesis. For speech synthesis, the SPC81A1 can provide NMI for accurate sampling frequency. Users can record or synthesize the sound The sound data can be played back
buffer or OD-NMOS
and digitize it into the ROM. program. ADPCM.
in the sequence of the control functions as designed by the user's Several algorithms are recommended for high fidelity and compression of sound including PCM, LOG PCM, and
input data OD : Open Drain
Input/Output IOD port : IOD3 - 0
For melody synthesis, the SPC81A1 provides the dual tone mode.
input data output data logic_5 control OD : Open Drain OD-PMOS or buffer
After selecting the dual tone mode, users only need to fill either TMA or TMB, or both TMA and TMB to generate expected frequency for each channel. routine. The hardware will toggle the tone wave automatically without entering into an interrupt service
60K
Users are able to simulate musical instruments or sound
effects by simply controlling the envelope of tone output.
6.12. Volume Control Function
The SPC81A1 contains a volume control function that provides an 8-step volume controller to control current D/A or PWM output. controller register is provided. A volume control function selector (Enable/Disable) register and
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SEP. 06, 2001 Version: 1.3
SPC81A1
6.13. Power Savings Mode
The SPC81A1 provides a power savings mode (Standby mode) for those applications that require very low stand-by current. To enter standby mode, the Wake-Up Register should be enabled and then stop the CPU clock by writing the STOP CLOCK Register. The CPU will then go to the stand-by mode. In such a mode, RAM and I/Os will remain in their previous states until being awakened. SPC81A1. Port IOD7-0 is the only wake-up source in the After the SPC81A1 is awakened, the internal CPU Wakeup Reset will not affect RAM or
will go to the RESET State (Tw 65536 x T1) and then continue processing the program. I/Os (FIG.1).
Sleep T1 CPU CLK
Wake-up
Reset
Tw
FIG. 1
T1 = 1 / (FCPU), Tw 65536 x T1
6.14. Low Voltage Reset
The SPC81A1 provides a Low Voltage Reset (LVR) function. Below the minimum power-supply voltage of 2.2V, the CPU system will become unstable and malfunction. Low Voltage Reset will reset all functions into the initial operational (stable) state if the VDD power-supply voltage drops below 2.2V (See FIG.2).
T1
CPU CLK VDD
2.2V
T2
RESET T2 2 * T1
TW
(The LVR function is the same as Power ON Reset or External Reset.) FIG. 2
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SPC81A1
6.15. Timer/Counter
The SPC81A1 contains two 12-bit timer/counters, TMA and TMB respectively. TMA can be specified as a timer or a counter, but In the timer mode, TMA and When timer overflows from TMA TMB can only be used as a timer. TMB are re-loaded up-counters. Clock source of Timer/Counter can be selected as follows: Timer/Counter 12-BIT TIMER 12-BIT COUNTER TMB 12-BIT TIMER Clock Source CPU CLOCK (T) or T/4 T/64, T/8192, T/65536 or EXT CLK T or T/4
$0FFF to $0000, the carry signal will make the timer automatically reload to the user's pre-set value and be up-counted again. At the same time, the carry signal will generate the INT signal if the corresponding bit is enabled in the INT ENABLE Register. If TMA is specified as a counter, users can reset by loading #0 into the counter. After the counter has been activated, the value of the counter can also be read from the counters at the same time.
MODE SELECT REGISTER TMA only, select timer or counter TIMER CLOCK SELECTOR Select T or T/4
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SPC81A1
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics DC Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions see AC/DC Electrical Characteristics.
Symbol V+ VIN TA TSTO
Ratings < 7.0V -0.5V to V+ + 0.5V 0 to +60 -50 to +150
For normal operational
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
7.2. AC Characteristics (TA = 25)
Characteristics Symbol Limit Min. Typ. 2.0 4.0 Max. 4.0 6.0 Unit MHz MHz Test Condition VDD = 2.4V - 3.6V, 2-battery VDD = 3.6V - 5.5V, 3-battery
OSC Frequency
FOSC2
7.3. DC Characteristics (VDD = 3.0V, TA = 25)
Characteristics Operating Voltage Operating Current Standby Current Audio output current Input High Level Input Low Level Output High I IOA, IOB, IOC, IOD Output Sink I IOA, IOB, IOC, IOD Input Resistor IOB, IOD Symbol VDD IOP ISTBY IAUD VIH VIL IOH IOL RIN Limit Min. 2.4 2.0 -1.0 2.0 Typ. 1.5 -1.5 100 Max. 3.6 2.0 2.0 0.8 Unit V mA A mA V V mA mA Kohm Test Condition For 2-battery FCPU = 3.0MHz @ 3.0V, no load VDD = 3.0V VDD = 3.0V, one-channel VDD = 3.0V VDD = 3.0V VDD = 3.0V VOH = 2.0V VDD = 3.0V VOL = 0.8V Pull Low VDD = 3.0V
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SPC81A1
7.4. DC Characteristics (VDD = 5.0V, TA = 25)
Characteristics Operating Voltage Operating Current Standby Current Audio output current Input High Level Input Low Level Output High I IOA, IOB, IOC, IOD Output Sink I IOA, IOB, IOC, IOD Input Resistor IOB, IOD Symbol VDD IOP ISTBY IAUD VIH VIL IOH IOL RIN Limit Min. 3.6 3.0 -1.0 4.0 Typ. 4.0 -3.0 60 Max. 5.5 5.0 2.0 0.8 Unit V mA A mA V V mA mA Kohm Test Condition For 3-battery FCPU = 4.0MHz @ 5.0V, no load VDD = 5.0V VDD = 5.0V, one-channel VDD = 5.0V VDD = 5.0V VDD = 5.0V VOH = 4.2V VDD = 5.0V VOL = 0.8V Pull Low VDD = 5.0V
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SPC81A1
SEP. 06, 2001
VDD
VDD
R1 50K 8 RESET IOC3 IOC2 IOC1 IOC0 IOA3 IOA2 IOA1 IOA0 2 1 30 29 14, 19 C3 + 220F C4 - 0.1 IOB5 IOB4 IOB1 IOB0 VDD C1 RESET 0.1 9 10 11 12 3 4 5 6 VDD 15 XO XI AUD1 AUD2 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 16 18 20 21 22 23 24 25 26 C2 0.1
R2 150K
Speaker
Q1
8050
R3
680
SPC81A1
27 28 VSS 7, 13
8. APPLICATION CIRCUITS
8.1. Application Circuits - (1)
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SPC81A1 Application circuit (D/A Output)
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SPC81A1
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VDD
VDD
R1 50K 8 RESET IOC3 IOC2 IOC1 IOC0 IOA3 IOA2 IOA1 IOA0 2 1 30 29 14 ,19 C3 220F + C4 - 0.1 IOB5 IOB4 IOB1 IOB0 VDD C1 RESET 0.1 9 10 11 12 3 4 5 6 VDD 15 XO XI AUD1 AUD2 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 16 18 20 21 22 23 24 25 26 C2 0.1
R2 150K
Speaker
Q1
8050
R3
680
SPRS 256A
VDD SDA SCL CSB VSS
27 28 VSS 7, 13
8.2. Application Circuits - (2)
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VDD
SPC81A1
SPC81A1 Application circuit with Serial Interface I/O Application
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SPC81A1
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VDD
R1 50K 8 RESET IOC3 IOC2 IOC1 IOC0 IOA3 IOA2 IOA1 IOA0 2 1 30 29 14 ,19 C3 + 220F C4 - 0.1 IOB5 IOB4 IOB1 IOB0 VDD C1 RESET 0.1 9 10 11 12 3 4 5 6 VDD 15 XO XI AUD1 AUD2 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 16 18 20 21 22 23 24 25 26
R2 150K
VDD
Speaker ~16
27 28 VSS 7, 13
8.3. Application Circuits - (3)
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SPC81A1
SPC81A1 Application circuit (PWM Output)
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SPC81A1
SEP. 06, 2001
VDD
R1 50K 8 RESET IOC3 IOC2 IOC1 IOC0 IOA3 IOA2 IOA1 IOA0 2 VDD 1 30 29 14 ,19 C3 + 220F C4 - 0.1 IOB5 IOB4 IOB1 IOB0 VDD C1 RESET 0.1 9 10 11 12 3 4 5 6 15 XO XI AUD1 AUD2 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 16 18 20 21 22 23 24 25 26
R2 150K
VDD
Speaker ~16
VDD VDD SDA SCL CSB VSS
SPRS 256A
27 28 VSS 7, 13
8.4. Application Circuits - (4)
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SPC81A1
SPC81A1 Application circuit with Serial Interface I/O Application
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SPC81A1
9. PACKAGE/PAD LOCATIONS
9.1. PAD Assignment
Chip Size: 2500m x 2180m This IC substrate should be connected to VSS
Note1: Chip size included scribe line. Note2: To ensure that the IC function properly, bond all VDD and VSS pins. Note3: The 0.1F capacitor between VDD and VSS should be placed to IC as close as possible.
9.2. Ordering Information
Product Number SPC81A1-nnnnV-C
Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (A = A - Z).
Package Type Chip form
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SPC81A1
9.3. PAD Locations
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PAD Name IOB4 IOB5 IOA3 IOA2 IOA1 IOA0 VSS RESET IOC3 IOC2 IOC1 IOC0 VSS VDD XO XI TEST AUD1 VDD AUD2 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 IOB0 IOB1 X -1039 -1039 -1039 -1039 -1039 -1039 -1024 -1046 -1039 -1039 -1039 -1039 -515 -375 -257 -114 16 268 607 946 1033 1033 1033 1033 1033 1033 1033 1033 1033 1033 Y 890 728 566 415 260 108 -78 -268 -424 -579 -730 -885 -872 -870 -880 -884 -885 -895 -895 -895 -636 -477 -326 -167 -10 159 315 475 631 800
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SPC81A1
10. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. Please note that application circuits
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. illustrated in this document are for reference purposes only.
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SPC81A1
11. REVISION HISTORY
Date OCT. 19, 1999 NOV. 08, 2000 Revision # 1.0 1.1 Original 1. Feature: Wide operating voltage 2.4V-3.6 @ 4.0MHz 2. Feature: 24 sec. Speech @ 6KHz sampling rates with 4-bit ADPCM. 3. DC CHARACTERISTICS (3.0V): Operating Voltage. 3.6(Max) 4. VDD = 2.4V - 3.6V for 2-battery application. 5. Approx. 26 sec. speech. MAR. 14, 2001 1.2 "APPLICATION CIRCUIT NOTES" (1-4): Modify AUD1(17) -> AUD1(18), AUD2(19) -> AUD2(20), VDD(18) -> VDD(19) SEP. 06, 2001 1.3 1. Correct chip size 2. Add Note1 and Note3 in the "9.1 PAD Assignment" 3. Renew to a new document format 15 15 8 - 11 Description Page
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