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K6T4016C3B Family
Document Title
256Kx16 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0 0.1
History
Initial draft Revise - Die name change ; A to B Finalize Revise - Operating current update and release. ICC(Read/Write) = 30/60 15/75mA ICC1(Read/Write) = 30/60 15/75mA ICC2 = 160 130mA Revise - Change datasheet format - Remove ICC write value from table. Revise - Change test load at 55ns: 100pF 50pF Errarta correction Revise - Add 55ns product for industrial temperature
Draft Data
June 28, 1996 September 19, 1996
Remark
Advance Preliminary
1.0 2.0
December 17, 1996 February 17, 1997
Final Final
3.0
February 17, 1998
Final
4.0
June 22, 1998
Final
4.01 5.0
August 8, 1998 May 22, 2001 Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 5.0 May 2001
K6T4016C3B Family
256Kx16 bit Low Power CMOS Static RAM
FEATURES
* * * * * * Process Technology: TFT Organization: 256Kx16 Power Supply Voltage: 4.5~5.5V Low Data Retention Voltage: 2V(Min) Three state output and TTL Compatible Package Type: 44-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6T4016C3B families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature ranges and small package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family K6T4016C3B-B K6T4016C3B-F Operating Temperature Vcc Range Commercial(0~70C) Industrial(-40~85C) Speed 551)/70ns 551)/70/100ns Standby (ISB1, Max) 20A 50A Operating (ICC2, Max) 130mA PKG Type
4.5~5.5V
44-TSOP2-400F/R
1. The parameter is measured with 50pF test load.
PIN DESCRIPTION
A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A12 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A17 A16 A15 A14 A13
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
A13 A14 A0 A1 A15 A16 A17 A2 A3 A4 I/O1~I/O8
Precharge circuit.
Vcc Vss
44-TSOP2 Forward
44-TSOP2 Reverse
Row select
Memory array 1024 rows 256x16 columns
Data cont Data cont Data cont
I/O Circuit Column select
I/O9~I/O16
Name
CS OE WE A0~A17 I/O1~I/O16
Function
Chip Select Input Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs
Name
Vcc Vss UB LB NC
Function
Power Ground Upper Byte(I/O9~16) Lower Byte (I/O1~8) No Connection
WE OE UB LB CS
A8 A9 A10 A5 A6 A7 A4 A12
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 5.0 May 2001
K6T4016C3B Family
PRODUCT LIST
Commercial Temperature Product(0~70C) Part Name K6T4016C3B-TB55 K6T4016C3B-TB70 K6T4016C3B-RB55 K6T4016C3B-RB70 Function 44-TSOP2-F, 55ns, LL-pwr 44-TSOP2-F, 70ns, LL-pwr 44-TSOP2-R, 55ns, LL-pwr 44-TSOP2-R, 70ns, LL-pwr
CMOS SRAM
Industrial Temperature Products(-40~85C) Part Name K6T4016C3B-TF55 K6T4016C3B-TF70 K6T4016C3B-TF10 K6T4016C3B-RF55 K6T4016C3B-RF70 K6T4016C3B-RF10 Function 44-TSOP2-F, 55ns, LL-pwr 44-TSOP2-F, 70ns, LL-pwr 44-TSOP2-F, 100ns, LL-pwr 44-TSOP2-R, 55ns, .LL-pwr 44-TSOP2-R, 70ns, .LL-pwr 44-TSOP2-R, 100ns, LL-pwr
FUNCTIONAL DESCRIPTION
CS H L L L L L L L L OE X1) H X1) L L L X1) X X
1) 1)
WE X1) H X1) H H H L L L
LB X1) X1) H L H L L H L
UB X1) X1) H H L L H L L
I/O1~8 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din
I/O9~16 High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din
Mode Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Active Active Active Active Active Active Active Active
1. X means dont care. (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol VIN,VOUT VCC PD TSTG TA TSOLDER Ratings -0.5 to 7.0 -0.5 to7.0 1.0 -65 to 150 0 to 70 -40 to 85 260C, 10sec(Lead Only) Unit V V W C C C Remark K6T4016C3B-B K6T4016C3B-F -
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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Revision 5.0 May 2001
K6T4016C3B Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.2 -0.5 3) Typ 5.0 0 -
CMOS SRAM
Max 5.5 0 Vcc+0.5 0.8
2)
Unit V V V V
Note: 1. Commercial Product: TA=0 to 70C, otherwise specified Industrial Product: TA=-40 to 85C, otherwise specified 2. Overshoot: VCC+3.0V in case of pulse width 30ns 3. Undershoot: -3.0V in case of pulse width 30ns 4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply Average operating current
Symbol
Test Conditions VIN=Vss to Vcc CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS=VIL, VIN=VIL or VIH, Read Cycle time=1s, 100% duty, IIO=0mA CS0.2V, VIN0.2V or VINVcc-0.2V Read Write
Min
Typ
Max
Unit
ILI ILO ICC ICC1 ICC2
-1 -1 2.4 -
-
1 1 15 15 75 130 0.4 3 201)
A A mA mA mA V V mA A
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL IOL=2.1mA IOH=-1.0mA CS=VIH, Other inputs=VIL or VIH CSVcc-0.2V, Other inputs=0~Vcc
Output low voltage Output high voltage Standby Current (TTL)
Standby Current(CMOS) 1. Industrial Product = 50A
VOL VOH ISB ISB1
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Revision 5.0 May 2001
K6T4016C3B Family
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level: 0.8 to 2.4V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): CL=100pF+1TTL CL=50pF+1TTL CL1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=4.5~5.5V, Commercial product: TA=0 to 70C, Industrial product: TA=-40 to 85C)
Speed Bins Parameter List Symbol 55ns Min Read cycle time Address access time Chip select to output Output enable to valid output Chip select to low-Z output Read Output enable to low-Z output UB, LB enable to low-Z output Chip disable to high-Z output Output Disable to High-Z Output UB, LB disable to high-Z output Output hold from address change LB, UB valid to data output Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write pulse width Write Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z LB, UB valid to end of write tRC tAA tCO tOE tLZ tOLZ tBLZ tHZ tOHZ tBHZ tOH tBA tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW tBW 55 10 5 5 0 0 0 10 55 45 0 45 45 0 0 25 0 5 45 Max 55 55 25 20 20 20 25 20 Min 70 10 5 5 0 0 0 10 70 60 0 60 55 0 0 30 0 5 60 70ns Max 70 70 35 25 25 25 35 25 100ns Min 100 10 5 5 0 0 0 10 100 80 0 80 70 0 0 40 0 5 Max 100 100 50 30 30 30 50 30 80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time
1. Industrial Product: 20A
Symbol VDR IDR tSDR tRDR
Test Condition CSVcc-0.2V Vcc=3.0V See data retention waveform
Min 2.0 0 5
Typ -
Max 5.5 15 1)
Unit V A ms
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Revision 5.0 May 2001
K6T4016C3B Family
TIMING DIAGRAMS
CMOS SRAM
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC Address tOH Data Out Previous Data Valid tAA Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO tOH
CS
tHZ UB, LB tBA tBHZ OE tOLZ tBLZ tLZ Data Valid tOE tOHZ
Data out
High-Z
NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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Revision 5.0 May 2001
K6T4016C3B Family
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
CMOS SRAM
tWC Address tCW(2) CS tAW tBW tWP(1) WE tAS(3) tDW Data in High-Z tWHZ Data out Data Undefined Data Valid tOW tDH High-Z tWR(4)
UB, LB
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS Controlled)
tWC Address tAS(3) CS tAW tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
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Revision 5.0 May 2001
K6T4016C3B Family
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC Address tCW(2) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4)
CMOS SRAM
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC 4.5V tSDR Data Retention Mode tRDR
2.2V VDR CSVCC - 0.2V CS GND
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Revision 5.0 May 2001
K6T4016C3B Family
PACKAGE DIMENSIONS
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
CMOS SRAM
Units: millimeter(inch)
0~8 0.25 ( ) 0.010 #44 #23 0.45 ~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
10.16 0.400
( 0.50 ) 0.020
#1
#22 1.000.10 0.0390.004 1.20 MAX. 0.047
0.15 0
0 + 0.1 5 - 0.0 04 + 0.0 02 .006 - 0.0
18.81 MAX. 0.741 18.410.10 0.7250.004
( 0.805 ) 0.032
0.350.10 0.0140.004
0.80 0.0315
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0.25 ( ) 0.010 #1 #22
0.05 MIN. 0.002
0.10 0.004 MAX
0~8
0.45 ~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
10.16 0.400
( 0.50 ) 0.020
#44
#23 1.000.10 0.0390.004 1.20 MAX. 0.047
0.15 0
0 + 0.1 5 - 0.0 04 + 0.0 02 .006 - 0.0
18.81 MAX. 0.741 18.410.10 0.7250.004
( 0.805 ) 0.032
0.350.10 0.0140.004
0.80 0.0315
9
0.05 MIN. 0.002
0.10 0.004 MAX
Revision 5.0 May 2001

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