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www.fairchildsemi.com
Green Mode Fairchild Power Switch (FPSTM) for CRT Monitors
Features
* Burst Mode Operation to Reduce the Power Consumption in Standby Mode * External Pin for Synchronization * Wide Operating Frequency Range up to 130kHz * Internal Startup Circuit * Low Operating Current (Max:6mA) * Pulse by Pulse Current Limiting * Over Voltage Protection (Auto Restart Mode) * Over Load Protection (Auto Restart Mode) * Abnormal Over Current Protection (Auto Restart Mode) * Internal Thermal Shutdown (Auto Restart Mode) * Under Voltage Lockout * Internal High Voltage SenseFET (650V) OUTPUT POWER TABLE(3)
PRODUCT FSES0765RG 230VAC 15%(2) Open Frame(1) 90 W 85-265VAC Open Frame(1) 70 W
FSES0765RG
Notes: 1. Maximum practical continuous power in an open frame design at 50C ambient. 2. 230 VAC or 100/115 VAC with doubler. 3. The maximum output power can be limited by the junction temperature
Application
* CRT Monitor
Typical Circuit
Vo
Description
FSES0765RG is a Fairchild Power Switch (FPS) specially designed for off-line SMPS of CRT monitors with minimal external components. This device combines a current mode PWM controller with a high voltage power SenseFET in a single package. The PWM controller features an integrated oscillator to be synchronized with the external sync signal, under voltage lockout, optimized gate driver and temperature-compensated precise current sources for the loop compensation. This device also includes various fault protection circuits such as over voltage protection, over load protection, abnormal over current protection and over temperature protection. Compared with discrete MOSFET and PWM controller solutions, FPS can reduce total cost, component count, size and weight while simultaneously increasing efficiency, productivity and system reliability. This device is well suited for cost effective CRT-monitor power supplies.
AC IN Vstr Drain FSES0765RG
PWM
VSync VFB Vcc GND
External Sync signal
Figure 1. Typical Flyback Application
Rev.1.0.1
(c)2005 Fairchild Semiconductor Corporation
FSES0765RG
Internal Block Diagram
Vcc
Vref
3
Vstr 6
Drain 1
Vth=8.5/9V Vcc 0.8V
5V
+
ICH
-
Vref Burst Sync detect Vcc good Internal Bias
50k
7V
9V/12V (Normal) 7.5V/12V (burst)
Turn-On
5 Vsync
6V Turn-Off
Vcc Idelay
Vref IFB
OSC
PWM 2.5R
S
Q
VFB 4
Soft start (15ms)
R
Q
Gate driver
R
LEB
VSD Vcc
S Q
2 GND
Vovp TSD Vcc good
R Q
AOCP
Vocp
Figure 2. Functional Block Diagram of FSES0765RG
2
FSES0765RG
Pin Definitions
Pin Number 1 2 3 Pin Name Drain GND Vcc Pin Function Description This pin is the high voltage power SenseFET drain connection. This pin is the control ground and the SenseFET source. This pin is the positive supply input. This pin provides the internal operating current for both start-up and steady-state operation. This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 7.5V, the over load protection triggers resulting in shutdown of the FPS. This pin is for synchronized switching. For proper synchronization, a pulse signal should be applied on this pin. The internal MOSFET is turned on being synchronized by the falling edge of this signal. This pin is connected directly to the high voltage DC link. At startup, the internal high voltage current source supplies the internal bias and charges the external capacitor that is connected to the Vcc pin. Once Vcc reaches 12V, the internal current source is disabled.
4
Vfb
5
Vsync
6
Vstr
Pin Configuration
TO-220-6L
6. Vstr FSES0765RG 5. Vsync 4. VFB 3. Vcc 2. GND 1. Drain
Figure 3. Pin Configuration (Top View)
3
FSES0765RG
Absolute Maximum Ratings
(Ta=25C, unless otherwise specified) Parameter Drain Voltage Vstr Voltage Drain Current Pulsed
(1)
Symbol VDS Vstr IDM ID ID EAS VCC Vsync VFB PD TJ TA TSTG Rthjc BVpkg
-
Value 650 650 15 7 4.5 570 20 -0.3 to 13 -0.3 to 10 145 +150 -25 to +85 -55 to +150 0.86 3500 2.0 300
Unit V V A A A mJ V V V W C C C C/W V kV V
Continuous Drain Current (Tc = 25C, with infinite heat sink) Continuous Drain Current (Tc=100C, with infinite heat sink) Single pulsed Avalanche Energy Supply Voltage Analog Input Voltage Range Total Power Dissipation (Tc = 25C , with infinite heat sink) Operating Junction Temperature Operating Ambient Temperature Storage Temperature Range Thermal Resistance Drain to PKG Breakdown Voltage (3) ESD Capability, HBM Model (All pins except Vstr and Vfb) ESD Capability, Machine Model (All pins except Vstr and Vfb)
Notes: 1. Repetitive rating: Pulse width limited by maximum junction temperature 2. Lm=21mH, Vdd=50V, Rg=25, starting Tj=25C 3. 60Hz AC
(2)
4
FSES0765RG
Electrical Characteristics (Continued)
(Ta=25C unless otherwise specified) Parameter SENSEFET SECTION Drain-Source Breakdown Voltage BVDSS VGS = 0V, ID = 250A VDS = Max, Rating, VGS = 0V VDS= 0.8*Max., Rating VGS = 0V, TC = 85C VGS = 10V, ID = 2.3A VGS = 0V, VDS = 25V, f = 1MHz VFB=5V VFB=5V VFB=0V VFB=5 11V Vcc 18V VFB=5 VFB = 0V, Vcc=15V VFB = 0V, Vcc=8.7V 0V VFB 0.4V VFB 6.9V VFB = 4V Vcc 17V 650 1.4 100 250 300 1.6 130 V A A
Symbol
Condition
Min. Typ. Max. Unit
Zero Gate Voltage Drain Current
IDSS
Static Drain-source on Resistance Output Capacitance UVLO SECTION Vcc Start Threshold Voltage Vcc Stop Threshold Voltage (Normal operation) Vcc Stop Threshold Voltage (Burst operation) OSCILLATOR SECTION Initial Frequency Voltage Stability Maximum Duty Cycle Minimum Duty Cycle FEEDBACK SECTION Feedback Source Current (Normal operation) Feedback Source Current (Burst operation) Feedback Voltage Threshold to Stop Switching Shutdown Feedback Voltage Shutdown Delay Current PROTECTION SECTION Over Voltage Protection Over Current Protection Threshold Voltage Thermal Shutdown Temp
(2) (1)
RDS(ON) Coss
pF
VSTART VSTOP VBSTOP FOSC FSTABLE DMAX DMIN IFB IBFB VOFF VSD IDELAY VOVP VAOCP TSD
11 8.5 7 18 0 48 0.7 70 0.2 7 1.6 18 0.9 140
12 9 7.5 20 1 55 0 0.9 100 0.3 7.5 2 19 1.0 -
13 9.5 8 22 3 62 1.1 130 0.4 8 2.4 20 1.1 -
V V V kHz % % % mA uA V V A V V C
Note: 1. These parameters, although guaranteed in design, are tested only in EDS (wafer test) process. 2. These parameters, although guaranteed in design, are not tested in mass production.
5
FSES0765RG
Electrical Characteristics (Continued)
(Ta=25C unless otherwise specified) Parameter Sync SECTION Low Sync Threshold Voltage High Sync Threshold Voltage Sync blanking time BURST MODE SECTION Burst Mode Enable Feedback Voltage Burst Mode Peak Current Limit
(1)
Symbol VSL VSH TSYB VBFB IBPK FSB VccH VccL TSS ILIM ICH
(3)
Condition
Min. Typ. Max. 5.6 6 7 5 0.8 0.6 50 9 8.5 15 4 1.5 3.5 1.5 6.4 7.5 7 0.9 0.75 60 9.4 8.9 20 4.48 1.8 6 3
Unit V V us V A kHz V V ms A mA mA mA
Vcc=15V, VFB=5V
6.5 3
Vcc=8.5V Vcc=8.8V, VFB=0V Vcc=8.8V, VFB=0V
0.7 0.45 40 8.6 8.1
Switching Frequency in Burst Mode Vcc High Threshold Voltage in Burst Mode Vcc Low Threshold Voltage in Burst Mode SOFTSTART SECTION Soft start Time (1) Peak Current Limit (2) TOTAL DEVICE SECTION Startup Charging Current Operating Supply Current - In normal operation - In burst mode
VFB=4V Vcc=15V, VFB=5V VSTR=650V, Vcc=0V Vcc=15V, VFB=5V Vcc=8.7V, VFB=0V
10 3.52 1.2 -
CURRENT LIMIT(SELF-PROTECTION)SECTION
IOP IOB
Note: 1. These parameters, although guaranteed in design, are tested only in EDS (wafer test) process. 2. These parameters indicate the Inductor current. 3. These parameters apply to the current flowing into the control IC.
6
FSES0765RG
Comparison of FS6S0765RC, FS8S0765RC and FSES0765RG
Function Startup Resistor Operating Supply Current Control Method Vcc OVP Threshold Vcc Hysteresis Level in Burst Mode Soft Start Switching Frequency in Burst Mode Current Peak in Burst Mode FS6S0765RC Required Istart=170uA (max) 15mA (max) SSR 30V 11/12V With external capacitor 50kHz 0.6A FS8S0765RC Required Istart=80uA (max) 15mA (max) PSR 37V 11/12V With external capacitor 40kHz 0.6A FSES0765RG Not Required (Internal startup circuit) 6mA (max) : Normal mode 3mA (max) : Burst mode SSR 20V 8.5/9V Internal soft-start (15ms) 50kHz 0.6A
7
FSES0765RG
Electrical Characteristics
(These characteristic graphs are normalized at Ta= 25C)
1.4
1.4
1.0
V START [Normalized]
-40 0 40 80 120 160
1.2
1.2
I CH [Normalized]
1.0
0.8
0.8
0.6
0.6 -40 0 40 80 120 160
Temp[? ]
Temp[? ]
Start Up Charging Current vs. Temp.
Vcc Start Voltage vs. Temp.
1.4
1.4
V NSTOP [Normalized]
1.0
V BSTOP [Normalized]
-40 0 40 80 120 160
1.2
1.2
1.0
0.8
0.8
0.6
0.6 -40 0 40 80 120 160
Temp[? ]
Temp[? ]
Normal Mode Vcc Stop Voltage vs. Temp.
Burst Mode Vcc Stop Voltage vs. Temp.
1.4
1.4
1.2
1.2
1.0
D MAX [Normalized]
-40 0 40 80 120 160
F OSC [Normalized]
1.0
0.8
0.8
0.6
0.6 -40 0 40 80 120 160
Temp[? ]
Temp[? ]
Initial Frequency vs. Temp.
Maximum Duty Cycle vs. Temp.
8
FSES0765RG
Electrical Characteristics
(These characteristic graphs are normalized at Ta= 25C)
1.4
1.4
1.2
1.2
V OVP [Normalized]
1.0
I NFB [Normalized]
-40 0 40 80 120 160
1.0
0.8
0.8
0.6
0.6 -40 0 40 80 120 160
Temp[? ]
Temp[? ]
OVP Threshold Voltage vs. Temp.
Normal Mode Feedback Current vs. Temp.
1.4
1.4
1.2
1.2
I DELAY [Normalized]
-40 0 40 80 120 160
I BFB [Normalized]
1.0
1.0
0.8
0.8
0.6
0.6 -40 0 40 80 120 160
Temp[? ]
Temp[? ]
Burst Mode Feedback Current vs. Temp.
Feedback Delay Current vs. Temp.
1.4
1.4
1.2
I BUPK [Normalized]
-40 0 40 80 120 160
V SD [Normalized]
1.2
1.0
1.0
0.8
0.8
0.6
0.6 -40 0 40 80 120 160
Temp[? ]
Temp[? ]
OLP Threshold Voltage vs. Temp.
Burst Mode Peak Drain Current vs. Temp.
9
FSES0765RG
Electrical Characteristics
(These characteristic graphs are normalized at Ta= 25C)
1.4
1.4
1.2
1.2
1.0
V SH [Normalized]
-40 0 40 80 120 160
V SL [Normalized]
1.0
0.8
0.8
0.6
0.6 -40 0 40 80 120 160
Temp[? ]
Temp[? ]
Low Sync Threshold Voltage vs. Temp.
High Sync Threshold Voltage vs. Temp.
2.0 1.4 1.6
1.2
I LIM [Normalized]
0 40 80 120 160
T SY [Normalized]
1.2
0.8
1.0
0.4
0.8
0.0 -40
0.6 -40
0
40
80
120
160
Temp[? ]
Temp[? ]
Sync Blanking Time vs. Temp.
Pulse-by-Pulse Current Limit vs. Temp.
10
FSES0765RG
Functional Description
1. Startup : In previous generations of Fairchild Power Switches (FPSTM) the Vcc pin had an external start-up resistor to the DC input voltage line. In this generation the startup resistor is replaced by an internal high voltage current source. At startup, an internal high voltage current source supplies the internal bias and charges the external capacitor (Cvcc) that is connected to the Vcc pin as illustrated in figure 4. When Vcc reaches 12V, the FPS begins switching and the internal high voltage current source is disabled. Then, the FPS continues its normal switching operation and the power is supplied from the auxiliary transformer winding unless Vcc goes below the stop voltage of 9V.
2.1 Pulse-by-pulse Current Limit: Because current mode control is employed, the peak current through the Sense FET is limited by the inverting input of the PWM comparator (Vfb*) as shown in figure 5. Assuming that the 0.9mA current source flows only through the internal resistor (2.5R +R= 2.8 k), the cathode voltage of diode D2 is about 2.5V. Since diode D1 is blocked when the feedback voltage (Vfb) exceeds 2.5V, the maximum voltage of the cathode of D2 is clamped at this voltage, thus clamping Vfb*. Therefore, the peak value of the SenseFET current is limited.
VDC CVcc
2.2 Leading Edge Blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FPS employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (TLEB) after the Sense FET is turned on.
Vcc 3 6
Vstr
Vcc Vref IFB
OSC
Istart
Vref 9V/12V Vcc good Internal Bias
Vo Vfb
H11A817A
CB
Idelay
4 D1 D2 2.5R + Vfb*
SenseFET
R
Gate driver
KA431
-
Figure 4. Internal Startup Circuit
VSD
OLP
Rsense
Figure 5. Pulse Width Modulation (PWM) Circuit
2. Feedback Control : FSES0765RG employs current mode control, as shown in figure 5. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. When the reference pin voltage of the KA431 exceeds the internal reference voltage of 2.5V, the H11A817A LED current increases, thus pulling down the feedback voltage and reducing the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased.
3. Protection Circuits : The FSES0765RG has several self protective functions such as over load protection (OLP), abnormal over current protection (AOCP), over voltage protection (OVP) and thermal shutdown (TSD). Because these protection circuits are fully integrated into the IC without requiring external components, the reliability can be improved without increasing cost. Once the fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage, 9V, the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When Vcc reaches the UVLO start voltage,12V, the FPS resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated (see figure 6). 11
FSES0765RG
Vds
Power on
Fault occurs
VFB
Fault removed
7.5V
Over load protection
2.5V
Vcc
T12= Cfb*(7.5-2.5)/Idelay
12V 9V
T1
T2
t
Figure 7. Over Load Protection
t
Normal operation Fault situation Normal operation
Figure 6. Auto restart operation
AOCP Vaocp
-
Figure 8. AOCP Block
3.3 Over Voltage Protection (OVP) : If the secondary side feedback circuit malfunctions or a solder defect causes an open in the feedback path, the current through the optocoupler transistor becomes almost zero. Then, Vfb climbs up in a manner similar to the over load situation, forcing the preset maximum current to be supplied to the SMPS until the over load protection is activated. Because more energy than required is provided to the output, the output voltage may 12
+
3.1 Over Load Protection (OLP) : Overload occurs when the load current exceeds a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated in order to protect the SMPS. However, even when the SMPS is in the normal operation, the over load protection circuit can be activated during the load transition. In order to avoid this undesired operation, the over load protection circuit is designed to be activated after a specified time to determine whether it is a transient or overload situation. Because of the pulse-by-pulse current limit capability, the maximum peak current through the Sense FET is limited, and therefore the maximum input power is restricted with a given input voltage. If the output consumes beyond this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the optocoupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (Vfb). If Vfb exceeds 2.5V, D1 is blocked and the 2uA current source (Idelay) starts to charge CB slowly up to Vcc. In this condition, Vfb continues increasing until it reaches 7.5V, then the switching operation is terminated as shown in figure 7. The delay time for shutdown is the time required to charge CB from 2.5V to 7.5V with 2uA. In general, a 10 ~ 50 ms delay time is typical for most applications.
3.2 Abnormal Over Current Protection (AOCP) : Even though the FPS has OLP (Over Load Protection) and current mode PWM feedback, these protections are not enough to protect the FPS when a secondary side diode short or a transformer pin short occurs. The FPS has an internal AOCP (Abnormal Over Current Protection) circuit, as shown in figure 8. When the gate turn-on signal is applied to the power Sense FET, the AOCP block is enabled and monitors the current through the sensing resistor. The voltage across the resistor is then compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level, the reset signal is applied to the latch, resulting in the shutdown of SMPS.
2.5R
OSC
PWM
S
Q
R
Q
Gate driver
R
LEB
Rsense 2 GND
FSES0765RG
exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is employed. In general, Vcc is proportional to the output voltage and the FPS uses Vcc instead of directly monitoring the output voltage. If VCC exceeds 19V, an OVP circuit is activated resulting in the termination of the switching operation. In order to avoid undesired activation of OVP during normal operation, Vcc should be designed to be below 19V. 3.4 Thermal Shutdown (TSD) : The Sense FET and the control IC are built in one package. This makes it easy for the control IC to detect the heat generation from the Sense FET. When the temperature exceeds approximately 150C, the thermal shutdown is activated. 4. Synchronization : Since the FSES0765RG is designed for CRT Monitor applications, this device has a synchronization function to minimize the screen noise. The MOSFET is turned on being synchronized to the external synchronization signal as shown in figure 9. In order to reduce voltage stress on the secondary side rectifier, a double pulse prevention function is included as well. The MOSFET's turn-on is inhibited for 5us after the MOSFET is turned off in order to eliminate a double pulse situation.
5. Soft Start : The FPS has an internal soft start circuit that slowly increases the PWM comparator's inverting input voltage together with the Sense FET current during startup. The typical soft start time is 15ms. The pulse width to the power switching device progressively increases to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors also progressively increases with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. 6. Burst operation : In order to minimize the power consumption in the standby mode, the FSES0765RG employs burst operation. Once FSES0765RG enters into burst mode, effective switching frequency and all output voltages are reduced. Figure 10 shows the typical feedback circuit to force the FSES0765RG to enter burst operation. In normal operation, the picture on signal is applied and the transistor Q1 is turned on, which de-couples R3 and D1 from the feedback network. Therefore, only Vo1 is regulated by the feedback circuit in normal operation and determined by R1 and R2 as
V o1
norm
R1 + R2 = 2.5 ------------------- R2
Sync signal
7.0V 6.0V
MOSFET turn-off
MOSFET turn-On
In standby mode, the picture on signal is disabled and the transistor Q1 is turned off, which couples R3 and D1 to the reference pin of KA431. Then, the voltage on the reference pin of KA431 is higher than 2.5V and the current through the opto coupler increases, which increases the current through the opto LED. This pulls down the feedback voltage (VFB) of FPS and forces FPS to stop switching until Vcc drops to 8.5V. When Vcc reaches 8.5V, the FPS starts switching with a switching frequency of 50kHz and a peak drain current of 0.6A until Vcc reaches 9V. When Vcc reaches 9V, the switching operation is terminated again until Vcc reduces to 8.5V.
VO2 VO1 (B+)
RD Rbias R3
Linear Regulator Micom
Sync signal 7.0V 6.0V
Current limit level determined by feedback voltage
CF RF
R1 D1
Q1
Picture ON
Drain Current
KA431
C A
R
R2
5us sync detect blanking
5us sync detect blanking
Figure 9. Synchronization Operation
Figure 10. Typical feedback Circuit for FPS Burst Operation
13
FSES0765RG
Typical application Circuit
Application Output power Input voltage Universal input CRT-Monitor 64W (85-265Vac) Output voltage (Max current) 80V (0.15A) 50V (0.70A) 14V (0.8A) -14V (0.3A) 6.5V (0.3A)
Features
* * * * * * High efficiency (>80% at 85Vac input) Synchronized switching Low standby mode power consumption (<1W) Low component count Enhanced system reliability through various protection functions Internal soft-start (15ms)
1. Schematic
T1 EER4044 1 R101 68k 2W C107 47nF 630V 2 C106 220uF 400V 3 D101 UF 4007 4 16 D201 RG4C
L201 13uH 180V R201 300k 0.25W R202 4.2k 0.25W 80V C203 47uF 160V 13 D203 UG4D L203 13uH C205 1000uF 35V C206 1000uF 35V 15V C204 47uF 160V
BD101 KBU6G
C201 22uF 400V L202 13uH
C202 22uF 400V
15 D202 SUF15J 14
R209 33k 0.25W
RT101 10D-9
C105 47nF 12
LF101 1.2mH
IC101 FSES0765 5 C108 1uF 50V R104 470 0.25W C109 47nF
6 Vsync 1
11 Drain
D204 UG4D C207 1000uF 35V D205 UG4D C209 1000uF 16V 9
L204 13uH
-15V C208 1000uF 35V
C103 4.7nF
C104 4.7nF
External Sync
4 Vfb GND 2
Vcc 3 C110 47uF 50V R102 6 D102 15 UF4004 0.25W 7
10
L205 13uH
6.5V C210 1000uF 16V
C102 47nF
C301 4.7nF
C302 4.7nF
VAR101 10D471K
F101 FUSE 250V 3.0A
IC301 HC11A817A
R203 1k 0.25W R204 1k 0.25W R206 2.7k 0.25W R207 4.7k 0.25W
IC202 KA7805 1 Input Output 3
5V, 0.13A
GND 2 C212 100uF 16V
R205 C211 33k 47nF 0.25W
D206 UF4004
R210 39 0.25W
SW 201 Switch R208 4.7k 0.25W
IC201 KA431
Q201 KSC945
14
FSES0765RG
2. Transformer Schematic Diagram
EER3540 N p1 1 2 N p2 3 4 5 Na 6 7 8 16 15 N 80V
Np1 Na N50V
14 13
N 50V
N14V N-14V
12 11 10
N 14V N -14V N 6.5V
N6.5V N80V Np2
9
3.Winding Specification No Np2 N80V N6.5V N-14V N14V N50V Na Np1 Pin (sf) 2-1 16 - 15 10 - 9 9 - 11 12 - 9 14 - 13 6-8 4-3 Wire 0.3 x 2 0.3

Turns 20 10 3 5 6 22 8 20
Winding Method Center Winding Center Winding Center Winding Center Winding Center Winding Center Winding Center Winding Center Winding
x1
0.3 x 2 0.3 x 1 0.3

x2
0.3 x 3 0.2 x 1 0.3 x2
4.Electrical Characteristics
Pin Inductance Leakage Inductance 1-4 1-4
Specification 420uH 5% 5uH Max
Remarks 1kHz, 1V 2
nd
all short
5. Core & Bobbin Core : EER 3540 Bobbin : EER3540 Ae : 107 mm2
15
FSES0765RG
Package Dimensions
Dimensions in Millimeters
TO-220-6L(Forming)
4.70 4.30 10.10 9.70 2.90 2.70 1.40 1.25
15.90 15.50 9.40 9.00
20.00 19.00
(13.55) 23.80 23.20
R0.55 (0.75) R0.55 8.30 MAX1.10 7.30 MAX0.80 0.70 0.50 0.60 0.45 3.48 2.88
(0.65)
2.60 2.20 (7.15)
2.19
1.75 1.27 3.81
10.20 9.80
16
FSES0765RG
Ordering Information
Product Number FSES0765RGWDTU Package TO-220-6L(Forming) Marking Code ES0765R BVdss 650V Rds(ON) Max. 1.6
17
FSES0765RG
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 10/4/05 0.0m 001 (c) 2005 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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