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HD404344R Series/HD404394 Series
Rev. 7.0 Sept. 1999 Description
The HD404344R series and HD404394 series 4-bit microcomputers are products of the HMCS400 series, which is designed to make application systems compact while realizing higher performance and increasing program productivity. Each microcomputer has an A/D converter, two timers and a serial interface. The HD404344R series includes the HD404344R with on-chip 4-kword ROM, HD404342R with 2-kword ROM, and HD404341R with 1-kword ROM. The HD404394 series includes the HD404394 with on-chip 4-kword ROM, HD404392 with 2-kword ROM, and HD404391 with 1-kword ROM. The HD4074344 and HD4074394 are the PROM version ZTATTM microcomputers. Programs can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The PROM program specifications are the same as for the 27256.) ZTATTM: Zero Turn Around Time ZTAT is a Trademark of Hitachi Ltd.
Features
* Input/output pins HD404344R series, HD4074344: 22 pins (10pins: Large-current I/O pins) HD404394 series: 21 pins (3 pins: intermediate-voltage NMOS open drain I/O; 5 pins: NMOS open drain I/O with 15-mA high-current driver) * Two timer/counters One timer output One event counter input (with programmable edge detection) * 8-bit clock-synchronous serial interface (1 channel) * On-chip A/D converter HD404344R series, HD4074344: 8 bit x 4 channel HD404394 series: 8 bit x 3 channel (with Vref pin) * Built-in oscillator
HD404344R Series/HD404394 Series
HD404344R Series Ceramic oscillator, CR oscillation, External clock drive is also possible. HD404394 Series, HD4074344 Ceramic oscillator, External clock drive is also possible. Five interrupt sources One by external source (with programmable edge detection) Four by internal sources Subroutine stack Maximum 16 levels including interrupts Two low-power dissipation modes Standby mode Stop mode One input signal to return from stop mode Instruction cycle time 1 s (fOSC = 4 MHz)
*
* *
* *
2
HD404344R Series/HD404394 Series
Type of Products
Product Name Type Mask ROM HD404344R Series*1 HD404341RS HD40C4341RS HD404342RS HD40C4342RS HD404344RS HD40C4344RS HD404341RFP HD40C4341RFP HD404342RFP HD40C4342RFP HD404344RFP HD40C4344RFP HD404341RFT HD40C4341RFT HD404342RFT HD40C4342RFT HD404344RFT HD40C4344RFT HCD404344R HCD40C4344R ZTATTM HD4074344S HD4074344FP HD4074344FT Note: HD4074394S HD4074394FP HD4074394FT 4,096 DP-28S FP-28DA FP-30D ---- 4,096 Chip *3 *4 HD404394FT 4,096 HD404392FT 2,048 HD404391FT 1,024 FP-30D HD404394FP 4,096 HD404392FP 2,048 HD404391FP 1,024 FP-28DA HD404394S 4,096 HD404392S 2,048 HD404394 Series HD404391S ROM (words) 1,024 RAM (digit) 256 Package DP-28S
1. The HD404344R Series is available in a mask ROM version only. 2. ZTATTM chip shipment is not supprted. 3. The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details.
3
HD404344R Series/HD404394 Series
List of Functions
Mask ROM item Operating voltage (V) Instruction cycle time (typ.) HD404341R 2.5 to 5.5 1 s (fosc = 4.0 MHz) ROM (Words) RAM (Digits) I/O High-current I/O pins (Sink 15 mA max) Timer functions Free running timer Reload timer 2 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 2 2 2 2 2 2 1,024 256 22 10 HD404342R 2.5 to 5.5 1 s (fosc = 4.0 MHz) 2.048 256 22 10 HD404344R 2.5 to 5.5 1 s (fosc = 4.0 MHz) 4,096 256 22 10 HCD404344R HD40C4341R HD40C4342R HD40C4344R 2.5 to 5.5 1 s (fosc = 4.0 MHz) 4,096 256 22 10 1,024 256 22 10 2,048 256 22 10 4,096 256 22 10 2.5 to 5.5 2 s (Rf = 20 k) 2.5 to 5.5 2 s (Rf = 20 k) 2.5 to 5.5 2 s (Rf = 20 k)
Event counter 1 Watchdog timer Serial interface A/D converter Interrupt External Internal Low-power modes Stop mode Standby mode Oscillator Ceramic oscillation RC oscillation Package -- DP-28S FP-28DA FP-30D Guaranteed operation temperature (C) -20 to +75 1 8bit x 4ch 1 4 2 1
1 8bit x 4ch 1 4 2
1 8bit x 4ch 1 4 2
1 8bit x 4ch 1 4 2
1 8bit x 4ch 1 4 2
1 8bit x 4ch 1 4 2
1 8bit x 4ch 1 4 2
l l l
l l l
-- DP-28S FP-28DA FP-30D -20 to +75
l l l
-- DP-28S FP-28DA FP-30D -20 to +75
l l l
-- Chip
l l
--
l l
--
l l
--
l
DP-28S FP-28DA FP-30D
l
DP-28S FP-28DA FP-30D -20 to +75
l
DP-28S FP-28DA FP-30D -20 to +75
+75
-20 to +75
4
HD404344R Series/HD404394 Series
List of Functions (cont)
Mask ROM item Operating voltage (V) Instruction cycle time (typ.) HCD40C4344R 2.7 to 5.5 2 s (Rf = 20 k) ROM (Words) RAM (Digits) I/O High-current I/O pins (Sink 15 mA max) Timer functions Free running timer Reload timer 2 2 1 1 2 2 4,096 256 22 10 ZTATTM HD4074344 2.7 to 5.5 1 s (fosc = 4.0 MHz) 4,096 PROM 256 22 10
Event counter 1 Watchdog timer Serial interface A/D converter Interrupt External Internal Low-power modes Stop mode Standby mode Oscillator Ceramic oscillation RC oscillation Package 1 8bit x 4ch 1 4 2 1
1 8bit x 4ch 1 4 2
l l
--
l l l
-- DP-28S FP-28DA FP-30D
l
Chip
Guaranteed operation temperature (C)
+75
-20 to +75
5
HD404344R Series/HD404394 Series
List of Functions (cont)
Mask ROM item Operating voltage (V) Instruction cycle time (typ.) HD404391 2.7 to 5.5 1 s (fosc = 4.0 MHz) ROM (Words) RAM (Digits) I/O intermediatevoltage NMOS open drain I/O NMOS open drain I/O (15 mA High current driver) Timer functions Free running timer Reload timer 2 2 1 1 2 1 1 2 1 1 2 2 2 2 5 5 5 5 1,024 256 21 3 HD404392 2.7 to 5.5 1 s (fosc = 4.0 MHz) 2.048 256 21 3 HD404394 2.7 to 5.5 1 s (fosc = 4.0 MHz) 4,096 256 21 3 ZTATTM HD4074394 2.7 to 5.5 1 s (fosc = 4.0 MHz) 4,096 PROM 256 21 3
Event counter 1 Watchdog timer Serial interface A/D converter Interrupt External Internal Low-power modes Stop mode Standby mode Oscillator Ceramic oscillation Package DP-28S FP-28DA FP-30D Guaranteed operation temperature (C) -20 to +75 1 8bit x 3ch 1 4 2 1
1 8bit x 3ch 1 4 2
1 8bit x 3ch 1 4 2
2 8bit x 3ch 1 4 2
l l l
l l l
DP-28S FP-28DA FP-30D -20 to +75
l l l
DP-28S FP-28DA FP-30D -20 to +75
l l l
DP-28S FP-28DA FP-30D -20 to +75
6
HD404344R Series/HD404394 Series
Pin Arrangement
HD404344R Series, HD4074344
R10 R11 R12 R13 R20 R21 R22 R23 OSC1 OSC2 GND R30/AN0 R31/AN1 R32/AN2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
DP-28S FP-28DA
22 21 20 19 18 17 16 15
D5 D4/STOPC D3 D2 D1 D0/INT0/EVNB R03/TOC R02/SO R01/SI R00/SCK RESET TEST/VPP VCC R33/AN3
R10 R11 R12 R13 R20 R21 R22 R23 OSC1 OSC2 GND NC R30/AN0 R31/AN1 R32/AN2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25
FP-30D
24 23 22 21 20 19 18 17 16
D5 D4/STOPC D3 D2 D1 D0/INT0/EVNB R03/TOC R02/SO R01/SI R00/SCK RESET TEST/VPP VCC NC R33/AN3
Top view
HD404394 Series
R10 R11 R12 R13 R20 R21 R22 R23 OSC1 OSC2 GND Vref R31/AN1 R32/AN2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
DP-28S FP-28DA
22 21 20 19 18 17 16 15
D5 D4/STOPC D3 D2 D1 D0/INT0/EVNB R03/TOC R02/SO R01/SI R00/SCK RESET TEST/VPP VCC R33/AN3
R10 R11 R12 R13 R20 R21 R22 R23 OSC1 OSC2 GND NC Vref R3 1/AN1 R3 2/AN2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25
FP-30D
24 23 22 21 20 19 18 17 16
D5 D4/STOPC D3 D2 D1 D0/INT0/EVNB R03/TOC R02/SO R01/SI R00/SCK RESET TEST/VPP VCC NC R33/AN3
Top view
7
HD404344R Series/HD404394 Series
Pad Arrangement
HCD404344R, HCD40C4344R
30 29 28 27 26 25
1 2 3
24 23 22
4 5 6 20 19 18 17 21
7 8 Type Code 9
10
11
12
13
14
15
16
Type Code: HD404344R (HCD404344R) HD40C4344R (HCD40C4344R)
8
HD404344R Series/HD404394 Series
Bonding Pad Coordinates
HCD404344R, HCD40C4344R
Chip center (X=0, Y=0) Type Code
Chip size (X x Y): 3.23 x 3.65 (mm) Coordinates: Pad center Home point position: Chip center Pad size (X x Y): 90 x 90 (m) Chip thickness: 400 (m)
Pad No.
Coordinates Pad Name 1 R13 2 R20 3 R21 4 R22 5 R23 6 OSC1 7 OSC2 8 GND 9 GND X (m) -1425 -1425 -1425 -1425 -1425 -1425 -1425 -1425 -1425 -1257 -891 -526 -162 420 804 Y (m) 1370 1050 732 455 165 -115 -732 -997 -1244 -1627 -1627 -1627 -1627 -1627 -1627
Pad No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Coordinates Pad Name TEST RESET R00 R01 R02 R03 D0 D1 D2 D3 D4 D5 R10 R11 R12 X (m) 1360 1418 1418 1418 1418 1418 1418 1418 1418 1075 693 309 -329 -732 -1135 Y (m) -1627 -1456 -1072 -690 -306 312 694 1098 1501 1627 1627 1627 1627 1627 1627
10 11 12 13 14 15
R30 R31 R32 R33 VCC VCC
9
HD404344R Series/HD404394 Series
Pin Description
HD404344R Series, HD4074344
Pin Number Item Power supply Symbol VCC GND Test Reset Oscillator TEST RESET OSC 1 DP-28S/ FP-28DA FP-30D Chip 16 11 17 18 9 18 11 19 20 9 14, 15 8, 9 16 17 6 I I I I/O Function Applies power voltage Connects to ground Cannot be used in user applications. Connect this pin to GND. Resets the MCU Input/output pins for the internal oscillator. Connect these pins to the ceramic oscillator, or OSC1 to an external oscillator circuit.
OSC 2 Port D0-D 5
10 23-28
10 25-30
7 22-27
O I/O Input/output pins addressed individually by bits; pins D 1 and D 2 can sink 15 mA max. Four-bit input/output pins. Pins R1 0-R2 3 can sink 15 mA max.
R0 0-R0 3, R1 0-R1 3, R2 0-R2 3, R3 0-R3 3 Interrupt Stop clear Serial interface INT0 STOPC SCK SI SO Timer TOC EVNB A/D converter AN 0-AN 3
1-8, 12-15 19-22
1-8, 13-16, 21-24
18-21, 28-30, 1-5, 10-13
I/O
23 27 19 20 21 22 23 12-15
25 29 21 22 23 24 25 13-16
22 26 18 19 20 21 22 10-13
I I I/O I O O I I
Input pin for external interrupts Input pin for transition from stop mode to active mode Serial interface clock input/output pin Serial interface receive data input pin Serial interface transmit data output pin Timer output pin Event count input pin Analog input pins for the A/D converter
10
HD404344R Series/HD404394 Series
HD404394 Series
Pin Number Item Power supply Symbol VCC GND Test Reset Oscillator TEST RESET OSC 1 DP-28S/ FP-28DA FP-30D 16 11 17 18 9 18 11 19 20 9 I I I I/O Function Applies power voltage Connects to ground Cannot be used in user applications. Connect this pin to GND. Resets the MCU Input/output pin for the internal oscillator. Connect these pins to the ceramic oscillator, or OSC 1 to an external oscillator circuit OSC 2 Port D0-D 5 10 23-28 10 25-30 1-8, 14-16, 21-24 O I/O I/O Input/output pins addressed individually by bits; pins D 1 and D 2 can sink 15 mA max. Four-bit input/output pins. Pins R1 0-R1 2 are NMOS intermediate-voltage open drain pins. Pins R1 3-R2 3 are NMOS standard-voltage open drain pins which can sink 15 mA max. Input pin for external interrupts Input pin for transition from stop mode to active mode Serial interface clock input/output pin Serial interface receive data input pin Serial interface transmit data output pin Timer output pin Event count input pin Power supply for the internal ladder resistor in the A/D converter I Analog input pins for the A/D converter
R0 0-R0 3, 1-8, R1 0-R1 3, 13-15 R2 0-R2 3, 19-22 R3 1-R3 3 Interrupt Stop clear Serial interface INT0 STOPC SCK SI SO Timer TOC EVNB A/D converter Vref 23 27 19 20 21 22 23 12
25 29 21 22 23 24 25 13 14-16
I I I/O I O O I
AN 1-AN 3 13-15
11
HD404344R Series/HD404394 Series
HD404344R Series, HD4074344 Block Diagram
STOPC RESET OSC1 OSC2 TEST GND
INT0
Interrupt control
System control RAM (256 x 4 bits)
VCC
D0 D1 D port D2 D3 D4 D5
EVNB
Timer B
W (2 bits) X (4 bits)
R00 R0 port TOC Timer C SPX (4 bits) Y (4 bits) SI Internal address bus SO SCK Serial interface Internal data bus R10 R1 port SPY (4 bits) Internal data bus R11 R12 R13 R01 R02 R03
AN0 AN1 AN2 AN3 A/D converter
R20 R2 port ALU R21 R22 R23 ST (1 bit) CA (1 bit) R3 port
R30 R31 R32 R33
A (4 bits) B (4 bits) SP (10 bits) Data bus Instruction decoder PC (14 bits)
Large-current pin
ROM (1,024 x 10 bits) (2,048 x 10 bits) (4,096 x 10 bits)
Bidirectional signal line
12
HD404344R Series/HD404394 Series
HD404394 Series Block Diagram
STOPC RESET OSC1 OSC2 TEST GND
INT0
Interrupt control
System control RAM (256 x 4 bits)
VCC
D0 D1 D port D2 D3 D4 D5
EVNB
Timer B
W (2 bits) X (4 bits)
R00 R0 port TOC Timer C SPX (4 bits) Y (4 bits) Internal address bus SI SO SCK Internal data bus Serial interface R01 R02 R03
R10 R1 port SPY (4 bits) Internal data bus R11 R12 R13
AN1 AN2 AN3 Vref A/D converter
R20 R2 port ALU R21 R22 R23
Data bus
ST (1 bit)
CA (1 bit) R3 port R31 R32 R33
Large-current pin
A (4 bits) B (4 bits)
Intermediatevoltage NMOS open drain pins
SP (10 bits) Instruction decoder PC (14 bits)
Standardvoltage NMOS open drain pins
ROM (1,024 x 10 bits) (2,048 x 10 bits) (4,096 x 10 bits)
Bidirectional signal line
13
HD404344R Series/HD404394 Series
Memory Map
ROM Memory Map The ROM memory map for the MCU is shown in figure 1 and explained as follows.
0 Vector address 15 16 Zero-page subroutine (64 words) 63 64 $003F $0040 $000F $0010
$0000
$0000 JMPL instruction (jump to RESET, STOPC routine) $0001 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 JMPL instruction (jump to timer B routine) JMPL instruction (jump to timer C routine) JMPL instruction (jump to A/D converter routine) JMPL instruction (jump to serial routine) Not used JMPL instruction (jump to INT0 routine) $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
1023 1024
HD404341R, HD40C4341R, HD404391 program/pattern (1,024 words) HD404342R, HD40C4342R, HD404392 program/pattern (2,048 words)
HD404344R, HD40C4344R, HCD404344R, HCD40C4344R,HD404394, HD4074344, HD4074394
$03FF $0400
2047 2048
$07FF $0800
4095 4096
program/pattern (4,096 words)
$0FFF $1000
Not used
16383
$3FFF
Figure 1 ROM Memory Map
14
HD404344R Series/HD404394 Series
Vector Address Area ($0000 to $000F): When an MCU reset or an interrupt process is executed, the program will begin executing from a vector address. The JMPL instructions which branch to the reset routine and interrupt routine should be programmed at these top addresses. Zero-Page Subroutine Area ($0000-$003F): This area is reserved for subroutines. The program branches to a subroutine in this area in response to a CAL instruction. Pattern Area: HD404341R, HD40C4341R, HD404391--$0000 to $03FF HD404342R, HD40C4342R, HD404392--$0000 to $07FF HD404344R, HD40C4344R, HCD404344R, HCD40C4344R, HD404394, HD4074344, HD4074394-- $0000 to $0FFF This area contains ROM data which can be referenced with the P instruction. Program Area: HD404341R, HD40C4341R, HD404391--$0000 to $03FF HD404342R, HD40C4342R, HD404392--$0000 to $07FF HD404344R, HD40C4344R, HCD404344R, HCD40C4344R, HD404394, HD4074344, HD4074394-- $0000 to $0FFF
15
HD404344R Series/HD404394 Series
RAM Memory Map
The MCU RAM contains 256 digits x 4 bits which is used for the memory registers, and the data and stack areas. The interrupt control bits area, special register area, and the register flag area are mapped into the RAM memory. The RAM memory area is shown in figure 2 and explained as follows.
$000 RAM-mapped registers $040 $050 Data (176 digits) $100 Memory registers (MR) $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F
Interrupt control bits area Port mode register A (PMRA) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) Not used Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C (TMC) Timer C (TRCL/TWCL) (TRCU/TWCU) W W R/W R/W W R/W R/W W W R/W R/W
*
Not used
Not used $3C0 Stack (64 digits) $3FF $016 $017 $018 $019 $01A A/D channel register A/D data register lower A/D data register upper A/D mode register 1 A/D mode register 2 (ACR) (ADRL) (ADRU) (AMR1) (AMR2) W R R W W
Not used
$020 Register flag area $023 $024 Port mode register B (PMRB) $025 Port mode register C (PMRC) $026 Timer mode register B2 (TMB2) Not used Note: * Two registers are mapped on the same area ($00A, $00B, $00E, $00F). $02C $02D $030 $031 $032 $033 Port D0-D3 DCR Port D4 , D5 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Not used $03F
(DCD0) (DCD1)
W W W
W W W W W W
R: Read only W: Write only R/W: Read/write
(DCR0) (DCR1) (DCR2) (DCR3)
$00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W
Figure 2 RAM Memory Map
16
HD404344R Series/HD404394 Series
RAM Map Register Area ($000 to $03F): * Interrupt control bits area: $000 to $003 This area is made up of bits used for interrupt control as shown in figure 3. Each bit can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). Some bits however, have limitations along with certain instructions as shown in figure 4. * Special register area: $004 to $01F, $024 to $03F This area is made up of mode registers and data registers, such as for external interrupt, serial interface, timers, A/D converter, and data control for the I/O ports. Its configurations are shown in figures 2 and 5. These registers are categorized as write-only, read-only, and write/read. They can not be accessed by RAM bit manipulation instructions. * Register flag area: $020 to $023 This area is used for the WDON flag and other interrupt control flags. Its configuration is shown in figure 3. Each bit can be accessed only by the SEM/SEMD, REM/REMD, and TM/TMD instructions. Some bits however, have limitations along with certain instructions as shown in figure 4. Data Area ($040 to $0FF): Sixteen of the 176 digits in this area, from $040 to $04F, are memory registers. These registers can be accessed by the LAMR and XMRA instructions. Its configuration is shown in figure 6. Stack Area ($3C0 to $3FF): This area is used to hold the program counter (PC), the status flag (ST), and the carry flag (CA) for subroutine calls (CAL and CALL instructions) and interrupts. Since four digits are used for each level, this area can be used for stacking up to 16 subroutines. The stacking order of saved data and the storing of bits are shown in figure 6. The program counter is recovered by the RTN and RTNI instructions. The status and carry flags are recovered only by the RTNI instruction. Any area not used in the stack area is available for data storage.
17
HD404344R Series/HD404394 Series
RAM Address
$0000
Bit 3 IM0 (IM of INT0)
Bit 2
Bit 1
Bit 0
IE (Interrupt enable flag)
IF0 (IF of INT0)
RSP (Reset SP bit)
$0001
$0002
IMTC (IM of timer C) IMS (IM of serial)
IFTC (IF of timer C)
IMTB (IM of timer B) IMAD (IM of A/D)
IFTB (IF of timer B)
IFAD (IF of A/D)
$0003
IFS (IF of serial)
Interrupt control bits area
Bit 3
$020
Bit 2
ADSF (A/D start flag)
Bit 1
WDON (Watchdog on flag)
Bit 0
: Not used
$021
IF: Interrupt request flag IE: Interrupt mask IM: Interrupt enable flag SP: Stack pointer
RAME (RAM enable flag)
IAOF (IAD off flag)
$022
$023
Register flag area
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
SEM/SEMD IE IM IAOF IF RAME RSP WDON ADSF Not used Can be used Not processed Not processed Can be used Can be used Not processed
REM/REMD Can be used Can be used Can be used Not processed Inhibited to access Not processed
TM/TMD Can be used Can be used Inhibited to access Inhibited to access Can be used Inhibited to access
* The WDON bit can be reset by an MCU reset or by stop mode release with STOPC. * Do not use REM/REMD for the ADSF bit during A/D conversion. * If the TM or TMD instruction is excuted for the inhibited or non-existing bits, the value in ST becomes invaild.
Figure 4 Limitations for RAM Bit Manipulation Instructions
18
HD404344R Series/HD404394 Series
Register name $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F : Not used Note: * Applies to the HD404344R series and HD4074344. Does not apply to the HD404394 series. Bit 3 IM0 IMTC IMS R00/SCK Bit 2 IF0 IFTC IFS R03/TOC Bit 1 RSP Bit 0 IE IFTB IFAD R02/SO
PMRA SMR SRL SRU TMB1 TRBL/TWBL TRBU/TWBU MIS TMC TRCL/TWCL TRCU/TWCU
IMTB IMAD R01/SI Serial data transfer speed Serial data register (lower) Serial data register (upper)
Reload control
Pull-up control Reload control
Timer B clock source Timer B register (lower) Timer B register (upper) SO PMOS control Timer C clock source Timer C register (lower) Timer C register (upper)
ACR ADRL ADRU AMR1 AMR2
R33/AN3
A/D channel selection A/D data register (lower) A/D data register (upper) R32/AN2 R31/AN1
R30/AN0* A/D conversion speed
RAME
ADSF IAOF
WDON
PMRB PMRC TMB2
D4/STOPC
D0/INT0/EVNB Transmit clock SO idle level EVNB edge detection
DCD0 DCD1
D3 DCR
D2 DCR
D1 DCR D5 DCR
D0 DCR D4 DCR
DCR0 DCR1 DCR2 DCR3
R03 DCR R13 DCR R23 DCR R33 DCR
R02 DCR R12 DCR R22 DCR R32 DCR
R01 DCR R11 DCR R21 DCR R31 DCR
R00 DCR R10 DCR R20 DCR R30 DCR*
Figure 5 Special Register Area
19
HD404344R Series/HD404394 Series
Memory registers $040 MR(0) $041 MR(1) $042 MR(2) $043 MR(3) $044 MR(4) $045 MR(5) $046 MR(6) $047 MR(7) $048 MR(8) $049 MR(9) $04A MR(10) $04B MR(11) $04C MR(12) $04D MR(13) $04E MR(14) $04F MR(15) $3C0 Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 $3FF Level 1
Bit 3 $3FC $3FD $3FE $3FF ST PC 10 CA PC 3
Bit 2 PC13 PC9 PC6 PC2
Bit 1 PC 12 PC 8 PC 5 PC 1
Bit 0 PC11 PC7 PC4 PC0
PC13 -PC0 : Program counter ST: Status flag CA: Carry flag Note: Since HD404344R series, HD4074344 and HD404394 series have a 4-kword ROM, PC12 and PC13 are ignored.
Figure 6 Configuration of Memory Registers, Stack Area, and Stack Position
20
HD404344R Series/HD404394 Series
Functional Description
Registers and Flags The CPU has nine registers and two flags. Their configurations are shown in figure 7 and explained as follows.
3 Accumulator Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W (B) 1 W register Initial value: Undefined, R/W 3 X register Initial value: Undefined, R/W 3 Y register Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W 3 SPY register Initial value: Undefined, R/W (SPY) (SPX) (Y) (X) (A)
0
0
0 (W) 0
0
0
0
0 Carry Initial value: Undefined, R/W (CA) 0 Status Program counter Initial value: 0, no R/W Stack pointer Initial value: $3FF, no R/W Initial value: 1, no R/W 13 (PC) 9 1 1 1 1 5 (SP) 0 (ST) 0
Figure 7 Registers and Flags
21
HD404344R Series/HD404394 Series
Accumulator (A), B Register (B): The accumulator and B register are 4-bit registers used for storing ALU operation results and data that is transferred between memory and I/O ports or between other registers. W Register (W), X Register (X), Y Register (Y): The W register is a 2-bit register and the X and Y registers are 4-bit registers. These are used for indirect addressing to RAM. The Y register is also used for addressing the D port. SPX Register (SPX), SPY Register (SPY): The SPX and SPY registers are 4-bit registers that supplement the X and Y registers, respectively. Carry Flag (CA): The carry flag latches the ALU overflow during an arithmetic instruction execution. It is controlled by the SEC, REC, ROTL, and ROTR instructions. The carry flag is stored during interrupt processing, then recovered from the stack by a RTNI instruction. (It is not affected by the RTN instruction.) Status Flag (ST): The status flag latches the overflow of ALU arithmetic instructions and compara tive instructions, and also the results of ALU non-zero and bit test instructions. It is then used for branch conditions of the BR, BRL, CAL, and CALL instructions. The status flag remains unchanged until the next arithmetic instruction, comparative instruction, or bit test is executed. After a BR, BRL, CAL, or CALL instruction is executed, the status flag will be set to 1 regardless if the instruction is executed or skipped. The contents of the status flag is stored on the stack during interrupt processing, then recovered from the stack by a RTNI instruction. Program Counter (PC): This 14-bit binary counter maintains ROM address information. Stack Pointer (SP): The stack pointer is a 10-bit register which contains the address of the next stack space to be used. It is initialized as $3FF by an MCU reset. When data is stored onto the stack, the SP is decremented by 4, and when data is pulled from the stack, it is incremented by 4. The top four bits of the stack pointer are fixed at 1111, so it can be used for a maximum of 16 levels. There are two ways of initializing the stack pointer to $3FF. One is by MCU reset and the other is by resetting the RSP bit with a REM or a REMD instruction. Reset An MCU reset is executed by setting RESET low. The RESET input must be more than t RC so as to keep the oscillator steady during power on or when stop mode is cancelled. For other cases, the MCU can be reset by a RESET input for a minimum of two instruction cycle times. Initialized values by MCU reset are listed in table 1.
Certain bits in the interrupt control bits area and the register flag area can be set or reset by the SEM/SEMD or REM/REMD instructions. Also these can be tested by the TM/TMD instruction. The following specifies the limitations for each bit.
22
HD404344R Series/HD404394 Series
Table 1
Item Program counter
Initial Values After MCU Reset
Abbr. (PC) Initial Value $0000 Contents Indicates program execution point from start address of ROM area Enables conditional branching Stack level 0 Inhibits all interrupts Indicates there is no interrupt request Prevents (masks) interrupt requests Enables output at level 1 Turns output buffer off (to high impedance)
Status flag Stack pointer Interrupt flags/mask Interrupt enable flag Interrupt request flag Interrupt mask I/O Port data register Data control register
(ST) (SP) (IE) (IF) (IM) (PDR) (DCD0, DCD1)
1 $3FF 0 0 1 All bits 1 All bits 0
(DCR0,- DCR3) All bits 0 Port mode register A Port mode register B Port mode register C (PMRA) (PMRB) (PMRC) - 000 0--0 ---0 0000 Refer to description of port mode register A Refer to description of port mode register B Refer to description of port mode register C Refer to description of timer mode register B1 Refer to description of timer mode register B2 Refer to description of timer mode register C Refer to description of serial mode register -- -- -- -- -- --
Timer/ Timer mode register B1 (TMB1) counters, serial interface Timer mode register B2 (TMB2) Timer mode register C Serial mode register Prescaler S Timer counter B Timer counter C Timer write register B Timer write register C Octal counter (TMC) (SMR) (PSS) (TCB) (TCC)
- - 00 0000 0000 $000 $00 $00
(TWBU, TWBL) $X0 (TWCU, TWCL) $X0 000
23
HD404344R Series/HD404394 Series
Table 1
Item A/D A/D mode register 1 A/D mode register 2 Bit register
Initial Values After MCU Reset (cont)
Abbr. (AMR1) (AMR2) Initial Value 0000 ---0 0 0 0 00 - Contents Refer to description of A/D mode register Refer to description of A/D mode register Refer to description of timer C Refer to description of A/D converter Refer to description of A/D converter Refer to description of I/O, and serial interface
Watchdog timer on flag (WDON) A/D start flag I AD off flag (ADSF) (IAOF) (MIS)
Others
Miscellaneous register
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist.
Table 1
Initial Values After MCU Reset (cont)
After Stop Mode Release by STOPC Input After Stop Mode Release by RESET Input After Other Types of MCU Reset Program needs to initialize these registers.
Carry
(CA)
Program needs to initialize these registers.
Accumulator B register W register X/SPX register Y/SPY register Serial data register A/D data register RAM RAM enable flag Port mode register B bit 3
(A) (B) (W) (X/SPX) (Y/SPY) (SRU, SRL) (ADRU, ADRL) Data before entering stop mode are kept. (RAME) (PMRB3) 1 Data before entering stop mode are kept. 0 0 0 0
24
HD404344R Series/HD404394 Series
Interrupts There are five kinds of interrupts: external INT 0, timer B, timer C, serial interface, and A/D converter. An interrupt request flag or an interrupt mask and vector address are used for each type of interrupt. They are used for storing interrupt requests and interrupt controls. An interrupt enable flag is also used for total interrupt control. Interrupt Control Bits and Interrupt Processing: The interrupt control bits are mapped from $000 to $003 of RAM and can be accessed by RAM bit manipulation instructions. However, the interrupt request flag (IF) cannot be set by software. An MCU reset initializes the interrupt enable flag (IE) and the interrupt request flag (IF) to 0, and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 8. The interrupt priority order and vector addresses are listed in a table in the figure, along with the conditions for executing the interrupt processing of the five types of interrupt requests (table 2). An interrupt request occurs when the interrupt request flag is set to 1 and the interrupt mask to 0. If the interrupt enable flag is 1, interrupt processing has occurred. The vector address which corresponds to the interrupt source is generated from the priority PLA. The interrupt processing sequence is shown in figure 9 and the interrupt processing flowchart is shown in figure 10. After receiving an interrupt, the previous instruction is completed in the first cycle. The interrupt enable flag (IE) is reset after two cycles. The contents of the carry flag, status flag, and program counter are stored onto the stack at the second and third cycles. Instruction execution is restarted by jumping to the vector address during the third cycle. The JMPL instructions, which branch to the start addresses of the interrupt routines, should be programmed at each vector address area. The interrupt request which initiated the interrupt processing should be reset by software instructions in the interrupt routine.
25
HD404344R Series/HD404394 Series
$000,0 IE * (RESET, STOPC ) $000,2 INT0 interrupt IF0 $000,3 IM0 $002,0 Timer B interrupt IFTB $002,1 IMTB $002,2 Timer C interrupt IFTC $002,3 IMTC $003,0 A/D interrupt IFAD $003,1 IMAD $003,2 Serial interrupt IFS $003,3 IMS Priority Controller Priority Order Vector Address $0000 1 $0002 2 $0008 3 $000A 4 $000C 5 $000E Interrupt request
Note: * STOPC interrupt request is enabled only when the MCU is in stop mode.
Figure 8 Interrupt Control Circuit, Vector Addresses, and Interrupt Priorities
26
HD404344R Series/HD404394 Series
Table 2 Interrupt Processing and Activation Conditions
Interrupt Source Interrupt Control Bit IE IF0 * IM0 IFTB * IMTB IFTC * IMTC IFAD * IMAD IFS * IMS INT0 1 1 * * * * Timer B 1 0 1 * * * Timer C 1 0 0 1 * * A/D 1 0 0 0 1 * Serial 1 0 0 0 0 1
Note: * Can be either 0 or 1. Their values have no effect on operation.
Instruction cycles 1 2 3 4 5 6
Instruction execution*
Interrupt acceptance
Stacking; IE reset
Stacking; Vector address generation
Execution of JMPL instruction at vector address
Execution of instruction at start address of interrupt routine
Note:
* The stack is accessed and the interrupt enable flag is reset after the instruction is executed, even if it is a two-cycle instruction.
Figure 9 Interrupt Processing Sequence
27
HD404344R Series/HD404394 Series
Power on
RESET = 0? Yes
No
Interrupt request? No
Yes
No
IE = 1? Yes Accept interrupt
Execute instruction Reset MCU
PC (PC) + 1
IE 0 Stack (PC) Stack (CA) Stack (ST)
PC $0002
Yes
INT0 interrupt? No
PC $0008
Yes
Timer B interrupt? No
PC $000A
Yes
Timer C interrupt? No
PC $000C
Yes
A/D interrupt? No
PC $000E (serial interrupt)
Figure 10 Interrupt Processing Flowchart
28
HD404344R Series/HD404394 Series
Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag executes interrupt enable/disable for all interrupt requests as listed in table 3. It is reset by interrupt processing and set by the RTNI instruction. Table 3
IE 0 1
Interrupt Enable Flag (IE: $000, Bit 0)
Interrupt Enabled/Disabled Disabled Enabled
External Interrupt (INT0): INT0 input should be selected by using port mode register B (PMRB: $024), so that the external interrupt request flag (IF0) is set at the falling edge of the INT0 input. External Interrupt Request Flag (IF0: $000, Bit 2): The external interrupt request flag is set by the INT0 input edge, as listed in table 4. Table 4
IF0 0 1
External Interrupt Request Flag (IF0: $000, Bit 2)
Interrupt Request No Yes
External Interrupt Mask (IM0: $000, Bit 3): IM0 is a bit which masks the interrupt request caused by an external interrupt request flag, as listed in table 5. Table 5
IM0 0 1
External Interrupt Mask (IM0: $000, Bit 3)
Interrupt Request Enabled Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the overflow output of timer B, as listed in table 6. Table 6
IFTB 0 1
Timer B Interrupt Request Flag (IFTB: $002, Bit 0)
Interrupt Request No Yes
29
HD404344R Series/HD404394 Series
Timer B Interrupt Mask (IMTB: $002, Bit 1): IMTB is a bit which masks the interrupt request caused by the timer B interrupt request flag, as listed in table 7. Table 7
IMTB 0 1
Timer B Interrupt Mask (IMTB: $002, Bit 1)
Interrupt Request Enabled Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): The timer C interrupt request flag is set by the overflow output of timer C, as listed in table 8. Table 8
IFTC 0 1
Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
Interrupt Request No Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): IMTC is a bit which masks the interrupt request caused by the timer C interrupt request flag, as listed in table 9. Table 9
IMTC 0 1
Timer C Interrupt Mask (IMTC: $002, Bit 3)
Interrupt Request Enabled Disabled (masked)
Serial Interrupt Request Flag (IFS: $003, Bit 2): A serial interrupt request flag is set when the serial data transfer is completed or when the data transfer is suspended, as listed in table 10. Table 10
IFS 0 1
Serial Interrupt Request Flag (IFS: $003 Bit 2)
Interrupt Request No Yes
30
HD404344R Series/HD404394 Series
Serial Interrupt Mask (IMS1: $003, Bit 3): IMS1 is a bit which masks the interrupt request caused by the serial interrupt request flag, as listed in table 11. Table 11
IMS 0 1
Serial Interrupt Mask (IMS: $003, Bit 3)
Interrupt Request Enabled Disabled (masked)
A/D Interrupt Request Flag (IFAD: $003, Bit 0): The A/D interrupt request flag is set after the A/D conversion is completed, as listed in table 12. Table 12
IFAD 0 1
A/D Interrupt Request Flag (IFAD: $003, Bit 0)
Interrupt Request No Yes
A/D Interrupt Mask (IMAD: $003, Bit 1): IMAD is a bit which masks the interrupt request caused by the A/D interrupt request flag, as listed in table 13. Table 13
IMAD 0 1
A/D Interrupt Mask (IMAD: $003, Bit 1)
Interrupt Request Enabled Disabled (masked)
31
HD404344R Series/HD404394 Series
Operating Modes
The MCU has three operating modes as shown in table 14. The transitions between the operating modes are shown in figure 11. Table 14
Function System oscillator CPU RAM Timers B, C Serial A/D I/O
Operations in Each Operating Mode
Active Mode OP OP OP OP OP OP OP Standby Mode OP Retained Retained OP OP OP Retained* Stop Mode Stopped Reset Retained Reset Reset Reset Reset
Notes: OP implies in operation. * Since input/output circuits are in operation, the current will flow in/out depending on the pin status in standby mode. Note that this current is in addition to the standby mode dissipation current.
SBY instruction Interrupt request Standby mode
Active mode
STOP instruction
RESET = 0
RESET = 1
Stop mode
RESET = 0 MCU reset
RESET = 0
Figure 11 MCU Status Transition
32
HD404344R Series/HD404394 Series
Active Mode: All functions operate in active mode. In active mode, the MCU is controlled by the oscillating circuit of OSC1 and OSC2. Standby Mode: The MCU switches to standby mode when an SBY instruction is executed. In standby mode, the oscillator continues operating, but the clocks related to instruction execution stops running. This causes the CPU to stop operating. However, the contents of RAM are retained. Also, the D and R ports, which are set as output, maintain their status before entering standby mode. The peripheral functions, such as interrupt, timers, serial interface, and A/D converter, continue operating. Power dissipation in standby mode is less than in active mode because of the CPU not operating. The MCU enters standby mode when the SBY instruction is executed in active mode. To terminate standby mode, provide a RESET input or an interrupt request. If a reset input is given, the MCU will be reset. If an interrupt request is given, the MCU will change to active mode and the next instruction will be executed. After the instruction execution, if the interrupt enable flag is 1, the interrupt operation is executed. If the interrupt enable flag is 0, normal instruction execution continues and the interrupt request is left pending. The standby mode flowchart is shown in figure 13. Stop Mode: The MCU enters stop mode when a STOP instruction is received. In stop mode, all MCU functions stop, except for maintaining RAM data. Power dissipation in this mode is therefore the lowest of all operating modes. In stop mode, the OSC1 and OSC2 oscillator is stopped. To terminate stop mode provide either a RESET or STOPC input as shown in figure 12. When terminating stop mode, it is important to ensure a proper oscillation stabilization period of at least tRC for the RESET or STOPC input. (Refer to the AC characteristics tables.) After clearing stop mode, the RAM maintains its data kept before entering stop mode. However, the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and the serial data register are not maintained. Clearing Stop Mode Using STOPC: The MCU is transition from stop mode to active mode by either a RESET or STOPC input. The MCU starts instruction execution from the start of the program at address 0. Then the RAM enable flag (RAME: $021, 3) is set accordingly, RAME = 0 for RESET input and RAME = 1 for STOPC input. A RESET input is effective when the MCU is in any mode. A STOPC input however, is effective only in stop mode and is ignored in other modes. So, when clearing stop mode with a STOPC input the program needs to identify the RAME status. (For example, when the RAM contents before entering stop mode is used after transition to active mode.) A TEST instruction for the RAM enable flag (RAME) should be executed at the beginning of the program.
33
HD404344R Series/HD404394 Series
Table 15
Mode Active mode
Operating Modes and Transition Conditions
Conditions to Enter Mode * * * * * RESET release Interrupt request STOPC release in stop mode SBY instruction * * * * RESET input Interrupt request RESET input STOPC input in stop mode Conditions to Exit Mode * * RESET input STOP/SBY instruction
Standby mode
Stop mode
STOP instruction
Stop mode Oscillator Internal clock
RESET or STOPC STOP instruction execution
tres tres tRC (stabilization period)
Figure 12 Timing of Stop Mode Cancellation
34
HD404344R Series/HD404394 Series
Stop Standby
Oscillator: Stop Peripheral clocks: Stop All other clocks: Stop
Oscillator: Active Peripheral clocks: Active All other clocks: Stop
No
RESET = 0? Yes
RESET = 0? Yes
No
No STOPC = 0?
IF0 * IM0 = 1? Yes
No
Yes
IFTB * IMTB = 1? Yes
No
IFTC * IMTC = 1? Yes
No
IFAD * IMAD = 1? Yes
No
RAME = 1
RAME = 0 IFS * IMS = 1? Yes No
Restart processor clocks
Execute next instruction
Restart processor clocks
No
IF = 1, IM = 0, and IE = 1? Yes
Reset MCU
Execute next instruction
Interrupt accept
Figure 13 MCU Process Flowchart
35
HD404344R Series/HD404394 Series
MCU Operation Sequence: The MCU operates according to the flowcharts shown in figures 14 to 16. Since RESET is asynchronous input, the MCU will be reset in any mode that the MCU is operating in. The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked.
Power on
RESET = 0? Yes
No
RAME = 0
MCU operation cycle
Reset MCU
Figure 14 MCU Operation Sequence (Power On)
36
HD404344R Series/HD404394 Series
MCU operation cycle
IF = 1?
Yes
No
No
IM = 0 and IE = 1?
Yes Instruction execution
Yes
SBY/STOP instruction?
IE 0 Stack (PC), (CA), (ST)
No
Low-power mode operation cycle
PC Next location
PC Vector address
IF: IM: IE: PC: CA: ST:
Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag
Figure 15 MCU Operation Sequence (MCU Operation Cycle)
37
HD404344R Series/HD404394 Series
Low-power mode operation cycle
IF = 1 and IM = 0?
No
Yes
Standby mode (SBY)
Stop mode
* No
IF = 1 and IM = 0?
No
STOPC = 0?
Yes Hardware NOP execution Hardware NOP execution
Yes
RAME = 1
PC Next Iocation
PC Next Iocation
Reset MCU
Instruction execution
MCU operation cycle
Note: * For IF and IM operation, refer to figure 13.
Figure 16 MCU Operation Sequence (Low Power Mode Operation)
38
HD404344R Series/HD404394 Series
Oscillator Circuit
Figure 17 shows a block diagram of the clock generation circuit. Ceramic oscillator can be connected to OSC 1 and OSC2 as listed in table 16. An external clock can also be connected. In addition, the system oscillator of the HD404344R Series is capable of CR oscillation.
OSC2 OSC1
1/4 System fOSC division oscillator circuit
fcyc tcyc
Timing generator circuit
System clock generation
oCPU
CPU with ROM, RAM, registers, flags, and I/O
oPER
Peripheral function interrupt
Figure 17 Clock Generation Circuit
R23 OSC1 OSC2 GND : GND
Figure 18 Typical Layout of Ceramic Oscillator
39
HD404344R Series/HD404394 Series
Table 16 Oscillator Circuit Examples
Circuit Configuration External clock operation
External oscillator OSC 1
Circuit Constants
Open
OSC 2
Ceramic oscillator (OSC1, OSC 2)
Ceramic oscillator : CSA4.00MG (Murata)
C1 OSC1 Ceramic oscillator Rf OSC2 C2 GND
Rf = 1 M 20% C1 = C2 = 30 pF 20% Ceramic oscillator: KBR-4.0MSA (Kyocera) Rf = 1 M 20% C1 = C2 = 33 pF 20% Rf = 20 k 1%
CR oscillation (OSC1, OSC 2) HD404344R series
OSC1 Rf OSC2
Notes: 1. Since the circuit constants change depending on the ceramic oscillator and stray capacitance of the board, the user should consult with the ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC 2, and elements should be as short as possible, and must not cross other wiring (see figure 18).
40
HD404344R Series/HD404394 Series
Input/Output
The HD404344R series and HD4074344 MCU has 22 input/output pins (D0-D 5, R00-R3 3 ) and the HD404394 MCU has 21 input/output pins (D0-D5, R00-R2 3, R31-R3 3). These input/output pins have the following features: * All 22 pins for the HD404344R series and HD4074344 have a CMOS output circuit. Ten pins D1, D2, and R1 0-R2 3 are large current input/output pins. * Three input/output pins of the 21 pins on the HD404394 series, R10-R12, have intermediate-voltage NMOS open drain output circuits. Five other input/output pins, R13 and R20-R23, have standard-voltage NMOS open drain output circuits. The remaining 13 input/output pins, D0-D5, R00-R0 3 and R31-R33, have CMOS output circuits. Ten pins D1, D2, and R10-R2 3 are high-current input/output pins. * Some input/output pins are multiplexed with peripheral functions, such as for the timers and serial interface. For these pins, the settings for peripheral functions are done prior to the D or R ports settings. If these pins are set as peripheral functions, the pin functions and input/output selections automatically switch according to the settings. * Program control of input/output port selection, as well as peripheral function selection. * All peripheral function output pins are CMOS output pins. However, the R0 2/SO pin can be programmed to be NMOS open drain output. * In stop mode, all peripheral function selections are cleared because of the MCU being reset. Also, the input/output pins go into a high-impedance state. * All input/output pins for both the HD404344R series, HD4074344 and the HD404394 series except for pins R10-R2 3, have built-in pull-up MOS. Therefore they can be individually turned on or off by software. * When pin functions are set as peripheral functions after selecting the pins as pull-up MOS, the pins are maintained as pull-up MOS from the time of selection. Also, pull-up MOS can be selected by software after setting the pin functions as peripheral functions. The control of the input/output pins are shown in table 17 and the circuit configuration of each input/output pin is shown in table 18. Table 17 Programmable Control of Standard I/O Pins
0 0 0 PMOS NMOS Pull-up MOS Note: -- indicates off. -- -- -- 1 -- -- -- 1 0 -- On -- 1 On -- -- 1 0 0 -- -- -- 1 -- -- On 1 0 -- On -- 1 On -- On
MIS3 (bit 3 of MIS) DCD, DCR PDR CMOS buffer
41
HD404344R Series/HD404394 Series
Table 18 Circuit Configurations of I/O Pins
Pins HD404344R Series, HD4074344
Pull-up control signal Buffer control signal DCD, DCR Output data PDR HLT MIS3
HD404394 Series D0-D 5, R0 0, R0 1 R0 3, R3 1-R3 3
I/O Pin Type Input/output pins
Circuit
VCC
D0-D 5, R0 0, R0 1 R0 3, R1 0-R3 3
VCC
Input data Input control signal VCC VCC
None
Buffer control signal HLT DCR Output data PDR
R1 3, R2 0-R2 3 (standard voltage pins)
Input data Input control signal VCC Pull-up control signal Buffer control signal Output data DCR MIS2 PDR HLT MIS3
R0 2
R0 2
VCC
Input data Input control signal HLT DCR PDR Input data Input control signal
None
R1 0-R1 2 (middle voltage pins)
42
HD404344R Series/HD404394 Series
Table 18 Circuit Configurations of I/O Pins (cont)
Pins HD404344R HD404394 Series, Series HD4074344
VCC Pull-up control signal HLT MIS3
I/O Pin Type Peripheral function pins Input/ output pins
Circuit
VCC
SCK
SCK
Output data Input data
SCK
SCK HLT MIS3
Output pins
VCC
VCC
Pull-up control signal
SO
SO
PMOS control signal MIS2 Output data SO HLT MIS3
VCC
VCC
Pull-up control signal
TOC
TOC
Output data
TOC
Input pins
VCC Input data
HLT MIS3 PDR SI, INT0, EVNB, STOPC HLT MIS3 PDR
SI, INT0, EVNB, STOPC
SI, INT0, EVNB, STOPC
VCC
AN 0-AN 3
AN 1-AN 3
A/D input
Input control
Note: In stop mode, the MCU is reset and the peripheral function selection is cancelled. Also, the HLT signal goes low, and input/output pins enter a high-impedance state.
43
HD404344R Series/HD404394 Series
D Port The D port consists of six input/output pins each addressed by one bit. The D ports can be set and reset by SED/RED and SEDD/REDD instructions. Output data is stored in the port data register (PDR) for each pin. Also, all D ports can tested by the TD/TDD instructions. The on/off status of the output buffers is controlled by the D-port data control registers (DCD0, DCD1: $02C and $02D), which are mapped to memory addresses (figure 19). Pins D0 and D4 are multiplexed with peripheral function pins INT0/EVNB, and STOPC. Setting of the peripheral functions for these pins is executed by bits 3 and 0 (PMRB3, PMRB0) of port mode register B (PMRB: $024) (figure 20).
Data control register DCD0, DCD1 DCR0 to DCR3 Bit Initial value Read/Write Bit name 3 0 W DCD03 (DCD0, DCD1: $02C, $02D) (DCR0 to DCR3: $030 to $033) 2 0 W DCD02 1 0 W DCD01 to DCD11 DCR01 to DCR31 0 0 W DCD00 to DCD10 DCR00 to DCR30 Bits 0 to 3 CMOS Buffer Control 0 1 CMOS buffer off (high impedance) CMOS buffer on
DCR03 to DCR33
DCR02 to DCR32
Correspondence between ports and DCR bits Register DCD0 DCD1 DCR0 DCR1 DCR2 DCR3 Bit 3 D3 -- R03 R13 R23 R33 Bit 2 D2 -- R02 R12 R22 R32 Bit 1 D1 D5 R01 R11 R21 R31 Bit 0 D0 D4 R00 R10 R20 R30*
Note: * Available for the HD404344R series and HD4074344, but not available for the HD404394 series.
Figure 19 Data Control Register (DCR)
44
HD404344R Series/HD404394 Series
Port mode register B (PMRB: $024) Bit Initial value Read/Write Bit name 3 0 W 2 -- -- 1 -- -- 0 0 W
PMRB3 Not used Not used PMRB0
PMRB3 D4/STOPC Mode Selection 0 1 D4 STOPC
PMRB0 0 1
D0/INT0 /EVNB Mode Selection D0 INT0 /EVNB
Figure 20 Port Mode Register B (PMRB)
45
HD404344R Series/HD404394 Series
R Port The R port consists of input/output pins each addressed by 4 bits. Input/output is controlled by the LAR and LBR instructions and the LRA and LRB instructions. The output data is stored in the port data register (PDR) of each pin. The on/off status of the output buffers is controlled by the R-port data control registers (DCR0-DCR3: $030-$033), which are mapped to memory addresses (figure 19). The R10-R1 2 ports of the HD404394 series are n-channel middle-voltage open drain input/output pins. The R00-R03 pins are also used as peripheral function pins: SCK, SI, SO, and TOC. Setting of the peripheral functions for these pins is executed by bit 3 (SMR3) of the serial mode register (SMR:$005) and by bits 2 to 0 (PMRA2-PMRA0) of port mode register A (PMRA: $004), as shown in figures 21 and 22. The R30-R3 3 pins of the HD404344R series and HD4074344 are also used as AN0-AN3 peripheral function pins. Pins R31-R33 of the HD404394 series are also used as AN 1-AN3 peripheral function pins. The setting of peripheral functions for these pins is executed by bits 3 to 0 (AMR13-AMR10) of A/D mode register 1 (AMR1: $019). For the HD404394 series, the use of AMR10 is prohibited (figure 23).
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 -- -- 2 0 W 1 0 W 0 0 W
Not used PMRA2 PMRA1 PMRA0 PMRA0 R02/SO Mode Selection R02 SO R01/SI Mode Selection R01 SI
PMRA2 0 1
R03/TOC Mode Selection R03 TOC
0 1 PMRA1 0 1
Figure 21 Port Mode Register A (PMRA)
46
HD404344R Series/HD404394 Series
Serial mode register (SMR: $005) Bit Initial value Read/Write Bit name 3 0 W SMR3 2 0 W SMR2 1 0 W SMR1 0 0 W SMR0
SMR3 0 1
R00/SCK Mode Selection R00 SCK
SMR2 0
SMR1 0
SMR0 0 1
SCK Output
Clock Source Prescaler
Prescaler Division Ratio See table 22.
1
0 1
1
0
0 1
1
0 1
Output Input
System clock External clock
-- --
Figure 22 Serial Mode Register (SMR)
A/D mode register 1 (AMR1: $019) Bit Initial value Read/Write Bit name 3 0 W AMR13 2 0 W AMR12 1 0 W AMR11 0 0 W AMR10 AMR10* AMR12 0 1 AMR13 0 1 R32/AN2 Mode Selection R32 AN2 R33/AN3 Mode Selection R33 AN3 0 1 AMR11 0 1 R30/AN0 Mode Selection R30 AN0 R31/AN1 Mode Selection R31 AN1
Note: * Available for the HD404344R series and HD4074344, but not available for the HD404394 series.
Figure 23 A/D Mode Register 1 (AMR1)
47
HD404344R Series/HD404394 Series
Pull-Up MOS Transistor Control Pull-up MOS, which can be controlled by software, is built into all input/output pins except R10-R2 3 of the HD404394 series. The on/off status of all pull-up MOS pins is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C) and the port data registers (PDR) of each pin. Each pin can therefore independently switch between with or without pull-up MOS (table 17 and figure 24). The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS3 0 1
Pull-Up MOS On/Off Selection Pull-up MOS off Pull-up MOS on
MIS2 0 1
PMOS On/Off Selection for Pin R02/SO On Off
Programming MIS1 and MIS0 to 1 is prohibited.
Figure 24 Miscellaneous Register How to Deal with Unused I/O Pins When input/output pins are not being used and are left floating, it is necessary to set these pins to VCC to reduce the possibility of LSI malfunctions due to noise. This can be done by selecting pull-up MOS for the pins or by connecting an external pull-up resistor of about 100 k at each unused pin.
48
HD404344R Series/HD404394 Series
Prescaler
The MCU has one built-in prescaler, S (PSS). This divides the system clock and outputs the divided clock to the peripheral function modules as shown in figure 25. Clocks for timers B and C except for external events, and clocks for serial interface except for the external clock are all selected from the prescaler output by programming each mode register. Prescaler S is an 11-bit counter which inputs the system clock. After an MCU reset clears the prescaler to $000, it begins dividing the system clock. Prescaler S stops operating due to either an MCU reset or stop mode. It cannot be stopped by any other mode.
Timer B Timer C System clock Prescaler S Serial
Figure 25 Prescaler Output Supply
49
HD404344R Series/HD404394 Series
Timers
The MCU has two built-in timers, B and C. The functions of each timer are listed in table 19. Table 19
Functions Clock source Prescaler S External event Timer functions Free-running Event counter Reload Watchdog Timer output PWM
Timer Functions
Timer B Available Available Available Available Available -- -- Timer C Available -- Available -- Available Available Available
Timer B Timer B is an 8-bit multifunction timer that includes free-running, reload, and event counter features. These are described as follows. * By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler S can be selected, or timer B can be used as an external event counter. * By setting timer mode register B2 (TMB2: $026), timer B can be incremented by each edge detector of input signals at pin EVNB. * By setting timer write register BL, BU (TWBL, TWBU: $00A, $00B), timer counter B (TCB) can be written to during reload timer operation. * By setting timer read register BL, BU (TRBL, TRBU: $00A, $00B), the contents of timer counter B can be read out. Timer B Operation * Free-running/reload timer operation: The selection of the free-running/reload timer, input clock source, and prescaler division ratio is done by timer mode register B1 (TMB1: $009). Timer B is initialized to the data which is written to timer write register B (TWBL: $00A, TWBU: $00B) by software. The data is then incremented in steps of 1 by using the input clock. If the clock input is continued after timer B is set to $FF, an overflow occurs. Timer B then begins counting again, setting the timer to the value in timer write register B (TWBL: $00A, TWBU: $00B) when the reload timer is selected, or reset to $00 when the free-running timer is selected.
50
HD404344R Series/HD404394 Series
The timer B interrupt request flag is set by an overflow. Resetting the timer B interrupt request flag (IFTB: $002, bit 0) is executed by either software or by an MCU reset. * External event counter operation: By setting the external event input as an input clock source, timer B can operate as an external event counter. The D0/INT 0/EVNB pins are set to be INT0/EVNB pins by port mode register B (PMRB: $024). The detection edge of the external event counter for timer B is selected as rising edge, falling edge, or rising/falling edge by timer mode register B2 (TMB2: $026). When the rising/falling edge is selected, the period must be set to more than 2tcyc between the falling edge and the rising edge. Timer B is incremented by 1 using the edge selection in timer mode register B2 (TMB2: $026). Other functions are based on the free-running/reload timer.
Interrupt request flag of timer B (IFTB) Timer read register BU (TRBU)
Timer read register B lower (TRBL)
Clock Internal data bus 51 Free-running timer control Timer counter B (TCB) Overflow
Timer write register B upper (TWBU) Timer write register B lower (TWBL)
EVNB Edge detector oPER
Selector /2 /4 /8 /32 /128 /512 /2048
3 Timer mode register B1 (TMB1)
System clock
Prescaler S (PSS) Edge detection control
2
Timer mode register B2 (TMB2)
Figure 26 Timer B Free-Running and Reload Operation Block Diagram
HD404344R Series/HD404394 Series
Using Timer B Registers Timer B sets the operation and the read/write data according to the following registers. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $026) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register B (PMRB: $024)
* Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload timer, input clock, and prescaler division ratio, as shown in figure 27. It is reset to $0 by an MCU reset. Data written to timer mode register B1 is valid after two instruction cycles. The initial setting of timer B, which is set by writing to timer write register B (TWBL: $00A, TWBU: $00B), should be programmed only after a mode change has been effective.
Timer mode register B1 (TMB1: $009) Bit Initial value Read/Write Bit name 3 0 W TMB13 2 0 W TMB12 1 0 W TMB11 0 0 W TMB10
TMB13 0 1
Free-Running/Reload Timer Selection Free-running timer Reload timer
TMB12 0
TMB11 0
TMB10 0 1
Input Clock Period and Input Clock Source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc D0/INT0/EVNB (external event input)
1
0 1
1
0
0 1
1
0 1
Figure 27 Timer Mode Register B1 (TMB1)
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HD404344R Series/HD404394 Series
* Timer mode register B2 (TMB2: $026): Two-bit write-only register that sets the input edge detection of pin EVNB, as shown in figure 28. It is reset to $0 by an MCU reset.
Timer mode register B2 (TMB2: $026) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 W 0 0 W TMB20 TMB20 0 1 1 0 1 EVNB Edge Detection Selection No detection Falling-edge detection Rising-edge detection Rising- and falling-edge detection
Not used Not used TMB21 TMB21 0
Figure 28 Timer Mode Register B2 (TMB2) * Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit (TWBL) and the upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit value cannot be guaranteed. See figures 29 and 30. Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case, the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the timer B value. Timer B is initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer B.
Timer write register B (lower) (TWBL: $00A) Bit Initial value Read/Write Bit name 3 0 W TWBL3 2 0 W TWBL2 1 0 W TWBL1 0 0 W TWBL0
Figure 29 Timer Write Register B (lower) (TWBL)
Timer write register B (upper) (TWBU: $00B) Bit Initial value Read/Write Bit name 3 W 2 W 1 W 0 W
Undefined Undefined Undefined Undefined TWBU3 TWBU2 TWBU1 TWBU0
Figure 30 Timer Write Register B (upper) (TWBU)
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HD404344R Series/HD404394 Series
* Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit (TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit. See figures 31 and 32. The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading TRBL, the count of timer B when TRBU is read can be obtained.
Timer read register B (lower) (TRBL: $00A) Bit Initial value Read/Write Bit name 3 R TRBL3 2 R TRBL2 1 R TRBL1 0 R TRBL0
Undefined Undefined Undefined Undefined
Figure 31 Timer Read Register B (lower) (TRBL)
Timer read register B (upper) (TRBU: $00B) Bit Initial value Read/Write Bit name 3 R TRBU3 2 R TRBU2 1 R TRBU1 0 R TRBU0
Undefined Undefined Undefined Undefined
Figure 32 Timer Read Register B (upper) (TRBU) * Port mode register B (PMRB: $024): Write-only register that selects the D0/INT 0/EVNB pin as shown in figure 20. It is reset to $0 by an MCU reset.
54
HD404344R Series/HD404394 Series
Timer C Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features, which are selected and described as follows. * By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S can be selected. * By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output (PWM output) is enabled. * By setting timer write register CL, CU (TWCL, TWCU: $00E, $00F), timer counter C (TCC) can be written to. * By setting timer read register CL, CU (TRCL, TRCU: $00E, $00F), the contents of timer counter C can be read out. * An interrupt can be requested when timer counter C overflows. * Timer counter C can be used as a watchdog timer for detecting runaway programs.
55
HD404344R Series/HD404394 Series
System reset signal Watchdog on flag (WDON) Watchdog timer controller Interrupt request flag of timer C (IFTC)
Timer read register CU (TRCU) TOC Timer output controller Timer read register C lower (TRCL)
Clock
Timer counter C (TCC) Timer output control
Overflow Internal data bus
Timer write register C upper (TWCU) Timer write register C lower (TWCL)
Selector /2 /4 /8 /32 /128 /512 /1024 /2048
Free-running/ reload timer control 3
System clock
oPER
Prescaler S (PSS)
Timer mode register C (TMC)
Port mode register A (PMRA)
Figure 33 Timer C Block Diagram Timer C Operation * Free-running/reload timer operation: The selection of the free-running/reload timer, input clock source, and prescaler division ratio is done by timer mode register C (TMC: $00D). Timer C is initialized to the data, which is written to timer write register C (TWCL: $00E, TWCU: $00F) by software. The data is then incremented in steps of 1 by using the input clock. If the clock input is continued after timer C is set to $FF, an overflow occurs. Timer C then begins counting again, setting the timer to the value in timer write register C (TWCL: $00E, TWCU: $00F) when the reload timer is selected, or reset to $00 when the free-running timer is selected. The timer C interrupt request flag is set by an overflow. Resetting the timer C interrupt request flag (IFTC: $002, bit 2) is executed by either software or by an MCU reset.
56
HD404344R Series/HD404394 Series
* Watchdog timer operation: Timer C can be used as a watchdog timer for programs that may run out of control. A watchdog timer is enabled when the setting on the watchdog on flag (WDON: $020, bit 1) is 1. When timer C overflows, an MCU reset occurs. This usually controls programs running out of control by initializing timer C through software before timer C counts up to $FF (figure 34).
$FF + 1 Overflow Timer C count value
$00
Time
CPU operation
Normal operation
Timer C clear
Normal operation
Timer C clear
Program runaway
Reset
Normal operation
Figure 34 Watchdog Timer Operation Flowchart * Timer output operation: Timer C can select the timer output mode by selecting the TOC pin after setting bit 2 (PMRA2) of port mode register A (PMRA: $004) to 1. The output of the TOC pin is initialized to 0 by an MCU reset. PWM output is a pulse output function of variable duty. The output wave differs by the contents of timer mode register C and timer write register C, as shown in figure 35.
T x (N + 1) TMC3 = 0 (free-running timer) T TMC3 = 1 (reload timer) T x (256 - N) Notes: T: Input clock period supplied to counter. (The clock input source and system clock division ratio are determined by timer mode register C.) N: Value in timer write register C. (When N = 255 ($FF), PWM output is fixed low.) T x 256
Figure 35 PWM Output Waveform
57
HD404344R Series/HD404394 Series
Using Timer C Registers Timer C sets the operation and the read/write data according to the following registers. Timer mode register C (TMC: $00D) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) * Timer mode register C (TMC: $00D): Four-bit write-only register that selects the free-running/reload timer, input clock, and prescaler division ratio, as shown in figure 36. It is reset to $0 by an MCU reset. The data written to timer mode register C is valid after two instructions cycles. The initial setting of timer C, which is set by writing to timer write register C (TWCL: $00E, TWCU: $00F), should be programmed to execute only after a mode change has been effective.
Timer mode register C (TMC: $00D) Bit Initial value Read/Write Bit name 3 0 W TMC3 2 0 W TMC2 1 0 W TMC1 0 0 W TMC0
TMC3 0 1
Free-Running/Reload Timer Selection Free-running timer Reload timer
TMC2 0
TMC1 0
TMC0 0 1
Input Clock Period 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc
1
0 1
1
0
0 1
1
0 1
Figure 36 Timer Mode Register C (TMC)
58
HD404344R Series/HD404394 Series
* Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit (TWCL: $00E) and an upper digit (TWCU: $00F), as shown in figures 37 and 38. The operation of this register is the same as that of timer write register B.
Timer write register C (lower) (TWCL: $00E) Bit Initial value Read/Write Bit name 3 0 W TWCL3 2 0 W TWCL2 1 0 W TWCL1 0 0 W TWCL0
Figure 37 Timer Write Register C (lower) (TWCL)
Timer write register C (upper) (TWCU: $00F) Bit Initial value Read/Write Bit name 3 W 2 W 1 W 0 W
Undefined Undefined Undefined Undefined TWCU3 TWCU2 TWCU1 TWCU0
Figure 38 Timer Write Register C (upper) (TWCU) * Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit (TRCL: $00E) and upper digit (TRCU: $00F), which allows the upper digit of timer C to be read directly (figures 39 and 40). The operation of this register is the same as that of timer read register B.
Timer read register C (lower) (TRCL: $00E) Bit Initial value Read/Write Bit name 3 R TRCL3 2 R TRCL2 1 R TRCL1 0 R TRCL0
Undefined Undefined Undefined Undefined
Figure 39 Timer Read Register C (lower) (TRCL)
Timer read register C (upper) (TRCU: $00F) Bit Initial value Read/Write Bit name 3 R TRCU3 2 R TRCU2 1 R TRCU1 0 R TRCU0
Undefined Undefined Undefined Undefined
Figure 40 Timer Read Register C (upper) (TRCU)
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HD404344R Series/HD404394 Series
Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 20. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 20 PWM Output Following Update of Timer Write Register
PWM Output Mode Free running Timer Write Register is Updated during High Timer Write Register is Updated during Low PWM Output PWM Output
Timer write register updated to value N Timer write register updated to value N
Interrupt request
Interrupt request
T x (255 - N) T x (N + 1)
T x (N' + 1) T x (255 - N) T x (N + 1)
Reload
Timer write register updated to value N
Interrupt request
Timer write register updated to value N
Interrupt request
T
T x (255 - N)
T
T T x (255 - N) T
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HD404344R Series/HD404394 Series
Serial Interface
The MCU has a one-channel 8-bit serial interface built in with the following features. * One of 12 different internal clocks or an external clock can be selected as the transmit clock. The internal clocks include the six prescaler outputs divided by two and by four, and the system clock. * During idle states, the serial output pin can be controlled as high or low output. * Transmit clock errors can be detected. * An interrupt request can be generated when any errors occurred or data transfer has completed.
SO Idle controller SCK I/O controller SI Clock
Octal counter (OC)
Serial interrupt request flag (IFS)
Serial data register (SR) Internal data bus 61
Selector 3 /2 /8 /32 /128 /512 /2048 Serial mode register (SMR)
System clock
oPER
Prescaler S (PSS)
Selector
1/2
1/2
Transfer control signal
Port mode register C (PMRC)
Figure 41 Serial Interface Block Diagram
HD404344R Series/HD404394 Series
Serial Interface Operation Selection and Changing of Serial Interface Operation Mode: The available settings for port mode register A (PMRA: $004) and the serial mode register (SMR: $005) are shown in table 21. To change the operating mode or to initialize the serial interface, write to the serial mode register. The R0 0/SCK pin is controlled by writing data to serial mode register (SMR: $005). The R01 /SI and R0 2/SO pins are controlled by writing data to port mode register A (PMRA: $004). Table 21
SMR Bit 3 1
Serial Interface Operating Modes
PMRA Bit 1 0 Bit 0 0 1 1 0 1 Operating Mode Continuous clock output mode Transmit mode Receive mode Transmit/receive mode
Setting Serial Clock Source: The transmit clock is set by writing to the serial mode register (SMR: $005) and port mode register C (PMRC: $025). Serial Data Setting: Serial data is sent by writing to the serial data register (SRL: $006 and SRU: $007). Serial data can then be obtained by reading the serial data register. Serial data is shifted by the transmit clock. The output of the SO pin is undefined until the first serial data is output after an MCU reset, or until the output level control is performed during an idle state. Transfer Control: Serial interface operation is initiated by an STS instruction. The octal counter is reset by the STS instruction to 000 and then incremented by one by the rising edge of the transmit clock. If eight rising edges from the transmit clock is input or the serial data transfer is cut-off, the counter is reset to 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and the serial data transfer stops. As for using the built-in prescaler output for the transmit clock, selection for the transmit clock frequency can be from 4tcyc to 8192t cyc by setting bits 2 to 0 (SMR2-SMR0) of the serial mode register (SMR: $005) and bit 0 (PMRC0) of port mode register C (PMRC: $025). Writing to these registers for the setting of the transmit clock is shown in table 22.
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HD404344R Series/HD404394 Series
Table 22
PMRC Bit 0 0
Transmit Clock Selection (Prescaler Output)
SMR Bit 2 0 Bit 1 0 Bit 0 0 1 1 0 1 1 0 0 1 Prescaler Division Ratio / 2048 / 512 / 128 / 32 /8 /2 / 4096 / 1024 / 256 / 64 / 16 /4 Transmit Clock Frequency 4096t cyc 1024t cyc 256t cyc 64t cyc 16t cyc 4t cyc 8192t cyc 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc
1
0
0
0 1
1
0 1
1
0
0 1
Serial Interface Operating States: The serial interface has the following operating states shown in figure 42, both in external clock mode and internal clock mode. STS wait state Transmit clock wait state Transfer state Continuous clock output (internal clock mode only)
* STS wait state: The serial interface is put into the STS wait state by an MCU reset (00, 10 in figure 42). While in this state, the serial interface is initialized and does not operate, even if a transmit clock is provided. If an STS instruction is executed while in this state (01, 11), the serial interface transfers to the transmit clock wait state. * Transmit clock wait state: Transmit clock wait state period starts from when an STS instruction is executed until the first transmit clock falling edge. While in the transmit clock wait state, if the transmit clock is input (02, 12), the octal counter is incremented by the transmit clock, the data in the serial data register shifts, and the serial interface enters the transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). By writing to the serial mode register (SMR: $005) (04, 14) while in the transmit clock wait state, the serial interface changes to the STS wait state. * Transfer state: The transfer state period starts from the first falling edge of the transmit clock to the eighth rising edge of the transmit clock. While in the transfer state, if an STS instruction is executed or eight pulses of the transmit clock is applied, the octal counter will reset to 000 and the state will change. If an STS instruction is executed (05, 15), the state changes to the transmit clock wait state. After the
63
HD404344R Series/HD404394 Series
eight pulses of the transmit clock, the state changes to the transmit clock wait state for the external clock mode (03). Also, the state changes to the STS wait state for the internal clock mode (13). In the internal clock mode, the transmit clock stops after eight pulses of the transmit clock are output. While in the transfer state, if the serial mode register (SMR: $005) (06, 16) is written to, the serial interface is initialized and the state changes to the STS wait state. After the transfer state has changed to another state, the octal counter is reset to 000 and the serial interrupt request flag (IFS: $003, 2) is set. * Continuous clock output state (internal clock mode only): Continuous clock output state is the state in which only the transmit clock from the SCK pin is output without data transfer. This can be done only while in internal clock mode. When the status of the 1 and 0 bits (PMRA1, PMRA0) of port mode register A (PMRA: $004) is 00 while in transmit clock wait state, the state can be changed to continuous clock output state by enabling the transmit clock (17). By writing to the serial mode register (SMR: $005) while in continuous clock output state (18), the state will change to the STS wait state.
STS wait state (Octal counter = 000, transmit clock disabled)
MCU reset 00
SMR write 04 STS instruction 01
Transmit clock 02 Transmit clock wait state (Octal counter = 000)
SMR write (IFS 1) 06
Transfer state (Octal counter = 000)
8 transmit clocks 03 or STS instruction 05 (IFS 1)
External clock mode
SMR write 18
STS wait state (Octal counter = 000, transmit clock disabled)
MCU reset 10
Continuous clock output state (PMRA 0, 1 = 0, 0)
SMR write 14 STS instruction 11
8 transmit clocks 13 or SMR write (IFS 1) 16
Transmit clock 17
Transmit clock 12
Transmit clock wait state (Octal counter = 000)
STS instruction 15 (IFS 1)
Transfer state (Octal counter = 000)
Internal clock mode
Note: Refer to the operating states section for the corresponding encircled numbers.
Figure 42 Serial Interface State Transitions
64
HD404344R Series/HD404394 Series
Output Level Control During Idle States: The output level of the SO pin can be set during either STS wait state or transmit clock wait state by software. During idle states, the output level is controlled by writing to bit 1 (PMRC1) of port mode register C (PMRC: $025). An example of output level control during idle states is shown in figure 43. During transfer state, output level control cannot be executed.
Transmit clock wait state State MCU reset Port selection PMRA write External clock selection SMR write Output level control in idle states PMRC write Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined LSB MSB Dummy write for state transition Output level control in idle states STS wait state Transfer state Transmit clock wait state STS wait state
IFS External clock mode Transmit clock wait state State MCU reset Port selection PMRA write Internal clock selection SMR write Output level control in idle states PMRC write SRL, SRU write STS instruction SCK pin (output) SO pin Undefined LSB MSB Data write for transmission Output level control in idle states STS wait state Transfer state STS wait state Flag reset at transfer completion
IFS Internal clock mode Flag reset at transfer completion
Figure 43 Example of Serial Interface Operation Sequence
65
HD404344R Series/HD404394 Series
Transmit Clock Error Detection (External Clock Mode): Serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during data transfer. A transmit clock error of this type can be detected as shown in figure 44. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer is completed and IFS is reset, writing to the serial mode register (SMR: $005) changes the state from transfer to STS wait. At this time the serial interface is in the transfer state, and the serial interrupt request flag (IFS: $003, bit 2) is set again, and therefore the error can be detected.
Transfer completion (IFS 1)
Interrupts inhibited
IFS 0
SMR write
IFS = 1?
Yes
Transmit clock error processing
No Normal termination Transmit clock error detection flowchart Transmit clock wait state Transfer state Transfer state
Transmit clock wait state State SCK pin (input)
Noise 1 2 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SMR is written, IFS is set.
SMR write
IFS Flag set because octal counter reaches 000. Transmit clock error detection procedure Flag reset at transfer completion.
Figure 44 Transmit Clock Error Detection
66
HD404344R Series/HD404394 Series
Notes On Use: * Initializing after writing to registers: If port mode register A (PMRA: $004) is written to in the transmit clock wait state or transfer state, the serial interface should be reinitialized by writing to the serial mode register (SMR: $005). * Serial interrupt request flag (IFS: $003, bit 2) set: For the serial interface, if the state is changed from transfer state to another by writing to serial mode register (SMR:$005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag (IFS: $003, bit 2) is not set. To set the serial interrupt request flag (IFS: $003, bit 2), a serial mode register (SMR: $005) write or STS instruction execution must be programmed to be executed after confirming that the SCK pin is at 1, that is, after executing the input instruction to port R0. Registers for Serial Interface The serial interface operation is selected, and serial data is read and written using the following registers: * * * * * Serial mode register (SMR: $005) Port mode register C (PMRC: $025) Serial data registers (SRL: $006 and SRU: $007) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C)
Serial Mode Register (SMRA: $005): This register has the following functions (figure 45): * * * * R0 0/SCK pin function selection Selection of transmit clock Selection of prescaler division ratio Serial interface initialization
The write-only serial mode register is reset to $0 by an MCU reset. Writing to the serial mode register discontinues the transmit clock input to the serial data registers (SRL: $006 and SRU: $007) and the octal counter. The octal counter is then reset to 000. If the serial mode register is written to during serial interface operation, data transfer will be cut off and the serial interrupt request flag (IFS: $003, bit 2) will be set. Data in the serial mode register becomes effective after two instruction execution cycles from the time the serial mode register is written to. It is therefore necessary to program the STS instruction to be executed two cycles after the serial mode register is written to.
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HD404344R Series/HD404394 Series
Serial mode register (SMR: $005) Bit Initial value Read/Write Bit name 3 0 W SMR3 2 0 W SMR2 1 0 W SMR1 0 0 W SMR0
SMR3 0 1
R00/SCK Mode Selection R00 SCK
SMR2 0
SMR1 0
SMR0 0 1
SCK Output
Clock Source Prescaler
Prescaler Division Ratio See table 22.
1
0 1
1
0
0 1
1
0 1
Output Input
System clock External clock
-- --
Figure 45 Serial Mode Register (SMR) Port Mode Register C (PMRC: $025): This register has the following functions: * Prescaler division ratio selection * Output level control during idle states Port mode register C is a two-bit write-only register, which cannot be changed during data transfer. Bit 0 (PMRC0) selects the prescaler division ratio. Only this bit is reset to 0 by an MCU reset. Bit 1 enables the output level control of the SO pin during an idle state. The output levels at the pins are therefore changed when writing to bit 1 (PMRC1).
68
HD404344R Series/HD404394 Series
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1
Undefined
0 0 W PMRC0
W
Not used Not used PMRC1
PMRC0 0 1 PMRC1 0 1
Transmit Clock Division Ratio Prescaler output divided by 2 Prescaler output divided by 4 Output Level Control in Idle States Low level High level
Figure 46 Port Mode Register C (PMRC)
69
HD404344R Series/HD404394 Series
Serial Data Register (SRL: $006, and SRU: $007): This register has the following functions (figures 47 and 48): * Transmission data write and shift * Receive data shift and read Data written to the serial data registers is output from the SO pin, LSB first, synchronously with the falling edge of the transmit clock. Also, data from the SI pin (from the LSB) is input synchronously with the rising edge of the transmit clock. Reading or writing to the serial data register should be performed after data transfer. Read/write operation to this register during data transfer does not guarantee valid data. The input/output timing chart for the transmit clock and the data are shown in figure 49.
Serial data register (lower) (SRL: $006) Bit Initial value Read/Write Bit name 3 R/W SR3 2 R/W SR2 1 R/W SR1 0 R/W SR0
Undefined Undefined Undefined Undefined
Figure 47 Serial Data Register (SRL)
Serial data register (upper) (SRU: $007) Bit Initial value Read/Write Bit name 3 R/W SR7 2 R/W SR6 1 R/W SR5 0 R/W SR4
Undefined Undefined Undefined Undefined
Figure 48 Serial Data Register (SRU)
Ttransmit clock 1 Serial output data Serial input data latch timing LSB 2 3 4 5 6 7 8 MSB
Figure 49 Serial Interface Timing
70
HD404344R Series/HD404394 Series
Port Mode Register A (PMRA: 004): This register A has the following functions: * R0 1/SI pin function selection * R0 2/SO pin function selection Port mode register A is a three-bit write-only register and reset to 0 by an MCU reset, as listed in figure 50.
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 -- -- 2 0 W 1 0 W 0 0 W
Not used PMRA2 PMRA1 PMRA0 PMRA0 R02/SO Mode Selection R02 SO R01/SI Mode Selection R01 SI
PMRA2 0 1
R03/TOC Mode Selection R03 TOC
0 1 PMRA1 0 1
Figure 50 Port Mode Register A (PMRA) Miscellaneous Register The miscellaneous register (MIS: $00C) has the following functions: * Control of R0 2/SO pin PMOS * Pull-up MOS on/off selection It is a two-bit write-only register and is reset to $0 by an MCU reset, as listed in figure 51.
71
HD404344R Series/HD404394 Series
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS3 0 1
Pull-Up MOS On/Off Selection Pull-up MOS off Pull-up MOS on
MIS2 0 1
PMOS On/Off Selection for Pin R02/SO On Off
Programming MIS1 and MIS0 to 1 is prohibited.
Figure 51 Miscellaneous Register
72
HD404344R Series/HD404394 Series
A/D Converter
The MCU has a built-in A/D converter that uses a sequential comparison method with a register ladder. It can perform a digital conversion with 3 or 4 analog inputs at 8-bit resolution. The following describes the features of the A/D converter. * A/D mode register 1 (AMR1: $019) is used to select digital or analog ports (figure 53). * A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed (figure 54). * The A/D channel register (ACR: $016) is used to select an analog input channel (figure 55). * A/D conversion is started by setting the A/D start flag (ADSF: $020, bit 2) to 1. After the conversion is completed, converted data is stored in the A/D data register, and at the same time, the A/D start flag is cleared to 0 (figure 56). * By setting the IAD off flag (IAOF: $021, bit 2) to 1, the current flowing through the resistance ladder can be cut off even in standby or active mode (figure 57). * A/D data registers (ADRL: $017, ADRU: $018) are read-only registers used to store the conversion result. (ADRL: lower 4 bits, ADRU: upper 4 bits.) These registers cannot be cleared by a reset input. Also, data in these registers are not guaranteed during the conversion period. After the conversion is completed, an 8-bit result is set to these registers and kept until the next conversion starts (figures 58, 59, and 60). Notes On Use: * Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF). * Do not write to the A/D start flag during A/D conversion. * Data in the A/D data register during A/D conversion is undefined. * Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D converter does not operate in stop mode. In addition, to save power dissipation while in a stop mode, all current flowing through the converter's resistance ladder is cut off. * Output signal level from other ports should be fixed during A/D conversion. * The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC . When using a shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode register as an analog pin will remain pulled up.
73
HD404344R Series/HD404394 Series
4 A/D interrupt request flag (IFAD) A/D mode register 1 (AMR1)
4
A/D mode register 2 (AMR2) A/D data registers (ADRU, L) Internal data bus
R33/AN3 R32/AN2 R31/AN1
*1 (R30/AN0)
Selector
Encoder
+ Comp - D/A VCC (Vref)*2
A/D controller
Control signal for conversion time
A/D channel register (ACR)
A/D start flag (ADSF) GND
IAD off flag (IAOF)
Operating mode signal (1 in stop mode)
Notes: 1. Available for the HD404344R series and HD4074344. Not available for the HD404394 series. 2. Connected to VCC for the HD404344R series and HD4074344. Connected to Vref for the HD404394 series.
Figure 52 A/D Converter Block Diagram
74
HD404344R Series/HD404394 Series
A/D mode register 1 (AMR1: $019) Bit Initial value Read/Write Bit name 3 0 W AMR13 2 0 W AMR12 1 0 W AMR11 0 0 W AMR10 AMR10* AMR12 0 1 AMR13 0 1 R32/AN2 Mode Selection R32 AN2 R33/AN3 Mode Selection R33 AN3 0 1 AMR11 0 1 R30/AN0 Mode Selection R30 AN0 R31/AN1 Mode Selection R31 AN1
Note: * Available for the HD404344R series and HD4074344, but not available for the HD404394 series.
Figure 53 A/D Mode Register 1 (AMR1)
A/D mode register 2 (AMR2: $01A) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 -- -- 0 0 W
Not used Not used Not used AMR20
AMR20 0 1
Conversion Time 34tcyc 67tcyc
Figure 54 A/D Mode Register 2 (AMR2)
75
HD404344R Series/HD404394 Series
A/D channel register (ACR: $016) Bit Initial value Read/Write Bit name 3 0 W ACR3 2 0 W ACR2 1 0 W ACR1 0 0 W ACR0
ACR3 ACR2 ACR1 ACR0 0 0 0 0 1 1 0 1
Analog Input Selection AN0* AN1 AN2 AN3
Note: * Available for the HD404344R series and HD4074344, but not available for the HD404394 series.
Figure 55 A/D Channel Register (ACR)
A/D start flag (ADSF: $020, bit 2) Bit Initial value Read/Write Bit name 3 -- -- Not used 2 0 R/W ADSF 1 0 W 0 -- --
WDON Not used
A/D Start Flag (ADSF) 0 1 A/D conversion completed A/D conversion started
WDON Refer to the description of timers
Figure 56 A/D Start Flag (ADSF)
76
HD404344R Series/HD404394 Series
IAD off flag (IAOF: $021, bit 2) Bit Initial value Read/Write Bit name 3 0 R/W RAME 2 0 R/W IAOF 1 -- -- 0 -- --
Not used Not used
IAD Off Flag (IAOF) 0 1 IAD current flows IAD current is cut off RAME Refer to the description of operating modes
Figure 57 IAD Off Flag (IAOF)
ADRU: $018 3 2 1 0 3 ADRL: $017 2 1 0
MSB Bit 7
LSB Bit 0
Result
Figure 58 A/D Data Register
A/D data register lower (ADRL: $017) Bit Initial value Read/Write Bit name 3 0 R ADRL3 2 0 R ADRL2 1 0 R ADRL1 0 0 R ADRL0
Figure 59 A/D Data Register Lower (ADRL)
77
HD404344R Series/HD404394 Series
A/D data register upper (ADRU: $018) Bit Initial value Read/Write Bit name 3 1 R ADRU3 2 0 R ADRU2 1 0 R ADRU1 0 0 R ADRU0
Figure 60 A/D Data Register Upper (ADRU)
78
HD404344R Series/HD404394 Series
Pin Description in PROM Mode
The HD4074344 and the HD4074394 are PROM versions of a ZTATTM microcomputer. In PROM mode, the MCU stops operating, thus allowing the user to program the on-chip PROM.
Pin Number DP-28S/FP-28DA FP-30D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MCU Mode Pin R1 0 R1 1 R1 2 R1 3 R2 0 R2 1 R2 2 R2 3 OSC 1 OSC 2 GND NC R3 0/AN0 or Vref R3 1/AN1 R3 2/AN2 R3 3/AN3 NC VCC TEST RESET R0 0/SCK R0 1/SI R0 2/SO R0 3/TOC D0/INT0/EVNB D1 D2 D3 D4/STOPC D5 I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC VPP RESET O1 O2 O3 O4 A0 A1 A2 A3 CE A4 I I I/O I/O I/O I/O I I I I I I I/O or Vref I/O I/O I/O M0 XON O0 I I I/O 2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I O GND PROM Mode Pin A5 A6 A7 A8 A9 A10 A11 A12 OE I/O I I I I I I I I I Remarks
Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin 2. R3 0/AN0 is for the HD404344R series and V ref for the HD404394 series in MCU mode.
79
HD404344R Series/HD404394 Series
Programmable ROM Operation The HD4074344 and HD4074394 on-chip PROMs are programmed in PROM mode. In PROM mode, the MCU does not operate. It can be programmed like a standard 27256 EPROM using a standard PROM programmer and a socket adapter as shown in figure 61. Table 23 lists the recommended PROM programmers and socket adapters. Since instructions of the HMCS400 series consists of 10 bits, the HMCS400 series microcomputers incorporate a conversion circuit to enable the use of a general-purpose PROM programmer. By this circuit, an instruction is read or written to using two addresses, lower five bits and upper five bits. For example, if 4 kwords of on-chip PROM are programmed by a general-purpose PROM programmer, 8 kbytes of addresses ($0000-$1FFF) should be specified.
CE, OE
Control signals
2 A12-A0 A12-A0
A14 , A13 A14-A0 Address bus
3 O4-O0 XON M0 RESET VCC GND VPP HD4074344 HD4074394 O4-O0
O7 -O5 O7-O0 Data bus
VCC GND VPP 28-to-28-pin socket adapter 30-to-28 pin socket adapter PROM programmer
Figure 61 PROM Mode Connections
80
HD404344R Series/HD404394 Series
Table 23 PROM Programmer and Socket Adapter
PROM Programmer Maker DATA I/O AVAL Corp. Type Name UNISITE PKW-3100
Socket Adapter Package DP-28S FP-28DA FP-30D Maker Hitachi Type Name HS4344ESS01H HS4344ESP01H HS4344ESF01H
Programming and Verification The HD4074344 and HD4074394 can be high-speed programmed without causing voltage stress or affecting data reliability. Table 24 shows how programming and verification modes are selected. Table 24 PROM Mode Selection
Pin Mode Programming Verification Programming inhibited CE Low High High OE High Low High VPP VPP VPP VPP O0-O4 Data input Data output High impedance
Precautions 1. Addresses $0000 to $1FFF should be specified if the PROM is programmed by a PROM programmer. If address $2000 or higher is accessed, the PROM may not be programmed or verified correctly. Note that the plastic package type devices cannot be erased and reprogrammed. Set all data in unused addresses to $FF. 2. Be careful of not using the wrong PROM programmer or socket adapter, which may cause an overvoltage and damage the LSI. Make sure that the LSI is firmly fixed onto the socket adapter, and that the socket adapter is firmly fixed to the programmer. 3. The PROM should be programmed with VPP = 12.5 V. Other PROMs use 21 V. If 21 V is applied to the HD4074344 or HD4074394, the LSI may become permanently damaged. 12.5 V is Intel's 27256 VPP.
81
HD404344R Series/HD404394 Series
Addressing Modes
RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 digits from $040 to $04F, are accessed with the LAMR and XMRA instructions. ROM Addressing Modes Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction.
10 3 W X 03 Y 0 Instruction Opcode 3 0
9 RAM address
7
3
0
9 RAM address 0 0 0 1 0 0 Memory Register Addressing
0
Register Indirect Addressing
9 Instruction
1st instruction 2nd instruction word word 09 0 Opcode 9 RAM address Direct Addressing 0
Figure 62 RAM Addressing Modes
82
HD404344R Series/HD404394 Series
Current Page Addressing Mode: A program can branch to any address in the current page (256 words per page) by executing the BR instruction. Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page subroutine area ($0000-$003F) by executing the CAL instruction. Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit immediate data, the accumulator, and the B register by executing the TBR instruction.
1st instruction word
9 3 09
2nd instruction word
0
Opcode
9
5
0
Opcode
Operand
Operand
13
0
13
0
Program counter Direct Addressing
Program counter 0 0 0 0 0 0 0 0 Zero-Page Addressing
Operand Opcode
9 7 0 9 3 07 0
Operand
13 0
Opcode
13
B
A
0
Program counter * * * * * * Current Page Addressing
Program counter 0 0 Table Data Addressing
Figure 63 ROM Addressing Modes
83
HD404344R Series/HD404394 Series
Addressing Mode for P Instruction: By using the P instruction, the ROM data determined by table data addressing can be referenced. The lower-order 8 bits of ROM data are written in the accumulator and the B register when bit 8 of the ROM data is 1, and are written in the R1 and R2 port output registers when bit 9 is 1. If bit 8 and bit 9 are both 1, the ROM data is simultaneously written into the accumulator, the B register, and the R1 and R2 port output registers. (See figure 64.) The program counter is not affected by the P instruction.
Instruction [P] Opcode p3 p2 p1 p0 B3 0 Referenced ROM address 0 B register B2 B1 B0 Accumulator A3 A2 A1 A0
RA13 RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 Address
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
B3
B2
B1
B0
A3
A2
A1
A0
RO8 = 1
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
R23 R22 R21 R20 R13 R12 R11 R10 Pattern Output
RO9 = 1
Figure 64 P Instruction
84
HD404344R Series/HD404394 Series
BR Branching Instruction at Page Boundary: When the BR instruction is at a page boundary (256n + 255), the address in the program counter is transferred over to point to the next page as done by the internal hardware. Therefore, executing the BR instruction at a page boundary will cause the program to branch to the next page. (See figure 65.)
BR AAA
AAA
256 (n - 1) + 255 256n
NOP
BR BR
AAA BBB
256n + 254 256n + 255 256 (n + 1)
BBB
NOP
Figure 65 BR Instruction at Page Boundary
85
HD404344R Series/HD404394 Series
Absolute Maximum Ratings
Item Supply voltage Programming voltage Pin voltage Symbol VCC VPP VT IO -IO IO -I O Topr Tstg Value -0.3 to +7.0 -0.3 to +14.0 Unit V V 1 2 3 4 5 6, 7 6, 8 9 10 11 Notes
-0.3 to VCC + 0.3 V -0.3 to +15.0 V mA mA mA mA mA C C 100 30 30 4
Total permissible input current Total permissible output current Maximum input current
Maximum output current Operating temperature Storage temperature
4 -20 to +75 -55 to +125
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to pin TEST (VPP) of the HD4074344 and HD4074394. 2. Applies to the following pins. HD404344R series and HD4074344: D0-D 5, R0, R1, R2, R3 HD404394 series: D0-D 5, R0, R13, R2, R31-R3 3 3. Applies to the following pins. HD404394 series: R1 0-R1 2 4. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 5. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 6. The maximum input current is the maximum current flowing from each I/O pin to GND. 7. Applies to D 1, D2, R1, and R2. 8. Applies to the following pins. HD404344R series and HD4074344: D0, D3-D 5, R0, R3 HD404394 series: D0, D3-D 5, R0, R31-R3 3 9. The maximum output current is the maximum current flowing out from V CC to each I/O pin. 10. The operating temperature indicates the temperature range in which power can be supplied to the LSI (voltage Vcc shown in the electrical characteristics tables can be applied). 11. In the case of chips, the storage specification differs from that of the package products. Please consult your Hitachi sales representative for details.
86
HD404344R Series/HD404394 Series
Electrical Characteristics
DC Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: VCC = 2.5 to 5.5 V, GND = 0 V, Ta = -20 to +75C, HCD404344R, HCD40C4344R: VCC = 2.5 to 5.5 V, GND = 0 V, T a = +75C, HD404394, HD404392, HD404391, HD4074344, HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified)
Item Input high voltage Symbol VIH Pins RESET, SCK, INT0, STOPC, EVNB SI OSC 1 Input low voltage VIL RESET, SCK, INT0, STOPC, EVNB SI OSC 1 Output high voltage Output low voltage I/O leakage current VOH VOL |IIL| SCK, SO, TOC SCK, SO, TOC RESET, SCK, SI, SO, TOC, OSC 1, INT0, STOPC, EVNB Current I CC1 dissipation in active mode I CC2 I SBY1 Current dissipation in standby mode I SBY2 I SBY3 VCC VCC -- -- 3.5 mA VCC = 5 V, f OSC = 4 MHz -- -- 0.4 0.5 -- -- 1.5 mA mA mA VCC = 3 V, f OSC = 400 kHz VCC = 5 V, f OSC = 4 MHz 2, 4 5 3 2 -0.3 -0.3 -- -- 0.3V CC 0.5 -- 0.4 1 V V V V A -I OH = 0.5 mA I OL = 0.5 mA Vin = 0 V to VCC 1 0.7V CC -0.3 -- VCC + 0.3 V VCC + 0.3 V 0.2V CC V Min 0.8V CC Typ -- Max Unit Test Condition Notes
VCC + 0.3 V
VCC - 0.5 -- --
VCC - 1.0 -- -- -- -- --
-- -- --
-- -- --
0.2 0.4 0.6
mA mA mA
VCC = 3 V, f OSC = 400 kHz VCC = 5 V, f OSC = 800 kHz
3, 4 3, 5 3, 5, 6
87
HD404344R Series/HD404394 Series
DC Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: VCC = 2.5 to 5.5 V, GND = 0 V, Ta = -20 to +75C, HCD404344R, HCD40C4344R: VCC = 2.5 to 5.5 V, GND = 0 V, Ta = +75C, HD404394, HD404392, HD404391, HD4074344, HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) (cont)
Item Symbol Pins VCC Min -- Typ -- Max 10 Unit A Test Condition Vin (RESET) = VCC - 0.3 V to VCC, Vin (TEST) = 0 to 0.3 V Stop mode retaining voltage VSTOP VCC 2 -- -- V Notes
Current I STOP dissipation in stop mode
Notes: 1. Excludes current flowing through pull-up MOS and output buffers. 2. I CC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET, TEST at GND D0-D 5, R0-R3 at V CC 3. I SBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Standby mode Pins: RESET at V CC TEST at GND D0-D 5, R0-R3 at V CC 4. Applies to the HD404394 series and HD4074344. 5. Applies to the HD404344R series. 6. The current in case of excluding the current through A/D converters ladder resistance (flag IAOF is set to "1"). Circuit structure and circuit constants of oscillator circuit is the following condition.
Circuit Structure C1 OSC1 Ceramic oscillator Rf OSC2 C2 Rd
Circuit Constants Ceramic oscillator: KBR-800FTR (KYOSERA) C1 = C2 = 100 pF Rf = 1 M Rd = 2.2 k
88
HD404344R Series/HD404394 Series
I/O Characteristics for Standard Pins (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: V CC = 2.5 to 5.5 V, GND = 0 V, Ta = -20 to +75C, HCD404344R, HCD40C4344R: V CC = 2.5 to 5.5 V, GND = 0 V, Ta = +75C, HD404394, HD404392, HD404391, HD4074344, HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, T a = -20 to +75C, unless otherwise specified)
Pins Item Input high voltage Symbol VIH
HD404344R HD404394 Series Series, HD4074344
Min 0.7V CC
Typ Max --
Unit Test Condition
Note
D0-D 5, R0-R3
D0-D 5, R0, R13, R2, R3 1-R3 3 D0-D 5, R0, R13, R2, R3 1-R3 3 D0-D 5, R0, R3 1-R3 3
VCC + 0.3 V
Input low voltage
VIL
D0-D 5, R0-R3
-0.3
--
0.3V CC
V
Output high VOH voltage
D0-D 5, R0-R3
VCC - 1.0 --
--
V
-I OH = 0.5 mA
-- Output low VOL voltage D0-D 5, R0-R3
R1 3, R2 D0-D 5, R0, R13, R2, R3 1-R3 3 D1, D2, R1 3, R2 D0-D 5, R0, R13, R2, R3 1-R3 3 D0-D 5, R0, R3 1-R3 3
VCC - 0.5 -- -- --
-- 0.4
V V
500 k at V CC I OL = 0.5 mA
2
D1, D2, R1, R2 Input leakage current Pull-up MOS current |IIL| D0-D 5, R0-R3
--
--
2.0
V A
I OL = 15 mA, VCC = 4.5-5.5 V Vin = 0 V to VCC 1
--
--
1
-I PU
D0-D 5, R0-R3
30
150 300
A
VCC = 5 V, Vin = 0 V
Notes: 1. Output buffer current and pull-up MOS current are excluded. 2. Applies to the HD404394 series.
89
HD404344R Series/HD404394 Series
I/O Characteristics for NMOS Intermediate-Voltage Pins for HD404394 Series (VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified)
Item Input high voltage Input low voltage Output high voltage Output low voltage Symbol Pins VIH VIL VOH VOL R1 0-R1 2 R1 0-R1 2 R1 0-R1 2 R1 0-R1 2 R1 0-R1 2 I/O leakage current |IIL| R1 0-R1 2 Min Typ Max 12.0 Unit V Test Condition Notes 1 1 500 k at 12 V I OH = 0.5 mA I OL = 15 mA, VCC = 4.5 to 5.5 V -- -- 20 A Vin = 0 V to 12 V 1, 2 Notes: 1. Applies to the HD404394 series. 2. Excludes output buffer current. 1 1 1
0.7V CC -- -0.3 11.5 -- -- -- -- -- --
0.3V CC V -- 0.4 2.0 V V V
A/D Converter Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: V CC = 2.5 to 5.5 V, GND = 0 V, Ta = -20 to +75C, HCD404344R, HCD40C4344R: V CC = 2.5 to 5.5 V, GND = 0 V, Ta = +75C, HD404394, HD404392, HD404391, HD4074344, HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, T a = -20 to +75C, unless otherwise specified)
Item Symbol Pins Vref Min Typ Max VCC VCC Vref 200 -- -- 4 3 2.0 2.5 3.0 67 -- Unit V V V A pF Bit Channel Channel LSB LSB LSB t cyc M f OSC = 1 MHz, Vin = 0 V Notes: 1. Applies to the HD404344R series. 2. Applies to the HD4074344. 3. Applies to the HD404394 series. Ta = 25C, 1 2 1 2 Test Condition Note 2 1 2 Vref = VCC = 5.0 V 2
Analog reference voltage Vref Analog input voltage AVin I AD
0.5V CC -- -- -- -- 15 8 -- -- -- -- -- -- --
AN 0-AN 3 GND AN 1-AN 3 GND -- AN 0-AN 3 -- -- 0 0
Current flowing between Vref and GND Resolution Number of input channels
Analog input capacitance CA in
Absolute accuracy
AN 0-AN 3 -2.0 AN 0-AN 3 -2.5 AN 1-AN 3 -3.0
Vref = VCC = 5.0 V 3
Conversion time Input impedance
34 AN 0-AN 3 1
90
HD404344R Series/HD404394 Series
AC Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: VCC = 2.5 to 5.5 V, GND = 0 V, Ta = -20 to +75C, HCD404344R, HCD40C4344R: VCC = 2.5 to 5.5 V, GND = 0 V, T a = +75C, HD404394, HD404392, HD404391, HD4074344, HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified)
Item Symbol Pins OSC 1, OSC 2 OSC 1, OSC 2 Min 0.4 1.0 0.89 Typ -- 2.0 -- Max 4.5 3.5 10 Unit Test Condition Note
Clock oscillation frequency f OSC (ceramic oscillator) Clock oscillation frequency f OSC (resistor oscillator) Instruction cycle time (external clock, ceramic oscillator) Instruction cycle time (resistor oscillator) Oscillation setting time (external clock) Oscillation setting time (ceramic oscillator) Oscillation setting time (resistor oscillator) External clock high-level width External clock low-level width External clock rise time External clock fall time INT0, EVNB high-level width INT0, EVNB low-level width RESET low-level width STOPC low-level width RESET rise time STOPC rise time t cyc
MHz Division by 4 MHz Division by 4 Rf = 20 k s Division by 4
t cyc t RC t RC t RC t CPH t CPL t CPr t CPf t IH t IL t RSTL t STPL t RSTr t STPr OSC 1, OSC 2 OSC 1, OSC 2 OSC 1, OSC 2 OSC 1 OSC 1 OSC 1 OSC 1 INT0, EVNB INT0, EVNB RESET STOPC RESET STOPC
1.14 -- -- -- 92 92 -- -- 2 2 2 1 -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- --
4.0 2 2 0.5 -- -- 20 20 -- -- -- -- 20 20
s ms ms ms ns ns ns ns t cyc t cyc t cyc t RC ms ms
Division by 4 Rf = 20 k 1 1 Rf = 20 k 1, 11 2 2 2 2 3 3 4 5 4 5
91
HD404344R Series/HD404394 Series
AC Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: VCC = 2.5 to 5.5 V, GND = 0 V, Ta = -20 to +75C, HCD404344R, HCD40C4344R: VCC = 2.5 to 5.5 V, GND = 0 V, T a = +75C, HD404394, HD404392, HD404391, HD4074344, HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) (cont)
Item Input capacitance Symbol Pins Cin All input pins except TEST, Vref and R10-R1 2 TEST -- -- 15 pF f = 1 MHz, Vin = 0 V -- Vref R1 0-R1 2 -- -- -- -- -- -- -- 40 30 15 30 pF pF pF pF 7 8 9 10 6 Min -- Typ -- Max 15 Unit pF Test Condition Note f = 1 MHz, Vin = 0 V
Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. After V CC reaches the minimum specification value at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of t RC. When using a ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 2. Refer to figure 66. 3. Refer to figure 67. 4. Refer to figure 68. 5. Refer to figure 69. 6. Applies to the HD404341R, HD404342R, HD404344R, HD404391, HD404392, and HD404394. 7. Applies to the HD4074344 and HD4074394. 8. Applies to the HD404394 series. 9. Applies to the HD404344R series. 10. Applies to the HD404394 series and HD4074344. 11. Applies to the HD40C4344R, HD40C4342R, HD404341R
92
HD404344R Series/HD404394 Series
Serial Interface Timing Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: V CC = 2.5 to 5.5 V, GND = 0 V, Ta = -20 to +75C, HCD404344R, HCD40C4344R: V CC = 2.5 to 5.5 V, GND = 0 V, Ta = +75C, HD404394, HD404392, HD404391, HD4074344, HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, T a = -20 to +75C, unless otherwise specified) During Transmit Clock Output
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Transmit clock rise time Transmit clock fall time Symbol t Scyc t SCKH t SCKL t SCKr t SCKf Pins SCK SCK SCK SCK SCK SO SI SI Test Condition Min Load shown in figure 71 Load shown in figure 71 Load shown in figure 71 Load shown in figure 71 Load shown in figure 71 Load shown in figure 71 1 0.4 0.4 -- -- -- 100 200 Typ -- -- -- -- -- -- -- -- Max -- -- -- 80 80 300 -- -- Unit t cyc t Scyc t Scyc ns ns ns ns ns Note 1 1 1 1 1 1 1 1
Serial output data delay time t DSO Serial input data setup time Serial input data hold time t SSI t HSI
During Transmit Clock Input
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Transmit clock rise time Transmit clock fall time Symbol t Scyc t SCKH t SCKL t SCKr t SCKf Pins SCK SCK SCK SCK SCK SO SI SI Load shown in figure 71 Test Condition Min 1 0.4 0.4 -- -- -- 100 200 Typ -- -- -- -- -- -- -- -- Max -- -- -- 80 80 300 -- -- Unit t cyc t Scyc t Scyc ns ns ns ns ns Note 1 1 1 1 1 1 1 1
Serial output data delay time t DSO Serial input data setup time Serial input data hold time Note: 1. Refer to figure 70. t SSI t HSI
93
HD404344R Series/HD404394 Series
OSC 1 1/fCP
VCC - 0.5 V
tCPH
tCPL
0.5 V
tCPr
tCPf
Figure 66 External Clock Timing
INT0, EVNB
0.8VCC
tIH
tIL
0.2VCC
Figure 67 Interrupt Timing
RESET
0.8VCC
tRSTL 0.2VCC tRSTr
Figure 68 RESET Timing
STOPC
0.8VCC
tSTPL 0.2VCC tSTPr
Figure 69 STOPC Timing
94
HD404344R Series/HD404394 Series
t Scyc t SCKf SCK VCC - 0.5 V (0.8VCC )* 0.4 V (0.2VCC)* t DSO SO VCC - 0.5 V 0.4 V t SSI SI 0.7V CC 0.3VCC t HSI t SCKL t SCKH t SCKr
Note: * VCC - 0.5 V and 0.4 V are the threshold voltages for transmit clock output, and 0.8VCC and 0.2VCC are the threshold voltages for transmit clock input.
Figure 70 Serial Interface Timing
VCC RL = 2.6 k Test point C= 30 pF R= 12 k Hitachi 1S2074 H or equivalent
Figure 71 Timing Load Circuit
95
HD404344R Series/HD404394 Series
2.0 Ta = 25C, fcyc = fosc/4 Sample: Typ 1.5 Icc (mA) fosc = 4 MHz fosc = 2 MHz fosc = 1 MHz fosc = 800 kHz fosc = 400 kHz Icc (mA) 2.5 2.0 1.5 1.0 0.5 0.0 1 3 4 5 Vcc (V) (a) Icc vs Vcc Characteristics (ceramic oscillator) Ta = 25C, Rf = 20 k Sample: Typ fosc (MHz) 2 6 1 3 4 5 Vcc (V) (b) Icc vs Vcc Characteristics (resistor oscillator) Ta = 25C, Sample: Typ 4.0 3.0 2.0 1.0 0.0 1 3 4 5 6 Vcc (V) (c) fosc vs Vcc Characteristics (resistor oscillator) Ta = 25C Sample: Typ Vcc = 4.5 V Vcc = 5 V VOL (V) 1.5 1.0 0.5 0.0 0 20 30 40 50 IOL (mA) (e) VOL vs IOL Characteristics (D1, D2, R1, R2 pins) 10 Vcc = 5.5 V 2 0 20 30 40 50 Rf (k) (d) fosc vs Rf Characteristics (resistor oscillator) 10 Vcc = 5 V Vcc = 3.5 V Vcc = 2.5 V 2 6 Ta = 25C, Rf = 20 k fcyc = fosc/4 Sample: Typ
1.0
0.5
0.0
3.5 3.0 fosc (MHz) 2.5 2.0 1.5 1.0
5.0
2.5 2.0
Figure 72 Characteristics curve HD404344R series (consultation value)
96
HD404344R Series/HD404394 Series
Notes On ROM Out
Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as 4-kword versions (HD404344R and HD404394). A 4-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 4-kword version. This limitation apply to the case of using EPROM and the case of using data base.
ROM 1 kwords version: HD404341R, HD40C4341R, HD404391 Address $0400 to $0FFF $0000 Vector address $000F $0010 Zero page subroutine (64 words) $003F $0040 Pattern and program (1,024 words) $03FF $0400 Not used $0FFF Fill this area with all 1s $0FFF $07FF $0800 Not used $003F $0040 Pattern and program (2,048 words) $000F $0010 Zero page subroutine (64 words) $0000 Vector address ROM 2 kwords version: HD404342R, HD40C4342R, HD404392 Address $0800 to $0FFF
97
HD404344R Series/HD404394 Series
HD404341R/HD404342R/HD404344R/HCD404344R/HD40C4341R/HD40C4342R/ HD40C4344R/HCD40C4344R Option List
Please check off the appropriate applications and enter the necessary information. Date of order Customer Department Name ROM code name LSI number 1. ROM size HD404341R HD404342R HD404344R HCD404344R 2. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 3. System oscillator (OSC1-OSC2) (Shaded areas indicate selections that are not available.) HD404341R/HD404342R/HD404344R/HCD404344R Ceramic oscillator External clock RC oscillator 4. Stop mode Used Not used 5. Package type DP-28S FP-28DA FP-30D Chip Note: The specifications of shipped chips differ from of the package product. Please contact our sales staff for details. f= f= MHz MHz HD40C4341R/HD40C4342R/HD40C4344R/HCD40C4344R 1-kword 2-kword 4-kword 4-kword Ceramic oscillator External clock HD404341R HD404342R HD404344R 1-kword 2-kword 4-kword RC oscillator
HCD40C4344R 4-kword
98
HD404344R Series/HD404394 Series
HD404391/HD404392/HD404394 Option List
Please check off the appropriate applications and enter the necessary information. Date of order Customer Department Name ROM code name LSI number 1. ROM size HD404391 HD404392 HD404394 1-kword 2-kword 4-kword
2. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS.
3. System oscillator (OSC1-OSC2) Ceramic oscillator External clock f= f= MHz MHz
4. Stop mode Used Not used
5. Package type DP-28S FP-28DA FP-30D
99
HD404344R Series/HD404394 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
100

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