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| Ordering number : EN5717 LA6542M Monolithic Linear IC LA6542M 4-Channel Bridge (BTL) Driver for CD-ROM Overview The LA6542M is a 4-channel bridge (BTL) driver developed for CD-ROM applications. Package Dimensions unit: mm 3204-MFP36SLF [LA6542] 36 19 Functions * 4-channel power amplifier with bridge circuit (BTL) * IOmax: 1A * Integrated muting circuit (MUTE: Output OFF at Low, output ON at High. MUTE1 is for channels 1 and 2, and MUTE2 for channels 3 and 4.) * Slew rate 0.5 V/s * Integrated thermal shutdown circuit 1 15.3 18 0.15 0.35 0.8 0.85 SANYO : MFP36SLF Specifications Maximum Ratings at Ta = 25C Parameter Maximum supply voltage 1 Maximum supply voltage 2 Maximum input voltage Mute pin voltage Allowable power dissipation Operating temperature Storage temperature Symbol Conditions Ratings 14 Unit V V V V W C C VCCmax VSmax VINmax VMUTEmax Pd max Topr Tstg IC only VS1, 2 Input pins VIN1 to 4 0.1 2.15 2.5max 14 13 13 0.9 -20 to +75 -55 to +150 Operating Conditions at Ta = 25C Parameter Recommended operation voltage 1 Recommended operation voltage 2-1 Recommended operation voltage 2-2 Symbol Conditions Ratings 4 to 13 4 to 13 4 to 13 Unit V V V VCC V S1 V S2 *VCC VS1, 2 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN N1798RM(KI) No. 5717-1/7 0.65 10.5 7.9 9.2 LA6542M Electrical Characteristics at VCC = 12V, VS = 5V, Ta = 25C Parameter VCC no-load current drain Symbol Conditions min All outputs ON (MUTE1, MUTE2: High) All outputs OFF (MUTE1, MUTE2: Low) CH1, 2 ON (MUTE1, MUTE2: High) CH1, 2 OFF (MUTE1, MUTE2: Low) CH3, 4 ON (MUTE1, MUTE2: High) CH3, 4 OFF (MUTE1, MUTE2: Low) Potential difference between plus and minus outputs for CH1 to CH4 Input voltage range for VIN1 to VIN4 Plus and minus outputs at high level IO = 700 mA Ratings typ 5 10 5 10 max 20 10 30 4 10 30 4 -50 0.5 4.4 4.7 50 5 Unit mA mA mA mA mA mA mV V V ICC1 ICC2 IS1-1 IS1-2 VS1 no-load current drain VS2 no-load current drain IS2-1 IS2-2 Output offset voltage Input voltage range Output voltage (source) VOF1 to 4 VIN Vsource (sink) Vsink Plus and minus outputs at low level IO = 700 mA 0.3 0.6 V Closed circuit voltage gain Slew rate Mute ON voltage Mute ON current VG SR VMUTE IMUTE Voltage gain between BTL amplifiers (Note 1) MUTE1, MUTE2 voltage when output is ON (Note 2) MUTE1, MUTE2 current when output is ON (Note 2) 6 0.5 1.5 6 2 10 dB V/s V A Note 1: Guaranteed design value Note 2: MUTE works on all channels. At High, amplifier output is ON and at Low amplifier output is OFF (output impedance becomes HI). Allowable power dissipation, Pd max - W 1.2 Pd max - Ta 1.0 0.9 0.8 IC only 0.6 0.54 0.4 0.2 0 -20 0 20 40 60 80 100 Ambient temperature, Ta - C No. 5717-2/7 LA6542M Pin Assignment RF RF VOUT VIN- VIN+ MUTE1 VIN1 VG1 VIN2 1 2 3 4 5 6 7 8 9 36 35 RF RF 34 VSS 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VSS OUT VO1 VO2 VS1 VO3 VO4 VO5 VO6 VS2 VO7 VO8 VREF OUT VREF IN RF RF LA6542M VG2 10 VIN3 11 VG3 12 VIN4 13 VG4 14 MUTE2 15 VCC 16 RF 17 RF 18 Top view A11265 No. 5717-3/7 LA6542M Pin Function Pin number 1, 2 17, 18 19, 20 35, 36 7, 9 11, 13 8, 10 12, 14 16 22 V IN1, V IN2 Drive Pin name Equivalent circuit Pin function RF Substrate 16 VCC (minimum potential) Input pins for CH1 and CH2 V IN3, V IN4 9 11 7 13 10 12 8 14 VIN Input pins for CH3 and CH4 Input pins for CH1 and CH2 (for gain adjustment) Input pins for CH3 and CH4 (for gain adjustment) VG1, VG2 VG3, VG4 V CC V REFOUT VG A GND 1 2 17 18 19 22 VREF OUT 20 35 36 A11136 Power supply Level shift circuit reference voltage (V REF1 buffer amplifier output*) 3 4 5 6 15 V OUT V INV IN+ OP amp output OP amp inverted input OP amp non-inverted input VCC 16 MUTE1 MUTE2 CH1, CH2 output ON/OFF CH3, CH4 output ON/OFF MUTE1, 2 15 6 To bias circuit GND 1 2 17 18 19 20 35 36 A11138 21 23 24 26 27 28 29 31 32 V REFIN V O8 V O7 V O6 V O5 V O4 V O3 V O2 V O1 29 24 32 27 28 GND 1 2 17 18 19 20 35 36 A11137 Level shift circuit reference voltage input (V REF buffer amplifier input*) CH4 inverted output (AMP8 output) CH4 non-inverted output (AMP7 output) CH3 inverted output (AMP6 output) 16 VCC VO 31 26 23 CH3 non-inverted output (AMP5 output) CH2 inverted output (AMP4 output) CH2 non-inverted output (AMP3 output) CH1 inverted output (AMP2 output) CH1 non-inverted output (AMP1 output) Drive 25 30 33 34 VS2 VS1 V SS -OUT V SS CH3 (AMP5, AMP6), CH4 (AMP7, AMP8) output stage power supply CH1 (AMP1, AMP2), CH2 (AMP3, AMP4) output stage power supply Output stage reference voltage (V SS 1/2: typ) (V REF2 buffer amplifier output*) Connect to VS1, VS2 (resistance split) to generate V SSOUT *See block diagram on next page. No. 5717-4/7 LA6542M Block Diagram RF RF VOUT VIN- VIN+ MUTE1 VIN1 VG1 VIN2 VG2 VIN3 VG3 VIN4 VG4 MUTE2 VCC RF RF 1 2 3 4 - Thermal shutdown MUTE1 MUTE2 VREF2 - + 36 35 34 33 RF RF VSS VSS OUT V O1 V O2 V S1 V O3 V O4 V O5 V O6 V S2 V O7 V O8 VREF OUT VREF IN RF RF 5 6 7 8 9 10 11 12 13 14 15 16 17 18 + - + 32 31 30 VO1 to VO4 - + Level shift - + - 29 28 27 26 25 Level shift + - + - Level shift + - Level shift + - + 24 23 22 - + VO5 to VO8 21 20 19 VREF1 A11139 System Diagram (relationship between power supply and MUTE) CH1 MUTE1 CH2 VS1 CH3 MUTE2 CH4 A11140 VS2 No. 5717-5/7 LA6542M Sample Application Circuit 1 2 3 4 5 Microprocessor Focus input 6 7 8 Tracking input 9 10 Sled input 11 12 Spindle input 13 14 Microprocessor 12V power supply 15 16 17 18 RF RF VOUT VIN- VIN+ MUTE1 VIN1 VG1 VIN2 VG2 VIN3 VG3 VIN4 VG4 MUTE2 VCC RF RF RF 36 RF 35 VSS 34 VSS OUT 33 VO1 32 Focus VO2 31 VS1 30 VO3 29 Tracking VO4 28 VO5 27 M Sled VO6 26 VS2 25 VO7 24 M Spindle VO8 23 VREF OUT 22 VREF IN 21 RF 20 RF 19 Reference voltage 5V power supply LA6542M A11141 No. 5717-6/7 LA6542M Gain Setting (input pins and adjustment pins) A simplified diagram of VIN and VG is shown below. 1) Consider an 11 k (typ.) resistor inserted between VIN and VG. 2) When not the pin VG but the pin VIN is used alone, the BTL gain (between VO+ and VO- ) is set to 6 dB (0 dB for AMP only). This also applies for the case when VIN is not used and an 11 k external resistor is connected to VG for input. 3) Gain is set by the input impedance as seen from point A. When VG only is used and the external resistor is R, the BTL gain (between VO+ and VO-) is 20 log (11 k/R) + 6 dB. When an 11 k resistor is inserted between VIN and VG, and input is via VIN, the combined resistance Rz as seen from point A is Rz = 5.5 k. Gain is 20 log (11 k /5.5 k) + 6 dB = 12 dB. VG 11 k VIN Level shift - AMP1 + VO+ VREF - VREF1 + A VSS 11 k - VREF2 + - AMP2 + V O- 11 k A11142 GND Offset Voltage This IC incorporates a level shifter circuit. The input references the VREF to be applied, and references the voltage (VSS - VBE (0.7))/2V to be output. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice. PS No. 5717-7/7 |
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