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V62C1164096 256K x 16, CMOS STATIC RAM
PRELIMINARY
s s s s s s s s
CILETIV LESOM
Features
A0 A6 A7 A8 A9 I/O1 I/O16 UBE LBE OE WE CE1 CE2
Description
The V62C1164096 is a 4,194,304-bit static random-access memory organized as 262,144 words by 16 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.
High-speed: 85, 100 ns Ultra low CMOS standby current of 2A (max.) Fully static operation All inputs and outputs directly TTL compatible Three state outputs Ultra low data retention current (VCC = 1.0V) Operating voltage: 1.8V - 2.3V Packages - 48-Ball CSP BGA (8mm x 10mm)
Functional Block Diagram
VCC Row Decoder 1024 x 4096 Memory Array GND
Column I/O Input Data Circuit Column Decoder
A10
A17
Control Circuit
Device Usage Chart
Package Outline Operating Temperature Range 0C to 70C -40C to +85C B * * Access Time (ns) 85 * * 100 * * L * Power LL * * Temperature Mark Blank I
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UBE, LBE Byte Enable Active low inputs. These inputs are used to enable the upper or lower data byte. Write Enable Input WE The write enable input is active LOW and controls read and write operations. With the chip enabled, when WE is HIGH and OE is LOW, output data will be present at the I/O pins; when WE is LOW and OE is HIGH, the data present on the I/O pins will be written into the selected memory locations. I/O1-I/O16 Data Input and Data Output Ports These 16 bidirectional ports are used to read data from and write data into the RAM. VCC GND Power Supply Ground
A 0-A17 Address Inputs These 18 address inputs select one of the 256K x 16 bit segments in the RAM. CE1, CE2 Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. OE Output Enable Input The output enable input is active LOW. With the chip enabled, when OE is Low and WE High, data will be presented on the I/O pins. The I/O pins will be in the high impedance state when OE is High.
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Pin Descriptions
1 A B C D E F G H 2 3 4 5 6 A B D E F H TOP VIEW
V62C1164096 Rev. 1.0 November 2001
Pin Configurations (Top View)
48 BGA
1 BLE I/O9 2 OE BHE 3 A0 A3 4 A1 A4 A6 A7 5 A2 6 CE2
CE1 I/O1 I/O2 I/O3 I/O4 VCC
C I/O10 I/O11 A5 VSS I/O12 A17 VCC I/O13 NC
A16 I/O5 VSS
I/O15 I/O14 A14 A15 I/O6 I/O7 NC A8 A12 A13 A9 WE I/O8 NC
G I/O16 NC
A10 A11
Note: NC means no connect. TOP VIEW
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V62C1164096
CILETIV LESOM
V
MOSEL-VITELIC MANUFACTURED 62 = STANDARD
Part Number Information
62 C 18 16 4096 -
TEMP. SRAM FAMILY OPERATING VOLTAGE DENSITY 4096K PWR. 85 ns 100 ns B = BGA ORGANIZATION 16 = 16-bit L = LOW POWER LL = DOUBLE LOW POWER SPEED PKG BLANK = 0C to 70C I = -40C to +85C
C = CMOS PROCESS 18 = 1.8V - 2.3V
Absolute Maximum Ratings (1)
Symbol
VCC VN V DQ TBIAS TSTG
Parameter
Supply Voltage Input Voltage Input/Output Voltage Applied Temperature Under Bias Storage Temperature
Commercial
-0.5 to VCC + 0.5 -0.5 to VCC + 0.5 VCC + 0.3 -10 to +125 -55 to +125
Industrial
-0.5 to VCC + 0.5 -0.5 to VCC + 0.5 VCC + 0.3 -65 to +135 -65 to +150
Units
V V V C C
NOTE: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance* TA = 25C, f = 1.0MHz
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF
NOTE: 1. This parameter is guaranteed and not tested.
Truth Table
Mode
Standby Standby Output Disable Output Disable Read Read Read Write Write Write
CE1
H X L L L L L L L L
CE2
X L H H H H H H H H
OE
X X X H L L L X X X
WE
X X X H H H H L L L
UBE
X X H X L L H L L H
LBE
X X H X L H L L H L
I/O9-16 Operation
High Z High Z High Z High Z DOUT DOUT High Z DIN DIN High Z
I/O1-8 Operation
High Z High Z High Z High Z DOUT High Z DOUT DIN High Z DIN
NOTE: X = Don't Care, L = LOW, H = HIGH
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NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VIL (Min.) = -3.0V for pulse width < 20ns. 3. Maximum values.
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Symbol
VIL VIH IIL IOL VOL V OH
DC Electrical Characteristics (over all temperature ranges, VCC = 1.8V - 2.3V)
Parameter
Input LOW Voltage(1,2) Input HIGH Voltage(1) Input Leakage Current Output Leakage Current Output LOW Voltage Output HIGH Voltage VCC = Max, VIN = 0V to VCC VCC = Max, CE = VIH, VOUT = 0V to VCC VCC = Min, IOL = 2.1mA VCC = Min, IOH = -0. 1mA
Test Conditions
Min.
-0.3 1.6 -1 -1 -- VCC - 0.4
Typ.
-- -- -- -- -- --
Max.
0.4 VCC + 0.3 1 1 0.4 --
Units
V V A A V V
Symbol
ICC1
Parameter
Average Operating Current, CE1 = VIL, CE2 = VCC - 0.2V, Output Open, V CC = Max. TTL Standby Current CE VIH, VCC = Max., f = 0 CMOS Standby Current, CE1 VCC - 0.2V, CE2 < 0.2V V IN VCC - 0.2V or VIN 0.2V, VCC = Max., f = 0
Power Com.(3)
f = fmax f = 1 MHz L LL L LL 25 2 0.4 0.3 5 2
Ind.(3)
30 3 0.5 0.3 7 3
Units
mA
ISB
mA
ISB1
A
AC Test Conditions
Input Pulse Levels Input Rise and Fall Times Timing Reference Levels Output Load 0 to 1.6V
Key to Switching Waveforms
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L OUTPUTS WILL BE STEADY WILL BE CHANGING FROM H TO L WILL BE CHANGING FROM L TO H CHANGING: STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF" STATE
5 ns 0.9V see below
AC Test Loads and Waveforms
MAY CHANGE FROM L TO H
TTL CL*
DON'T CARE: ANY CHANGE PERMITTED DOES NOT APPLY
* Includes scope and jig capacitance CL = 30 pF + 1 TTL Load
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NOTES: 1. tRC = Read Cycle Time 2. TA = +25C.
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Symbol
VDR
Data Retention Characteristics
Parameter
VCC for Data Retention CE1 VCC - 0.2V, CE2 < 0.2V, VIN VCC - 0.2V, or VIN 0.2V Data Retention Current CE1 VDR - 0.2V, CE2 < 0.2V, VIN VCC - 0.2V, or VIN 0.2V, VDR = 1.0V Com'l L LL Ind. L LL tCDR tR Chip Deselect to Data Retention Time Operation Recovery Time (see Retention Waveform)
Power
Min.
1.0
Typ.(2)
--
Max.
2.3
Units
V
ICCDR
-- -- -- -- 0 tRC(1)
1 0.5 -- -- -- --
3 1.5 5 2 -- --
A
ns ns
Low VCC Data Retention Waveform (CE Controlled)
Data Retention Mode VCC 1.8V tCDR CE1 1.6V CE1 VCC - 0.2V VDR 1V tR 1.6V 1.8V
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Read Cycle
Parameter Name
tRC tAA tACS tBA tOE tCLZ tBLZ tOLZ tCHZ tOHZ tBHZ tOH
AC Electrical Characteristics
(over all temperature ranges)
85 Parameter
Read Cycle Time Address Access Time Chip Enable Access Time UBE, LBE Access Time Output Enable to Output Valid Chip Enable to Output in Low Z UBE, LBE to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z UBE, LBE to Output in High Z Output Hold from Address Change
100 Max.
-- 85 85 85 35 -- -- -- 30 30 30 --
Min.
85 -- -- -- -- 10 10 10 0 0 0 10
Min.
70 -- -- -- -- 15 15 10 0 0 0 10
Max.
-- 100 100 100 40 -- -- -- 35 35 35 --
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
Write Cycle
Parameter Name
tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tBW
85 Parameter
Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data Setup to End of Write Data Hold from End of Write UBE, LBE to End of Write
100 Max.
-- -- -- -- -- -- 25 -- -- --
Min.
85 70 0 70 60 0 0 40 0 70
Min.
100 80 0 80 70 0 0 45 0 80
Max.
-- -- -- -- -- -- 35 -- -- --
Unit
ns ns ns ns ns ns ns ns ns ns
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NOTES: 1. WE = VIH. 2. CE1 = VIL. CE2 = VIH. 3. Address valid prior to or coincident with CE transition LOW. 4. OE = VIL. 5. Transition is measured 500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested. 6. UBE = VIL, LBE = VIL.
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Read Cycle 1(1, 2)
ADDRESS OE UBE, LBE I/O
Switching Waveforms (Read Cycle)
tRC
tAA
tOE tOLZ tBLZ
tOHZ(5) tBHZ
tBA
Read Cycle 2(1, 2, 4, 6)
tRC ADDRESS tOH I/O tAA tOH
Read Cycle 3(1, 3, 4, 6)
ADDRESS tACS CE1
CE2 tCLZ(5) I/O tCHZ(5)
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NOTES: 1. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. tWR is measured from the earlier of CE1 or WE going high, or CE2 going LOW at the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention. 5. If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 6. tCW is measured from CE1 going low or CE2 going HIGH to the end of write.
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ADDRESS CE1 CE2 WE OUTPUT INPUT ADDRESS CE1 CE2 WE OUTPUT INPUT
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)(4)
tWC
tWR(2) tCW(6)
tAW tCW(6) tAS
tWP(1)
tWHZ
tDW
tDH
Write Cycle 2 (CE Controlled)(4)
tWC
tCW(6)
(4)
tWR(2)
tAW tCW(6) tAS
High-Z tDW tDH
(5)
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V62C1164096
e
E1
E
A
C
aaa SIDE VIEW
V62C1164096 Rev. 1.0 November 2001
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A1
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Package Diagrams
48 Ball--8x10 BGA
D D1 SYMBOL A A1 6 5 4 3 2 1 A B C D E F G H b c D D1 E E1 e aaa BOTTOM VIEW b SOLDER BALL
UNIT.MM 1.05+0.15 0.250.05 0.35.0.05 0.30(TYP) 10.000.10 5.25 8.000.10 3.75 0.75TYP 0.10
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888
V62C1164096
UK & IRELAND
SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516
U.S.A.
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NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
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U.S. SALES OFFICES
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(c) Copyright , MOSEL VITELIC Inc.
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
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3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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