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STV7620
PLASMA DISPLAY PANEL DATA DRIVER
PRELIMINARY DATA
FEATURES
s s s s s s s s
96 Outputs Plasma Display Driver 90V Absolute Maximum Rating Reduced EMI (Electro Magnetic Interference) 3.3V / 5V Compatible Logic -40 / 30 mA Source / Sink Output Mos 6 Bit Data Bus (40 MHz) BCD Process Packaging Adapted to Customer Request (DICE, COB, COF, TAB).
DESCRIPTION STV7620S/M/F is a data driver for Plasma Display Panel (PDP) designed in the ST proprietary BCD high voltage technology. A new shape of the output pulse generated by the STV7620S/M/F ensures a noticeable EMI reduction. Three different versions are available with various falling edge shapes. Using a 6 bit wide data bus, they can control 96 high current & high voltage outputs. The STV7620S/M/F is supplied with a separated 70V power output supply and a 5V logic supply. All command inputs are CMOS and 3.3V logic levels compatible.
Order code (1) STV7620S STV7620M STV7620F Version slow speed medium speed fast speed
(1) refer to timing characteristics (Section 10)
Please contact STMicroelectronics for ordering information concerning samples or bump version
Version 3.1
April 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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STV7620S/M/F
Revision follow-up
Target specification 02/2001 version 1.0 document creation 03/2001 version 1.1 general update, addition of EMI and figure 1 04/2001 version 1.2 general update, new pads dimensions 10/2001 version 1.3 addition of die photo in cover page, new pads dimensions Electrical characteristics: replaced a few TBD mentions with values AC timing characteristics: some TBD replaced with values F/R replaced with F/R Electrical characteristics: Idoutl/h value replaced with 30mA Preliminary data 02/2002 version 3.0 whole document: sales type becomes STV7620S/M/F for slow, medium, fast general update 04/02/2002 Version 3.1 general update
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STV7620S/M/F
1
BLOCK DIAGRAM
Figure 1. STV7620 S/M/F block diagram
CLK F/R
A1
P1
16bit Shift register
P91
A2
P2
16bit Shift register
P92
A3
P3
16bit Shift register
P93
A4
P4
16bit Shift register
P94
A5
P5
16bit Shift register
P95
A6
P6
16bit Shift register
P96
VSSLOG STB Q1 Q2 Q3 Q4 Q5 Q6 LATCH POC & & & & VCC Q94 Q95 Q96 VSSSUB
BLK & & & &
VSSP
OUT1
OUT96
VPP
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2
DIE PIN OUT / DIE DESCRIPTION
2.06
OUT56 OUT41 OUT40 y 0/0 x OUT2 OUT1 VPP VPP VSSP VSSP VSSLOG VSSSUB POC A6 A5 A4 A3 A2 A1 STB VCC F/R CLK VSSLOG BLK
OUT57
5.68
OUT95 OUT96 VPP VPP VSSP VSSP
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VSSLOG
STV7620S/M/F
3
PADS DIMENSIONS (in m)/ PADS POSITIONS
The reference is the centre of the die (x=0, y=0) Pad size is specified for wire-bonding options . TOP SIDE from left to right
Name OUT56 OUT55 OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 Centre:X -774.478 -671.288 -568.098 -464.907 -361.718 -258.528 -155.338 -52.148 51.042 154.232 257.422 360.612 463.802 566.992 670.267 773.457 Centre:Y 2696.03 2696.03 2696.03 2696.03 2696.03 2696.03 2696.03 2696.03 2696.03 2696.03 2696.03 2696.03 2696.03 2696.03 2696.03 2696.03 Size:x 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 SIze: y 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92
BOTTOM SIDE from right to left
Name VSSSUB VSSLOG VSSLOG Centre:X -567.078 -670.352 -770.822 Centre:Y -2696.03 -2696.03 -2696.03 Size:x 76 76 76 SIze: y 92 92 92
RIGHT SIDE from top to bottom
Name OUT40 OUT39 OUT38 OUT37 OUT36 OUT35 OUT34 OUT33 OUT32 OUT31 OUT30 OUT29 Centre:X 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 Centre:Y 1950.792 1847.602 1744.327 1641.138 1537.947 1434.757 1331.568 1228.378 1125.188 1021.998 918.807 815.618 712.428 609.238 506.048 402.857 299.668 196.478 93.288 -9.902 -113.092 -216.282 -319.472 -422.662 -525.852 -629.042 -732.232 Size:x 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 SIze: y 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76
BOTTOM SIDE from right to left
Name VSSLOG CLK Centre:X 770.822 670.352 567.162 463.972 360.782 258.442 155.252 52.062 -51.128 -154.318 -257.508 -360.698 -463.888 Centre:Y -2696.03 -2696.03 -2696.03 -2696.03 -2696.03 -2696.03 -2696.03 -2696.03 -2696.03 -2696.03 -2696.03 -2696.03 -2696.03 Size:x 76 76 76 76 76 76 76 76 76 76 76 76 76 SIze: y 92 92 92 92 92 92 92 92 92 92 92 92 92
OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14
F/R
POC VCC STB BLK A1 A2 A3 A4 A5 A6
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RIGHT SIDE from top to bottom
Name OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 VPP VPP VSSP VSSP Centre:X 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 887.655 Centre:Y -835.422 -938.612 -1041.802 -1144.992 -1248.182 -1351.372 -1454.562 -1557.752 -1660.942 -1764.132 -1867.322 -1970.512 -2073.702 -2176.722 -2279.912 -2383.018 -2486.208 Size:x 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 SIze: y 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76
LEFT SIDE from bottom to top
Name OUT84 OUT83 OUT82 OUT81 OUT80 OUT79 OUT78 OUT77 OUT76 OUT75 OUT74 OUT73 OUT72 OUT71 OUT70 OUT69 OUT68 OUT67 Centre:X -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 Centre:Y -835.422 -732.232 -629.042 -525.852 -422.662 -319.472 -216.282 -113.092 -9.902 93.287 196.477 299.667 402.857 506.047 609.238 712.428 815.618 918.808 1021.998 1125.188 1228.378 1331.568 1434.758 1537.948 1641.137 1744.328 1847.602 1950.792 Size:x 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 SIze: y 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76
LEFT SIDE from bottom to top
Name VSSP VSSP VPP VPP OUT96 OUT95 OUT94 OUT93 OUT92 OUT91 OUT90 OUT89 OUT88 OUT87 OUT86 OUT85 Centre:X -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 -887.655 Centre:Y -2486.208 -2383.018 -2279.912 -2176.722 -2073.702 -1970.512 -1867.322 -1764.132 -1660.942 -1557.752 -1454.562 -1351.372 -1248.182 -1144.992 -1041.802 -938.612 Size:x 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 SIze: y 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76
OUT66 OUT65 OUT64 OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57
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4
F/R
DATA BUS CONFIGURATION
Input CLK A1 A2 L A3 A4 A5 A6 A1 A2 H A3 A4 A5 A6 Out Out Out Out Out Out Out Out Out Out Out Out 01 01 02 03 04 05 06 91 92 93 94 95 96 02 07 08 09 10 11 12 85 86 87 88 89 90 03 13 14 15 16 17 18 79 80 81 82 83 84 04 19 20 21 22 23 24 73 74 75 76 77 78 05 25 26 27 28 29 30 67 68 69 70 71 72 Data Shift 06 31 32 33 34 35 36 61 62 63 64 65 66 ... 11 61 62 63 64 65 66 31 32 33 34 35 36 12 67 68 69 70 71 72 25 26 27 28 29 30 13 73 74 75 76 77 78 19 20 21 22 23 24 14 79 80 81 82 83 84 13 14 15 16 17 18 15 85 86 87 88 89 90 07 08 09 10 11 12 16 91 92 93 94 95 96 01 02 03 04 05 06 Reverse Shift Forward Shift
This table describes the position of the first data sampled by the first rising edge of the CLK signal. After 16 clock pulses this data will be shifted to Output 91.
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PIN DESCRIPTION
Symbol OUT(01-96) VSSP VPP BLK POC F/R VCC VSSLOG VSSSUB CLK STB IN (A1-A6) OUT(A4-A6) Function Output Ground Supply Input Input Input Supply Ground Ground Input Input Input output Power output Ground of power outputs High voltage supply of power outputs Blanking input Power output control input Selection of shift direction 5V logic supply Logic ground Substrate ground Clock of data shift register Latch of data to outputs Shift register input A1, A2, A3 shift register output Description
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6
CIRCUIT DESCRIPTION
All the output data are kept memorised and held in the latch stage when the latch input STB is pulled high. Vsssub and Vsslog must be connected as close as possible to the logical reference ground of the application. STV7620S/M/F is supplied with a 5 V power supply. All the logic inputs can be driven either by 5V CMOS logic or by 3.3V CMOS logic. A low EMI function has been implemented: the falling edge of the outputs has 2 slopes, a smooth one followed by a steeper one. The smooth slopes width increases from 20ns for the fast version to 55ns for the slow version whatever the external load.
STV7620S/M/F includes all the logic and power circuits necessary to drive the Plasma Display Panel (PDP) column of electrodes. Binary values of each pixel of the displayed line are loaded into the shift register by a 6 bit wide (A1 - A6) data bus. Data is shifted at each low to high transition of the CLK clock. The forward /reverse (F/R) input is used to select the direction of the shift register. The maximum frequency of the shift clock is 40MHz. This leads to an equivalent 240 MHz serial shift register for a 6 x 16 bits arrangement. When the STB signal is Low, data are transferred from the shift register to the latch and the power output stages. Table 1: Shift register truth table
Input F/R L L H H X CLK rise H or L rise H or L X
Shift register function Output Q Forward shift Steady Reverse shift Steady 6 bits shift register
Table 2: Power output truth table
Qn X X X L H
STB
X X H L L
BLK L H H H H
POC X L H H H
Driver Output all L all H Qn L H
Comments Output at low level Output at high level Data latched Data copied Data copied
Qn+1 = A1, Qn+2 = A2, Qn+3 = A3, Qn+4 = A4, Qn+5 = A5, Qn+6 = A6, n = [0,6,12,18,...,90]
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ABSOLUTE MAXIMUM RATINGS
Symbol Vcc Vpp Vin Ipout Idout Tjmax Tstg Vout Logic supply range Driver supply range Logic input voltage range Driver output current (Note 1)(Note 3) ( Note 4:) Diode Output Current ( Note 2:) ( Note 3:) ( Note 4:) Maximum junction temperature Storage temperature range Output power voltage range Parameter Value -0.3, +7 -0.3, +90 -0.3, Vcc+0.3 - 150 / + 150 -200 / +300 125 -50, +150 -0.3, +90 Unit V V V mA mA C C V
Note 1: Through one power output. Note 2: Through one power output for all power outputs (see Figure 4) with Junction temperature lower than or equal to Tjmax Note 3: These parameters are measured during ST's internal qualification which includes temperature characterisation on standard batches and on corners batches of the process. These parameters are not tested on the parts. Note 4: Transient current. Spike current duration inferior to 300ns. Remark: ESD susceptibility Human body model: 100pF, 1.5k A5, A6 pins - VESD = +800 V
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8
ELECTRICAL CHARACTERISTICS
Symbol SUPPLY Vcc Icc Iccl Icc Vpp Vpp Ipph OUTPUT OUT1-OUT96 Vpouth Power output high level (voltage drop versus Vpp) @Ipouth = - 25mA and Vpp = 70V Power output low level @ Ipoutl = + 25mA Output diode voltage drop @ Idouth = + 30mA (Note 7) Output diode voltage drop @ Idoutl = - 30mA (Note 7) 11 16 V Logic supply voltage Logic supply current (Note 5) Logic Dynamic Supply Current (FCLK=20Mhz) (Note 6) Logic Supply Current (Vih=2.0V) Power output supply voltage - DC mode Power output supply voltage - AC mode Power output supply current (steady outputs) 15 15 4.50 20 500 5 5.5 100 750 70 75 100 V A mA A V V A Parameter Min. Typ Max Unit
(Vcc = 5V, Vpp = 70V, Vssp = 0V, Vss = 0V, Tamb = 25C, FCLK = 40 MHz, unless otherwise specified)
Vpoutl
-
8
13
V
Vdouth
-
1
2
V
Vdoutl INPUT
-2
-1
-
V
CLK, F/R, STB, POC, BLK, A1-A6 Vih Vil Iih Iil Cin A4-A6 Voh Vol Note 5: Note 6: Note 7: Note 8: Logic output high level (Ioh = -1mA) Logic output low level (Iol = 1mA) 4.85 0.1 V V Input high level Input low level High level input current (Vih >=2.0V) Low level input current (Vil = 0v) Input capacitance (Note 8) 2.0 0.9 5 5 15 V V A A pF
Logic input levels compatible with 5V CMOS logic All data inputs are commuted at 10MHz see Figure 4.Test configuration page15 This parameter is measured during ST's internal qualification which includes temperature characterization on standard and corner batches of the process. This parameter is not tested on the part.
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9
AC TIMING REQUIREMENTS
Symbol tCLK tWHCLK tWLCLK tSDAT tHDAT tHSTB tSTB tSSTB Data clock period Duration of CLK pulse at high level Duration of CLK pulse at low level Set-up time of data input before low to high clock transition Hold-time of data input after low to high clock transition Hold-time of STB after low to high clock transition STB low level pulse duration STB set-up time before CLK rise Parameter Min. 25 10 10 5 5 5 10 5 Typ Max Unit ns ns ns ns ns ns ns ns
(Vcc = 4.5v to 5.5v, T amb = -20 to +85C, input signals max leading edge & trailing edge (tr,tf) = 5ns)
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10 AC TIMING CHARACTERISTICS
(Vcc = 5V, Vpp = 70V, Vssp = 0V, Vsssub = 0V, Vsslog = 0V, Tamb = 25C, FCLK = 40MHz,) (Vilmax = 0.2Vcc, Vihmin = 0.8Vcc)
Symbol tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tR OUT tF OUT Parameter Delay of power output change after CLK transition - high to low - low to high Delay of power output change after STB transition - high to low - low to high Delay of power output change after BLK, POC transition - high to low - low to high Power output rise time (Note 9) Power output fall time (Note 9) Width of the falling edge smooth shape tS STV7620F: Fast STV7620M: Medium STV7620S: Slow tR DAT tF DAT tPHL4 tPLH4 Logic data output rise time (CL = 10pF) Logic data output fall time (CL = 10pF) Delay of logic data output change after CLK transition - high to low - low to high 12 13 TBD TBD ns ns 25 30 55 9 5 TBD TBD ns ns ns ns ns 50 50 25 20 90 90 200 200 ns ns ns ns 95 95 ns ns 35 30 100 100 ns ns Min. Typ Max Unit
Note 9: one output among 96, loading capacitor CL = 50pF, other outputs at low level
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STV7620S/M/F
Figure 2. AC Characteristics Waveform
tCLK tWHCLK tWLCLK "1" CLK "0" tSDAT tHDAT "1" A INPUT tPHL4
50% 50%
"0" tF DAT
A4, 5, 6
tSTB
tPLH4
tHSTB
tR DAT "1"
STB
50%
50% "0" tSSTB
tPHL2 90% 10% tPLH2
tPHL1 "1" 90% 10% tPLH1 "0"
OUTn
"1" BLK (POC="L") 50% tPHL3 50% "0" tPLH3
OUTn see Figure 3
90% 10% tF OUT 10%
90%
"1"
"0" tR OUT
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STV7620S/M/F
Figure 3. Zoom for OUTn showing tS and tF OUT
tF OUT OUTn 90%
10%
tS
Figure 4. Test configuration
VPP=V SSP VPP=VSSP
VDOUTH
IDOUTH
VDOUTL V SSP VSSP
IDOUTL
Output sinking current as positive value, sourcing current as negative value
11 TESTED WAFER DISCLAIMER
All wafers are tested and guaranteed to comply with all datasheet limits up to the point of wafer sawing for a period of ninety (90) days from the delivery date. We remind you that it is the customer's responsibility to test and qualify their application in which the die is used. ST Microelectronics is ready to support the customer when qualifying the product.
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STV7620S/M/F
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change without notice. This publicati on supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems witho ut the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2002 STMicroelectronics - All Rights Reserved. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http:// www.st.com
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