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S71PL127/129JB0
Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM 128 Megabit (8M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Operation Flash Memory and 32 Megabit (2M x 16-Bit) CMOS Pseudo Static RAM with Page Mode Distinctive Characteristics
MCP Features
Power supply voltage of 2.7 to 3.1 volt High performance -- 70 ns maximum -- 30 ns maximum -- 70 ns maximum -- 30 ns maximum Package -- 64-Ball FBGA -- -25C to +85C access time (Flash) page access time (Flash) access time (PSRAM) page access time (PSRAM) SecSiTM (Secured Silicon) Sector region -- Up to 128 words accessible through a command sequence -- Up to 64 factory-locked words -- Up to 64 customer-lockable words Both top and bottom boot blocks in one device Manufactured on 0.11 m process technology Data retention: 20 years typical Cycling Endurance: 1 million cycles per sector typical
ADVANCE
Operating Temperature
Flash Memory Features
ARCHITECTURAL ADVANTAGES
128 Mbit Page Mode device -- Page size of 8 words: Fast page read access from random locations within the page Single power supply operation -- Full Voltage range: 2.7 to 3.1 volt read, erase, and program operations for battery-powered applications Dual Chip Enable inputs (PL129J) -- Two CE# inputs control selection of each half of the memory space Simultaneous Read/Write Operation -- Data can be continuously read from one bank while executing erase/program functions in another bank -- Zero latency switching from write to read operations FlexBank Architecture -- 4 separate banks, with up to two simultaneous operations per device -- Bank A: 16Mbit (4Kw x 8 and 32Kw x 31) -- Bank B: 48Mbit ( 32Kw x 96) -- Bank C: 48 Mbit (32Kw x 96) -- Bank D: 16Mbit (4Kw x 8 and 32Kw x 31)
SOFTWARE FEATURES
Software command-set compatible with JEDEC 42.4 standard -- Backward compatible with Am29F and Am29LV families CFI (Common Flash Interface) compliant -- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Erase Suspend / Erase Resume -- Suspends an erase operation to allow read or program operations in other sectors of same bank Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences
HARDWARE FEATURES
Ready/Busy# pin (RY/BY#) -- Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) -- Hardware method to reset the device to reading array data WP#/ ACC (Write Protect/Acceleration) input -- At VIL, hardware level protection for the first and last two 4K word sectors. -- At VHH, provides accelerated programming in a factory setting Persistent Sector Protection -- A command sector protection method to lock combinations of individual sectors and sector groups
Publication Number S71PL127/129JB0_00
Revision A
Amendment 0
Issue Date April 15, 2004
Preliminary
to prevent program or erase operations within that sector -- Sectors can be locked and unlocked in-system at VCC level
Password Sector Protection -- A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password
PSRAM Features
Power dissipation -- Operating: 40 mA maximum -- Standby: 135 A maximum CE1#r and CE2r Chip Select Power down features using CE1#r and CE2r Data retention supply voltage: 1.5 to 3.1 volt Byte data control: LB# (DQ0-DQ7), UB#(DQ8- DQ15)
Product Selector Guide
S71PL127JB0BAW9Z# S71PL127JB0BAW9U# S71PL127JB0BAW9P# S71PL127JB0BFW9Z# S71PL127JB0BFW9U# S71PL127JB0BFW9P# S71PL129JB0BAW9Z# S71PL129JB0BAW9U# S71PL129JB0BAW9P# S71PL129JB0BFW9Z# S71PL129JB0BFW9U# S71PL129JB0BFW9P# VCC = 2.7-3.1 V Flash 70 70 30 30 VCC = 2.7-3.1 V PSRAM 70 70 30 40
Part Number Supply Voltage Supply Voltage Max Access Time, ns Max CE# Access, ns Max Page Access, ns Max OE# Access, ns
Note:Both VCCf and VCCr must be the same level when either part is being accessed.
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S71PL127/129JB0
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1 Flash Memory Features ...................................................................................... 1 PSRAM Features ....................................................................................................2
Figure 3. AC Measurement Output Load Circuit...................... 20
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4. Read TIming #1 (Basic Timing).............................. 21 Figure 5. Read Timing #2 (OE# and Address Access) ............. 22
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 6. Read Timing #3 (LB#/UB# Byte Access) ................. 23 Figure 7. Read Timing #4 (Page Access after CE1# Control Access) 24
Product Selector Guide . . . . . . . . . . . 2 Connection Diagram (S71PL127JB0) . . . . . . . . . . . .5
Special Handling Instructions For FBGA Package ...................................5
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. Read Timing #5 (Random and Page Address Access) 25
Input/Output Descriptions (S71PL127JB0) . . . . 6 Absolute Maximum Ratings . . . . . . . . . 10
Figure 1. Maximum Negative Overshoot Waveform ................. 10 Figure 2. Maximum Positive Overshoot Waveform .......................................................... 10
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. Write Timing #1 (Basic Timing).............................. 26 Figure 10. Write Timing #2 (WE# Control)............................ 27
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11. Write Timing #3-1 (WE#/LB#/UB# Byte Write Control) 28 Figure 12. Write Timing #3-2 (WE#/LB#/UB# Byte Write Control) 29
Operating Ranges
. . . . . . . . . . . . . 10
BGA Pin Capacitance .......................................................................................... 11 TLA064--64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package ........................................................................................... 12
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 13. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control) 30 Figure 14. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control) 31
32Mb pSRAM (Supplier 1)
pSRAM Block Diagram . . . . . . . . . . . . . . . . . . . . 14 Function Truth Table . . . . . . . . . . . . . . . . . . . . . . 15 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power Down .....................................................................................................15 Power Down Program Sequence ...............................................................15 Address Key ..................................................................................................... 16
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. Read/Write Timing #1-1 (CE1# Control) ............... 32 Figure 16. Read/Write Timing #1-2 (CE1#/WE#/OE# Control) 33
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. Read/Write Timing #2 (OE#, WE# Control) ........... 34 Figure 18. Read/Write Timing #3 (OE#, WE#, LB#, UB# Control) 35
Recommended Operating Conditions . . . . . . . . 16 pSRAM DC Characteristics . . . . . . . . . . . . . . . . . 17 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 17
Read Operation ....................................................................................................17
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 19. Power-up Timing #1 ........................................... 35 Figure 20. Power-up Timing #2 ........................................... 36
PSRAM AC Characteristics . . . . . . . . . . . . . . . . . 19
Write Operation ................................................................................................. 19
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. Power-down Entry and Exit Timing........................ 36 Figure 22. Standby Entry Timing after Read or Write.............. 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Down Parameters ................................................................................ 20 Other Timing Parameters ............................................................................... 20
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
AC Test Conditions .......................................................................................... 20
Revision Summary
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MCP Block Diagram (S71PL127JB0)
VCCf A22 to A0 A22 to A0 WP#/ACC RESET# CE#f 128 M bit Flash Memory (Single CE) VSS RY/BY#
DQ15 to DQ0
DQ15 to DQ0 VCCr A20 to A0 DQ15 to DQ0 VSS
LB# UB# WE# OE# CE1#r CE2r
32 M bit PSRAM
MCP Block Diagram (S71PL129JB0)
VCCf A21 to A0 A21 to A0 WP#/ACC RESET# CE0#f CE1#f 128 M bit Flash Memory (Dual CE) VSS RY/BY#
DQ15 to DQ0
DQ15 to DQ0 VCCr A20 to A0 DQ15 to DQ0 VSS
LB# UB# WE# OE# CE1#r CE2r
32 M bit PSRAM
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Connection Diagram (S71PL127JB0)
64-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A10 N.C. D9 A15 C8 A11 C7 A8 B6 N.C. B5 N.C. C6 WE# C5 D8 A12 D7 A19 D6 CE2r D5 E9 A21 E8 A13 E7 A9 E6 A20 E5 RY/BY# E4 A18 E3 A5 E2 A2 F4 A17 F3 A4 F2 A1 G4 DQ1 G3 VSS G2 A0 F9 A22 F8 A14 F7 A10 G9 A16 G8 N.C. G7 DQ6 H9 N. C. H8 DQ15 H7 DQ13 H6 DQ4 H5 DQ3 H4 DQ9 H3 OE# H2 CE#f J9 VSS J8 DQ7 J7 DQ12 J6 VCCr J5 VCCf J4 DQ10 J3 DQ0 J2 CE1#r M1 N.C. K8 DQ14 K7 DQ5 K6 N.C. K5 DQ11 K4 DQ2 K3 DQ8 L6 N.C. L5 N.C. M10 N.C.
WP#/ACC RESET# C4 LB# C3 A7 D4 UB# D3 A6 D2 A3
A1 N.C.
Connection Diagram (S71PL129JB0)
64-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A10 N.C. D9 A15 C8 A11 C7 A8 B6 N.C. B5 N.C. C6 WE# C5 D8 A12 D7 A19 D6 CE2r D5 E9 A21 E8 A13 E7 A9 E6 A20 E5 RY/BY# E4 A18 E3 A5 E2 A2 F4 A17 F3 A4 F2 A1 G4 DQ1 G3 VSS G2 A0 F9 CE1#f F8 A14 F7 A10 G9 A16 G8 N.C. G7 DQ6 H9 N. C. H8 DQ15 H7 DQ13 H6 DQ4 H5 DQ3 H4 DQ9 H3 OE# H2 CE0#f J9 VSS J8 DQ7 J7 DQ12 J6 VCCr J5 VCCf J4 DQ10 J3 DQ0 J2 CE1#r K8 DQ14 K7 DQ5 K6 N.C. K5 DQ11 K4 DQ2 K3 DQ8 L6 N.C. L5 N.C.
M10 N.C.
WP#/ACC RESET# C4 LB# C3 A7 D4 UB# D3 A6 D2 A3
A1 N.C.
M1 N.C.
Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
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Input/Output Descriptions (S71PL127JB0)
Pin Name
A19to A0 A22 to A20 DQ15-DQ0 CE#f CE1#r CE2r OE# WE# RY/BY# UB# LB# RESET# WP#/ACC N.C. VSS VCCf VCCr
Input / Output
I I I/O I I I I I O I I I I - Power Power Power Address inputs (Common) Address inputs (Flash) Data input/output Chip Enable (Flash) Chip Enable (PSRAM) Chip Enable (PSRAM Output Enable (Common) Write Enable (Common)
Description
Ready/Busy Output (Flash) Open Drain Output Upper Byte Control Lower Byte Control Hardware Reset Pin / Sector Protection Unlock (Flash) Write Protect / Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (Flash)
Input/Output Descriptions (S71PL129JB0)
Pin Name
A19to A0 A21 to A20 DQ15-DQ0 CE0#f, CE1#f CE1#r CE2r OE# WE# RY/BY# UB# LB# RESET# WP#/ACC N.C. VSS VCCf VCCr
Input / Output
I I I/O I I I I I O I I I I - Power Power Power Address inputs (Common) Address inputs (Flash) Data input/output Chip Enable (Flash) Chip Enable (PSRAM) Chip Enable (PSRAM Output Enable (Common) Write Enable (Common)
Description
Ready/Busy Output (Flash) Open Drain Output Upper Byte Control Lower Byte Control Hardware Reset Pin / Sector Protection Unlock (Flash) Write Protect / Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (Flash)
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Ordering Information
Valid Combinations Order Number S71PL127JB0BAW9Z# S71PL127JB0BAW9U# S71PL127JB0BAW9P# S71PL127JB0BFW9Z# S71PL127JB0BFW9U# S71PL127JB0BFW9P# S29PL127J 70/30 32Mb Flash Flash Initial/Page Speed (ns) pSRAM pSRAM Supplier Supplier 1 Supplier 2 Supplier 3 Supplier 1 Supplier 2 Supplier 3 70/30 Pb-free Pb-free Compliant 8 x 11.6 x 1.2 64 pSRAM Initial/Page Speed (ns) Pb-free Compliant or Pb-free MCP Package Size (mm) Ball Count
S71PL129JB0BAW9Z# S71PL129JB0BAW9U# S71PL129JB0BAW9P# S71PL129JB0BFW9Z# S71PL129JB0BFW9U# S71PL129JB0BFW9P# S29PL129J 70/30 32Mb
Supplier 1 Supplier 2 Supplier 3 Supplier 1 Supplier 2 Supplier 3 70/30 Pb-free Pb-free Compliant 8 x 11.6 x 1.2 64
Notes: 1. # = 0 (Tray), 1 (7" Tape and Reel), or 3 (13" Tape and Reel)
Device Bus Operations (S71PL127B0)
Operation (1), (2)
Full Standby Output Disable Read from Flash (3) Write to Flash
CEf# CE1r# CE2r OE# WE# LB# UB#
H H L L L H L H H H H H H H X H L H X H H L X X X X L X X X X L L H H L L H H X X X X
A22 to A0
X X(6) X Valid Valid
DQ7 to DQ0
High-Z High-Z DOUT DIN DIN
DQ15 to DQ8
High-Z High-Z DOUT DIN DIN DIN High-Z High-Z DIN DIN High-Z High-Z X High-Z X X
WP/ RESET
H H H H
ACC (7)
X X X X
Read from PSRAM
H
L
H
L
H
H L
Valid
High-Z DIN
H
X
PSRAM No Read
H
L
H
L
H
H L
Valid
High-Z DIN
H
X
Write to PSRAM
H
L
H
H(5)
L
H L
Valid
High-Z DIN
H
X
PSRAM No Write Flash Temporary Sector Group Unprotection(4) Flash Hardware Reset Flash Boot Block Sector Write Protection PSRAM Power Down
H X X X X
L X H X X
H X H X L
H(5) X X X X
L X X X X
H X X X X
Valid X X X X
High-Z X High-Z X X
H VID L X X
X X X L X
Legend:Legend: L = VIL, H = VIH, X can be either VIL or VIH, Hihe-Z = High Impedance. See DC Characteristics for voltage levels.
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Note: 1. Other operations except for indicated this column are inhibited. 2. Do not apply for a following state two or more on the same time; 1) CEf# = VIL, 2) CE1r# = VIL and CE2r = VIH, 3. WE# can be VIL if OE# is VIL, OE# at VIH initiates the write operations. 4. It is also used for the extended sector group protections. 5. OE# can be VIL during Write operation if the following conditions are satisfied; 1) Write pulse is initiated by CE1r# (refer to CE1r# Controlled Write timing), or cycle time of the previous operation cycle is satisfied. 2) OE# stays VIL during Write cycle. 6. Can be either VIL or VIH but must be valid before Read or Write. 7. Protect " outer most " 2x8K bytes ( 4 words ) on both ends of the boot block sectors.
Device Bus Operations (S71PL129B0)
Operation (1), (2)
Full Standby
CE0#f CE1#f CE1#r CE2r
H H H H H L H L H L H L H H H H H H H H H H
OE
X
A21 to WE LB# UB# # A0
X X X X X(6)
DQ7 to DQ0
High-Z
DQ15 to RESET # DQ8
High-Z H
WP/ ACC (7)
X
Output Disable
L H
H
H
X
X
X
High-Z
High-Z
H
X
Read from Flash (3)
L H L H
L H H
H L L
X X X L
X X X L L H H L L H H X X X X
Valid Valid Valid
DOUT DIN DIN DIN
DOUT DIN DIN DIN DIN High-Z High-Z DIN DIN High-Z High-Z X High-Z X X
H H H
X X X
Write to Flash
Read from PSRAM
H
H
L
H
L
H
H L
Valid
High-Z DIN
H
X
PSRAM No Read
H
H
L
H
L
H
H L
Valid
High-Z DIN
H
X
Write to PSRAM
H
H
L
H
H(5)
L
H L
Valid
High-Z DIN
H
X
PSRAM No Write Flash Temporary Sector Group Unprotection(4) Flash Hardware Reset Flash Boot Block Sector Write Protection PSRAM Power Down
H X X X X
H X X X X
L X H X X
H X H X L
H(5) X X X X
L X X X X
H X X X X
Valid X X X X
High-Z X High-Z X X
H VID L X X
X X X L X
Legend: L = VIL, H = VIH, X can be either VIL or VIH, Hihe-Z = High Impedance. See DC Characteristics for voltage levels. Note:
1. Other operations except for indicated this column are inhibited. 2. Do not apply for a following state two or more on the same time; 1) CEf# = VIL, 2) CE1r# = VIL and CE2r = VIH, 3. WE# can be VIL if OE# is VIL, OE# at VIH initiates the write operations. 4. It is also used for the extended sector group protections. 5. OE# can be VIL during Write operation if the following conditions are satisfied; 1) Write pulse is initiated by CE1r# (refer to CE1r# Controlled Write timing), or cycle time of the previous
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operation cycle is satisfied. 2) OE# stays VIL during Write cycle. 6. Can be either VIL or VIH but must be valid before Read or Write. 7. Protect " outer most " 2x8K bytes ( 4 words ) on both ends of the boot block sectors.
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Absolute Maximum Ratings
Rating Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except RESET ,WP/ACC *1 VCCf/VCCr Supply *1 RESET *2 WP/ACC *3 Symbol Tstg TA VIN, VOUT VCCf,VCCr VIN VIN Min. -55 -25 -0.3 -0.3 -0.5 -0.5 Max. +125 +85 VCCf +0.3 VCCr +0.3 +3.3 + 13.0 +10.5 Unit C C V V V V V
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 1. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 2. 2. Minimum DC input voltage on pins RESET#, and WP#/ACC is -0.5 V. During voltage transitions, WP#/ACC, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 1. Maximum DC input voltage on pin RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns
20 ns
20 ns
Figure 1. Maximum Negative Overshoot Waveform
Figure 2. Maximum Positive Overshoot Waveform
Operating Ranges
Value Parameter Ambient Temperature VCCf/VCCr Supply Voltages Symbol TA VCCf,VCCr Min. -25 +2.7 Max. +85 +3.1 Unit C V
Note:Operating ranges define those limits between which the functionality of the device is guaranteed.
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DC Characteristics Electrical Characteristics (AC Characteristics)
CE# TIMING
Parameter CE# Recover Time CE# Hold Time CE1#r High to WE Invalid time for Standby Entry Symbol JEDEC -- -- -- Standard tCCR tCHOLD tCHWX Condition -- -- -- Value Min. 0 3 10 Max. -- -- -- Unit ns ns ns
TIMING DIAGRAM FOR ALTERNATING RAM TO FLASH
CE0#f or CE1#f
tCCR
tCCR
CE1#r
WE#
tCHWX tCHOLD
tCCR
tCCR
CE2r
Flash Characteristics
-- Please refer to S29PL127J/S29PL129J specification on the S29PL032J/S29PL064J/S29PL127J/S29PL129J datasheet.
PSRAM Characteristics
-- Please refer to "32Mb pSRAM (Supplier 1)" on page 14.
BGA Pin Capacitance
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ tbd tbd tbd Max tbd tbd tbd Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
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Physical Dimensions
TLA064--64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
D
0.15 C (2X)
10 9 8 7
A
D1 eD
SE
7
E eE
6 5 4 3 2 1 L J H G F E D CB A
E1
INDEX MARK PIN A1 CORNER 10
M
K
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
64X
0.15 0.08
0.20 C
6
SIDE VIEW b
M C AB MC
C
0.08 C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35 TLA 064 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 0.81 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 64 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10, F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3352 \ 16-038.22a
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Preliminary
32Mb pSRAM (Supplier 1)
32Mb (2 M word x 16 bit) CMOS 2,097,152 x 16 BIT pSRAM Block Diagram
VDD VSS
A20 to A0
ADDRESS LATCH & BUFFER
ROW DECODER
MEMORY CELL ARRAY 33,554,432 bit
DQ15 to DQ8 DQ7 to DQ0
INPUT / OUTPUT BUFFER
INPUT DATA LATCH & CONTROL
SENSE / SWITCH
OUTPUT DATA CONTROL
COLUMN / DECODER
ADDRESS LATCH & BUFFER
CE2
POWER CONTROL TIMING CONTROL
CE1 WE LB UB OE
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32Mb pSRAM (Supplier 1)
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Preliminary
Function Truth Table
Mode Standby (Deselect) Output Disable (Note 1) Output Disable (No Read) Read (Upper Byte) Read (Lower Byte) Read (Word) No Write Write (Upper Byte) Write (Lower Byte) Write (Word) Power Down (Note 2) L X X L H (Note 4) H L H L CE2 H CE1# H WE# X H OE# X H LB# X H H H L L H H L L X UB# X X H L H L H L H L X A20-0 X (Note 3) Valid Valid Valid Valid Valid Valid Valid Valid X DQ7-0 High-Z High-Z High-Z High-Z DQ15-8 High-Z High-Z High-Z Output Valid
Output High-Z Valid Output Output Valid Valid Invalid Invalid Invalid Input Valid Input Invalid Valid Input Input Valid Valid High-Z High-Z
Note: 1. Should not be kept this logic condition longer than 1 s. 2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Power Down Program. Refer to Power down for details.
3. Can be either VIL or VIH but must be valid for read or write. 4. OE# can be VIL during Write operation if the following conditions are satisfied; Write pulse is initiated by CE1# (refer to CE1# Controlled Write timing), or cycle time of the previous operation cycle is satisfied, OE stays during Write cycle.
Power Down
Power Down
The Power Down is to enter low power idle state when CE2 stays Low. The pSRAM has two power down modes, Deep Sleep 4M Partial and 8M Partial. These can be programmed by series of read/write operation. See the following table for mode features.
Mode Sleep (default) 4M Partial 8M Partial
Data Retention No 4M bit 8M bit
Retention Address N/A 00000h to 3FFFFh 00000h to 7FFFFh
The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought to Low for Power Down. It is not required to program to Sleep mode after power-up.
Power Down Program Sequence
The program requires total 6 read/write operation with unique address and data. Between each read/write operation requires that device be in standby mode. The following table shows the detail sequence.
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Preliminary
Cycle# 1st 2nd 3rd 4th 5th 6th
Operation Read Write Write Write Write Read
Address 1FFFFFh (MSB) 1FFFFFh 1FFFFFh 1FFFFFh 1FFFFFh Address Key
Data Read Data (RDa) RDa RDa Don't Care (X) X Read Data (RDb)
The first cycle is to read from most significant address (MSB). The second and third cycle are to write back the data (RDa) read by first cycle. If the second or third cycle is written into the different address, the program is cancelled and the data written by the second or third cycle is valid as a normal write operation. The fourth and fifth cycle is to write to MSB. The data of fourth and fifth cycle is don't care. If the fourth or fifth cycle is written into different address, the program is also cancelled but write data may not be wrote as normal write operation. The last cycle is to read from specific address key for mode selection. Once this program sequence is performed from a Partial mode, the write data may be lost. So, it should perform this program prior to regular read/write operation if Partial mode is used.
Address Key
The address key has the following format. Address Mode Sleep (default) 4M Partial 8M Partial A20 1 1 0 A19 1 0 1 A18-A0 1 1 1 Binary 1FFFFFh 17FFFFh 07FFFFh
Recommended Operating Conditions
Parameter Supply Voltage High Level Input Voltage Low Level Input Voltage Ambient Temperature
Notes:
1. Maximum DC voltage on input and I/O pins are VDD + 0.2 V. During voltage transitions, inputs may positive overshoot to VDD + 1.0 V for periods of up to 5 ns. 2. Minimum DC voltage on input or I/O pins are -0.3 V. During voltage transitions, inputs may negative overshoot VSS to -1.0 V for periods of up to 5 ns.
Symbol VDD VSS VIH VIH VIL TA
Min. 2.7 0 0.8 VDD 0.8 VDD -0.3 -25
Max. 3.1 0 VDD + 0.2 and +3.6 VDD + 0.2 0.2 VDD 85
Unit V V V V V
C
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Preliminary
pSRAM DC Characteristics
Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level VDD Power Down Current Symbol ILI ILO VOH VOL IDDPS IDDP8 IDDS IDDS1 IDDA1 IDDA2 IDDA3 Test Conditions VIN = VSS to VDD VOUT = VSS to VDD, Output Disable VDD = VDD(min), IOH = -0.5mA IOL = 1 mA VDD = VDD max., VIN = VIH or VIL, CE2 0.2V SLEEP 8M Partial Min. -1.0 -1.0 2.4 - - - - - - - - Max. +1.0 +1.0 - 0.4 10 50 1.5 80 30 3 10 Unit A A V V A A mA A mA mA mA
VDD Standby Current
VDD = VDD max., VIN = VIH or VIL, CE1# VDD = VDD max., VIN 0.2 V or VIN VDD - 0.2 V, CE1# =CE2 VDD - 0.2V VDD = VDD max., VIN = VIH or VIL, CE1# = VIL and CE2 = VIH, IOUT = 0 mA tRC/tWC = minimum tRC/tWC = 1 s
VDD Active Current VDD Page Read Current
VDD = VDD max., VIN = VIH or VIL, CE1# = VIL and CE2 = VIH, IOUT = 0 mA, tPRC = min.
Notes: 1. All voltages are referenced to VSS.
2. DC Characteristics are measured after following POWER-UP timing. 3. IOUT depends on the output load conditions.
pSRAM AC Characteristics
Read Operation
Value Min. 65 - - - - - 25 5 5 0 0 - -
Parameter Read Cycle Time (Notes 1, 2) CE1# Access Time (Note 3) OE# Access Time (Note 3) Address Access Time (Notes 3,5) LB#/UB# Access Time (Note 3) Page Address Access Time (Notes 3,6) Page Read Cycle Time (Notes 1,6,7) Output Data Hold Time (Note 3) CE1# Low to Output Low-Z (Note 4) OE# Low to Output Low-Z (Note 4) LB#/UB# Low to Output High-Z (Note 4) CE1# High to Output High-Z (Note 3) OE# High to Output High-Z (Note 3)
Symbol tRC tCE tOE tAA tBA tPAA tPRC tOH tCLZ tOLZ tBLZ tCHZ tOHZ
Max. 1000 65 40 65 30 20 1000 - - - - 20 20
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
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Parameter LB#/UB# High to Output High-Z (Note 3) Address Setup Time to CE1# Low Address Setup Time to OE# Low Address Invalid Time (Notes 5,8) Address Hold Time from CE1# High (Note 9) Address Hold Time from OE# High CE1# High Pulse Width
Symbol tBHZ tASC tASO tAX tCHAH tOHAH tCP
Value Min. Max. - 20 -5 - 10 - - -5 - -5 - 12 -
Unit ns ns ns ns ns ns ns
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Preliminary
Notes: 1. Maximum value is applicable if CE1# is kept at Low without change of address input of A3 to A20.
2. Address should not be changed within minimum tRC. 3. The output load 50pF. 4. The output load 5pF. 5. Applicable to A3 to A20 when CE1# is kept at Low. 6. Applicable only to A0, A1 and A2 when CE1# is kept at Low for the page address access. 7. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4 s. In other words, Page Read Cycle must be closed within 4 s. 8. Applicable when at least two of address inputs among applicable are switched from previous state. 9. tRC (min) and tPRC (min) must be satisfied.
PSRAM AC Characteristics
Write Operation
Parameter Write Cycle Time (Notes 1, 2) Address Setup Time (Note 3) CE1# Write Pulse Width (Note 3) WE# Write Pulse Width (Note 3) LB#/UB# Write Pulse Width (Note 3) LB#/UB# Byte Mask Setup Time (Note 4) LB#/UB# Byte Mask Hold Time (Note 5) CE1# Write Recovery Time (Note 6) WE# Write Recovery Time (Note 6) LB#/UB# Write Recovery Time (Note 6) Data Setup Time Data Hold Time OE# High to CE1# Low Setup Time for Write (Note 7) OE# High to Address Setup Time for Write (Note 8) WE#/UB#/LB# High to OE# Low Setup Time for Read (Note 10) LB# and UB# Write Pulse Overlap CE1# High Pulse Width Address Hold Time for Write End (Note (Note 3) Symbol tWC tAS tCW tWP tBW tBS tBH tWRC tWR tBR tDS tDH tOHCL tOES tWHOL tBWO tCP tAH Value Min. 65 0 40 40 40 -5 -5 12 7.5 12 12 0 -5 0 12 30 12 0 Max. 1000 - - - - - - - 1000 1000 - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 ns ns ns
Notes: 1. Maximum value is applicable if CE1# is kept at Low without any address change.
2. Minimum value must be equal or greater than the sum of write pulse (tCW, TWP, TBW) and write recovery time (tWCR, TWR or tBR). 3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last. 4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever occurs last. 5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever occurs first. 6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first. 7. If OE# is Low after minimum tOHCL, read cycle is initiated. In other words, OE# must be brought to High within 5 ns after CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met 8. If OE# is Low after new address input, read cycle is initiated. In other words, OE# must be brought to High at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input
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Preliminary
after minimum tRC is met and data bus is in High-Z 9. Absolute minimum values and defined at minimum VIH level. 10.If the actual value of tWHOL is shorter than the specified minimum values, the actual tAA of following Read may become longer by the amount of subtracting the actual value from the specified minimum value.
AC Characteristics
Power Down Parameters
Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1# High Hold Time following CE2 High after Power Down Exit (SLEEP mode only) (Note 1) CE1# High Hold Time following CE2 High after Power Down Exit (not in SLEEP mode) (Note 2) CE1# High Setup Time following CE2 High after Power Down Exit (Note 1)
Notes: 1. Applicable also to power up.
Symbol tCSP tC2LP tCHH tCHHP tCHS
Value Min. Max. 10 - 65 - 300 1 0 - - -
Unit ns ns
s s
ns
2. Applicable when 8M Partial mode is programmed.
Other Timing Parameters
Parameter CE#1 High to OE# Invalid Time for Standby Entry CE#1 High to WE# Invalid Time for Standby Entry (Note 1) CE2 Low Hold Time after Power up CE1# High Hold Time following CE2 High after Power up Input Transition Time (Note 2) Symbol tCHOX tCHWX tC2LH tCHH tT Value Min. Max. 10 10 50 - 300 - 1 25 Unit ns ns
s s
ns
Notes: 1. Some data might be written into any address location if tCHWX (min) is not satisfied
2. The Input Transition Time (tT) at AC testing is 5ns, as shown in AC Test Conditions below.. If actual tT is longer than 5ns, it may violate AC specification of some timing parameters.
AC Characteristics
AC Test Conditions
Symbol VIH VIL VREF tT Description Input High Level Input Low Level Input Timing Measurement Level Input Transition Time
VDD 0.1 F VSS DEVICE UNDER TEST 50pF OUT
Test Setup
Between VIL and VIH
15, 11 VDD * 0.8 VDD * 0.2 VDD * 0.5 5
Unit V V V ns
Figure 3. April 7, 2004 S71PL127/129JB0_00A0
AC Measurement Output Load Circuit 32Mb pSRAM (Supplier 1) 20
Preliminary
Timing Diagrams
tRC ADDRESS tASC CE1# tOE OE# tOHZ tBA LB / UB# tBLZ tOLZ DQ (Output) tCLZ tOH tBHZ ADDRESS VALID tCHAH tASC
tCE
tCP tCHZ
VALID DATA OUTPUT
Note: CE2 and WE# must be High for entire read cycle.
Figure 4.
Read TIming #1 (Basic Timing)
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Preliminary
tRC ADDRESS ADDRESS VALID tAA CE1#
tAx
tRC ADDRESS VALID tAA tOHAH
Low
tASO OE#
tOE
LB / UB# tOHZ tOLZ DQ (Output) VALID DATA OUTPUT VALID DATA OUTPUT tOH tOH
Note: CE2 and WE# must be High for entire read cycle.
Figure 5.
Read Timing #2 (OE# and Address Access)
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Preliminary
Timing Diagrams
tAX ADDRESS tAA CE1#,OE# tRC ADDRESS VALID tAx
Low tBA
tBA LB#
tBA UB# tBHZ tBLZ DQ0-DQ7 (Output) VALID DATA OUTPUT DQ8-DQ15 (Output) VALID DATA OUTPUT VALID DATA OUTPUT tBLZ tBHZ tOH tOH tBLZ tBHZ tOH
Note: CE2 and WE# must be High for entire read cycle.
Figure 6.
Read Timing #3 (LB#/UB# Byte Access)
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Preliminary
tRC ADDRESS (A20-A3) tRC ADDRESS (A2-A0) tASC CE1# tCE tCHZ ADDRESS VALID ADDRESS VALID tPRC
ADDRESS VALID
tPRC
ADDRESS VALID
tPRC
ADDRESS VALID
tPAA
tPAA
tPAA
tCHAH
OE#
LB# / UB# tOH tOH tOH tOH
tCLZ DQ (Output)
VALID DATA OUTPUT (Normal Access)
VALID DATA OUTPUT (Page Access)
Note:CE2 and WE# must be High for entire read cycle.
Figure 7.
Read Timing #4 (Page Access after CE1# Control Access)
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Preliminary
Timing Diagrams
tRC ADDRESS (A20-A3) ADDRESS VALID tRC ADDRESS (A2-A0)
ADDRESS VALID
tAX
tRC ADDRESS VALID
tAx
tPRC
ADDRESS VALID
tRC
ADDRESS VALID
tPRC
ADDRESS VALID
tAA CE1#
tPAA
tAA
tPAA
Low tASO tOE
OE#
tBA LB# / UB# tOLZ tBLZ tOH tOH tOH tOH
DQ (Output)
VALID DATA OUTPUT (Normal Access)
CE1# and OE# are Low.
VALID DATA OUTPUT (Page Access)
Note: CE2 and WE# must be High for entire read cycle. Either or both LB# and UB# must be Low when both
Figure 8.
Read Timing #5 (Random and Page Address Access)
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32Mb pSRAM (Supplier 1)
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Preliminary
Timing Diagrams
tWC ADDRESS tAS CE1# tAS WE# tAS LB #, UB# tOHCL OE# tDS DQ (Input) VALID DATA INPUT tDH tBR tAS tWR tAS tBW ADDRESS VALID tAH tAS
tCW
tWP
Note: CE2 must be High for Write Cycle.
Figure 9.
Write Timing #1 (Basic Timing)
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Preliminary
tWC ADDRESS ADDRESS VALID
tWC ADDRESS VALID
tOHAH CE1# Low tAS WE# tWR tWP tAH tAS tWP tWR
LB#, UB# tOES OE# tOHZ DQ (Input) VALID DATA INPUT VALID DATA INPUT tDS tDH tDS tDH
Note: CE2 must be High for Write Cycle.
Figure 10.
Write Timing #2 (WE# Control)
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Preliminary
Timing Diagrams
tWC ADDRESS ADDRESS VALID tWC ADDRESS VALID
CE1#
Low tWR tWR
WE# tAS LB# tBS UB# tDS DQ0-DQ8 (Input) VALID DATA INPUT DQ8-DQ15 (Input) VALID DATA INPUT tDS tDH tDH tBH tAS tBW tBW tBS tBH
Note: CE2 must be High for Write Cycle.
Figure 11.
Write Timing #3-1 (WE#/LB#/UB# Byte Write Control)
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Preliminary
tWC ADDRESS ADDRESS VALID
tWC ADDRESS VALID
CE1#
Low t WR tWR
WE# tAS LB# tBS UB# tDS DQ0-DQ7 (Input) VALID DATA INPUT DQ8-DQ15 (Input) VALID DATA INPUT tDS tDH tDH tBH tAS tBW tBW tBS tBH
Note: CE2 must be High for Write Cycle.
Figure 12.
Write Timing #3-2 (WE#/LB#/UB# Byte Write Control)
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Preliminary
Timing Diagrams
tWC ADDRESS ADDRESS VALID tWC ADDRESS VALID
CE1#
Low
WE# tAS LB# tBS UB# tDS DQ0-DQ7 (Input) VALID DATA INPUT DQ8-DQ15 (Input) VALID DATA INPUT tDS tDH tDH tBH tAS tBW tBR tBW tBR tBS tBH
Note: CE2 must be High for Write Cycle.
Figure 13.
Write Timing #3-3 (WE#/LB#/UB# Byte Write Control)
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Preliminary
tWC ADDRESS ADDRESS VALID
tWC ADDRESS VALID
CE1#
Low
WE# tAS LB# tBWO tDS DQ0-DQ7 (Input) tAS UB# tDS DQ8-DQ15 (Input) tDH tDS tDH tDH tDS tDH tBW tBR tAS tBW tBR
VALID DATA INPUT
VALID DATA INPUT
tBW
tBR
tAS
tBWO tBW
tBR
VALID DATA INPUT
VALID DATA INPUT
Note: CE2 must be High for Write Cycle.
Figure 14.
Write Timing #3-4 (WE#/LB#/UB# Byte Write Control)
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Preliminary
Timing Diagrams
tWC ADDRESS tCHAH CE1# tCP tCP tAS WRITE ADDRESS tWRC tCW tASC tRC READ ADDRESS tCHAH
tCE
WE#
UB#,LB# tOHCL OE# tCHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT tDS tDH tCLZ tOH
Note: Write address is valid from either CE1# or WE# of last falling edge.
Figure 15. Read/Write Timing #1-1 (CE1# Control)
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Preliminary
tWC ADDRESS tCHAH CE1# tCP tWP WE# tCP tAS WRITE ADDRESS tWR tASC
tRC READ ADDRESS tCHAH
tCE
UB#,LB# tOHCL OE# tCHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH tOLZ tOH
tOE
Note: OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read sequence.
Figure 16.
Read/Write Timing #1-2 (CE1#/WE#/OE# Control)
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Timing Diagrams
tWC ADDRESS WRITE ADDRESS tRC READ ADDRESS tAA tOHAH CE1# Low tAS WE# tOES tWP tWR tOHAH
UB#,LB#
tASO OE# tOHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT tDS tDH tOLZ
tOE
tOHZ tOH
READ DATA OUTPUT
Note: CE1# can be tied to Low for WE# and OE# controlled operation.
Figure 17.
Read/Write Timing #2 (OE#, WE# Control)
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Preliminary
tWC ADDRESS WRITE ADDRESS
tRC READ ADDRESS tAA
tOHAH CE1# Low
tOHAH
WE# tOES UB#,LB# tBHZ OE# tBHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH tBLZ tOH tASO tAS tBW tBR
tBA
Note: CE#1 can be tied to Low for WE# and OE# controlled operation.
Figure 18.
Read/Write Timing #3 (OE#, WE#, LB#, UB# Control)
Timing Diagrams
CE1# tCHS tC2LH CE2 tCHH
VDD
0V
VDD min
Note: The tC2LH specifies after VDD reaches specified minimum level.
Figure 19.
Power-up Timing #1
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32Mb pSRAM (Supplier 1)
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Preliminary
CE1# tCHH CE2
VDD
0V
VDD min
Note: The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1# and CE2.
Figure 20.
Power-up Timing #2
Timing Diagrams
CE1# tCHS CE2 tCSP DQ Power Down Entry tC2LP High-Z Power Down Mode Power Down Exit tCHH (tCHHP)
Note: This Power Down mode can be also used as a reset timing if Power-up timing above could not be satisfied and Power-Down program was not performed prior to this reset.
Figure 21.
Power-down Entry and Exit Timing
CE1# tCHOX OE# tCHWX
WE# Active (Read) Standby Active (Write) Standby
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (min) period for standby mode from CE1# Low to High transition.
Figure 22.
Standby Entry Timing after Read or Write
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Preliminary
Timing Diagrams
tRC ADDRESS MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tRC Key*2
tCP CE1#
tCP
tCP
tCP
tCP
tCP*3
OE#
WE#
LB#,UB#
DQ*3
RDa Cycle #1
RDa Cycle #2
RDa Cycle #3
X Cycle #4
X Cycle #5
RDb Cycle #6
Notes:
1. The all address inputs must be High from Cycle #1 to #5. 2. After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation.
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Preliminary
Revision Summary
Revision A (April 15, 2004)
Initial release.
Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided ias isi without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. FASL LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2004 FASL LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
April 15, 2004 S71PL127/129JB0_00A0
Revision Summary
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