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HUF75229P3
Data Sheet December 2001
44A, 50V, 0.022 Ohm, N-Channel UltraFET Power MOSFET
This N-Channel power MOSFET is manufactured using the innovative UltraFET(R) process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products.
Features
* 44A, 50V * Low On-Resistance, rDS(ON) = 0.022 * Temperature Compensating PSPICE(R) Model * Thermal Impedance SPICE Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
D
Ordering Information
PART NUMBER HUF75229P3 PACKAGE TO-220AB BRAND 75229P
G
NOTE: When ordering use the entire part number.
S
Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE)
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html For severe environments, see our Automotive HUFA series. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2001 Fairchild Semiconductor Corporation
HUF75229P3 Rev. B
HUF75229P3
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified UNITS Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 50 50 20 44 Figure 5 Figure 6, 14, 15 90 0.6 -55 to 175 300 260 W W/oC
oC oC oC
V V V A
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V (Figure 11) VGS = VDS, ID = 250A (Figure 10) VDS = 45V, VGS = 0V VDS = 40V, VGS = 0V, TC = 150oC VGS = 20V ID = 44A, VGS = 10V (Figure 9) VDD = 30V, ID 44A, RL = 0.68, VGS = 10V, RGS = 9.1 (Figures 18, 19) MIN 50 2 0.017 VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 30V, ID 44A, RL = 0.68 Ig(REF) = 1.0mA (Figures 13, 16, 17) (Figure 3) TO-220 TYP 0.020 12 58 33 33 60 35 2.0 1060 405 95 MAX 4 1 250 100 0.022 105 100 75 43 2.5 1.66 62 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RJC RJA
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD trr QRR ISD = 44A ISD = 44A, dISD/dt = 100A/s ISD = 44A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 72 120 UNITS V ns nC
(c)2001 Fairchild Semiconductor Corporation
HUF75229P3 Rev. B
HUF75229P3 Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) ID, DRAIN CURRENT (A) 40 50
30
20
10
0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM
0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101
SINGLE PULSE 0.01 10-5 10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200 100 ID, DRAIN CURRENT (A)
400 TJ = MAX RATED TC = 25oC IDM, PEAK CURRENT (A)
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I
= I25
175 - TC 150
100s
10
1ms
100
VGS = 10V
10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) BVDSS MAX = 50V 1 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 200
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 40 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
(c)2001 Fairchild Semiconductor Corporation
HUF75229P3 Rev. B
HUF75229P3 Typical Performance Curves
300 IAS, AVALANCHE CURRENT (A)
(Continued)
100
ID, DRAIN CURRENT (A)
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
80
VGS = 20V VGS = 10V VGS = 8V VGS = 7V
100
VGS = 6V
60
STARTING TJ = 25oC
40 VGS = 5V 20 PULSE DURATION = 250s TC = 25oC 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5
STARTING TJ = 150oC 10 0.001
0.01 0.1 1 tAV, TIME IN AVALANCHE (ms)
10
0
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
100
2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE TEST PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX -55oC 175oC PULSE DURATION = 250s, VGS = 10V, ID = 44A
ID, DRAIN CURRENT (A)
80
2.0
60
1.5
40
1.0
20 25oC 0 VDD = 15V 7.5
0
1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V)
0.5 -80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE
1.2 ID = 250A 1.1
1.0
0.8
1.0
0.6
0.9
0.4 -80
-40
0
40
80
120
160
200
0.8 -80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
(c)2001 Fairchild Semiconductor Corporation
HUF75229P3 Rev. B
HUF75229P3 Typical Performance Curves
1500 VGS , GATE TO SOURCE VOLTAGE (V) VGS = 0V, f = 1MHz 1200 C, CAPACITANCE (pF) CISS 900
(Continued)
10 VDD = 30V
8
6
600 COSS 300 CRSS 0 0 10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V) 50
4 WAVEFORMS IN DESCENDING ORDER: ID = 44A ID = 27A ID = 11A 0 5 10 15 20 25 Qg, GATE CHARGE (nC) 30 35
2
0
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
(c)2001 Fairchild Semiconductor Corporation
HUF75229P3 Rev. B
HUF75229P3 Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V
DUT IG(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
(c)2001 Fairchild Semiconductor Corporation
HUF75229P3 Rev. B
HUF75229P3 PSPICE Electrical Model
SUBCKT HUF75229P3 2 1 3 ;
CA 12 8 1.72e-9 CB 15 14 1.52e-9 CIN 6 8 9.61e-10
10
rev 6/19/97
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + EBREAK MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 17 18 DBODY DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
EBREAK 11 7 17 18 58.13 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.86e-9 LSOURCE 3 7 2.69e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD
GATE 1
ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
RLGATE
RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1e-3 RGATE 9 20 1.52 RLDRAIN 2 5 10 RLGATE 1 9 26.9 RLSOURCE 3 7 28.6 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 13.85e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*135),3.5))} .MODEL DBODYMOD D (IS = 7.50e-13 RS = 5.05e-3 TRS1 = 2.21e-3 TRS2 = 1.02e-6 CJO = 1.51e-9 TT = 4.05e-8 M = 0.5) .MODEL DBREAKMOD D (RS = 2.14e- 1TRS1 = 9.62e- 4TRS2 = 1.23e-6) .MODEL DPLCAPMOD D (CJO = 13.5e-1 0IS = 1e-3 0N = 10 M = 0.85) .MODEL MMEDMOD NMOS (VTO = 3.25 KP = 2.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.52) .MODEL MSTROMOD NMOS (VTO = 3.80 KP = 70.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.91 KP = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 15.2 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.05e- 3TC2 = 1.94e-7) .MODEL RDRAINMOD RES (TC1 = 8.04e-2 TC2 = 1.37e-4) .MODEL RSLCMOD RES (TC1 = 4.83e-3 TC2 = 1.16e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC = -3.43e-3 TC2 = -1.63e-5) .MODEL RVTEMPMOD RES (TC1 = -1.35e- 3TC2 = 1.16e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -7.90 VOFF= -4.90) VON = -4.90 VOFF= -7.90) VON = -0.50 VOFF= 2.50) VON = 2.50 VOFF= -0.50)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2001 Fairchild Semiconductor Corporation
+
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
-
RDRAIN 21 16
-
VBAT +
8 22 RVTHRES
HUF75229P3 Rev. B
HUF75229P3 SPICE Thermal Model
REV 16 June 97 HUF75229P3 CTHERM1 7 6 4.90e-7 CTHERM2 6 5 4.90e-4 CTHERM3 5 4 1.96e-3 CTHERM4 4 3 7.90e-3 CTHERM5 3 2 1.85e-1 CTHERM6 2 1 2.70 RTHERM1 7 6 1.10e-2 RTHERM2 6 5 3.30e-2 RTHERM3 5 4 1.64e-1 RTHERM4 4 3 7.90e-1 RTHERM5 3 2 3.60e-1 RTHERM6 2 1 1.60e-1
RTHERM1 CTHERM1 7 JUNCTION
6
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
1
CASE
(c)2001 Fairchild Semiconductor Corporation
HUF75229P3 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM
DISCLAIMER
FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM
OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R)
SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R)
VCXTM
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4

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