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0.5 CMOS 1.65 V TO 3.6 V Dual SPDT/2:1 MUX ADG836
FEATURES 0.5 Typical On Resistance 0.8 Maximum On Resistance at 125C 1.65 V to 3.6 V Operation Automotive Temperature Range: -40C to +125C High Current Carrying Capability: 300 mA Continuous Rail-to-Rail Switching Operation Fast Switching Times <20 ns Typical Power Consumption (<0.1 W) APPLICATIONS Cellular Phones PDAs MP3 Players Power Routing Battery-Powered Systems PCMCIA Cards Modems Audio and Video Signal Routing Communication Systems GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS
The ADG836 is a low voltage CMOS device containing two independently selectable single-pole, double-throw (SPDT) switches. This device offers ultralow on resistance of less than 0.8 over the full temperature range. The ADG836 is fully specified for 3.3 V, 2.5 V, and 1.8 V supply operation. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The ADG836 exhibits break-before-make switching action. The ADG836 is available in 10-lead MSOP and 3 mm 3 mm 12-lead LFCSP packages.
1. <0.8 over full temperature range of -40C to +125C. 2. Single 1.65 V to 3.6 V operation. 3. Compatible with 1.8 V CMOS logic. 4. High current handling capability (300 mA continuous current at 3.3 V). 5. Low THD + N (0.02% typ). 6. 3 mm 3 mm LFCSP package and 10-lead MSOP package.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADG836-SPECIFICATIONS1(V
Parameter
ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) On Resistance Flatness (RFLAT (ON)) LEAKAGE CURRENTS Source Off Leakage IS (OFF) Channel On Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS tON tOFF Break-before-Make Time Delay (tBBM) Charge Injection Off Isolation Channel-to-Channel Crosstalk
2
DD
= 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.)
-40C to +125C
0 V to VDD
+25C
-40C to +85C
Unit
V
Test Conditions/Comments
VDD = 2.7 V VDD = 2.7 V, VS = 0 V to VDD, IS = 10 mA; Test Circuit 1 VDD = 2.7 V, VS = 0.65 V, IS = 10 mA VDD = 2.7 V, VS = 0 V to VDD, IS = 10 mA VDD = 3.6 V VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V; Test Circuit 2 VS = VD = 0.6 V or 3.3 V; Test Circuit 3
0.5 0.65 0.04 0.1
0.75 0.075 0.15
0.8 0.08 0.16
typ max typ max typ max
nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ
0.2 1 0.2 1
10 15
100 120 2 0.8
0.005 0.1 4 21 26 4 7 17 40 -67 -90
VIN = VINL or VINH
28 8
29 9 5
-67
dB typ
Total Harmonic Distortion (THD + N) Insertion Loss -3 dB Bandwidth CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD
0.02 -0.05 57 25 75 0.003 1 4
% dB typ MHz typ pF typ pF typ A typ A max
RL = 50 , CL = 35 pF VS = 1.5 V/0 V; Test Circuit 4 RL = 50 , CL = 35 pF VS = 1.5 V; Test Circuit 4 RL = 50 , CL = 35 pF VS1 = VS2 = 1.5 V; Test Circuit 5 VS = 1.5 V, RS = 0 , CL = 1 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 7 S1A-S2A/S1B-S2B; RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 10 S1A-S1B/S2A-S2B; RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 9 RL = 32 , f = 20 Hz to 20 kHz, VS = 2 V p-p RL = 50 , CL = 5 pF; Test Circuit 8 RL = 50 , CL = 5 pF; Test Circuit 8
VDD = 3.6 V Digital Inputs = 0 V or 3.6 V
NOTES 1 Temperature range is as follows: Y version: -40C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
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ADG836
SPECIFICATIONS1 (V
Parameter
ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) On Resistance Flatness (RFLAT (ON)) LEAKAGE CURRENTS Source Off Leakage IS (OFF) Channel On Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS tON tOFF Break-before-Make Time Delay (tBBM) Charge Injection Off Isolation Channel-to-Channel Crosstalk
2
DD
= 2.5 V 0.2 V, GND = 0 V, unless otherwise noted.)
+25C -40C to +85C -40C to +125C
0 V to VDD 0.8 0.08 0.16 0.23 0.2 0.4 0.2 0.6 0.24 0.88 0.085
Unit
V
Test Conditions/Comments
0.65 0.72 0.04
typ max typ max typ max
nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ
VDD = 2.3 V, VS = 0 V to VDD, IS = 10 mA; Test Circuit 1 VDD = 2.3 V, VS = 0.7 V; IS = 10 mA VDD = 2.3 V, VS = 0 V to VDD, IS = 10 mA VDD = 2.7 V VS = 0.6 V/2.4 V, VD = 2.4 V/0.6 V; Test Circuit 2 VS = VD = 0.6 V or 2.4 V; Test Circuit 3
4 12
45 90 1.7 0.7
0.005 0.1 4 23 29 5 7 17 30 -67 -90
VIN = VINL or VINH
30 8
31 9 5
-67
dB typ
Total Harmonic Distortion (THD + N) Insertion Loss -3 dB Bandwidth CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD
0.022 -0.06 57 25 75 0.003 1.0 4.0
% dB typ MHz typ pF typ pF typ A typ A max
RL = 50 , CL = 35 pF VS = 1.5 V/0 V; Test Circuit 4 RL = 50 , CL = 35 pF VS = 1.5 V; Test Circuit 4 RL = 50 , CL = 35 pF VS1 = VS2 = 1.5 V; Test Circuit 5 VS = 1.25 V, RS = 0 , CL = 1 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 7 S1A-S2A/S1B-S2B; RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 10 S1A-S1B/S2A-S2B; RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 9 RL = 32 , f = 20 Hz to 20 kHz, VS = 1.5 V p-p RL = 50 , CL = 5 pF; Test Circuit 8 RL = 50 , CL = 5 pF; Test Circuit 8
VDD = 2.7 V Digital Inputs = 0 V or 2.7 V
NOTES 1 Temperature range is as follows: Y version: -40C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
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ADG836
SPECIFICATIONS1(V
Parameter
ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) LEAKAGE CURRENTS Source Off Leakage IS (OFF) Channel On Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS2 tON tOFF Break-before-Make Time Delay (tBBM) Charge Injection Off Isolation Channel-to-Channel Crosstalk
DD
= 1.65 V to 1.95 V, GND = 0 V, unless otherwise noted.)
+25C -40C to +85C -40C to +125C
0 V to VDD 2.2 4 2.2 4
Unit
V
Test Conditions/Comments
1 1.4 2 0.1
typ max max typ
VDD = 1.8 V, VS = 0 V to VDD, IS = 10 mA; Test Circuit 1 VDD = 1.65 V, VS = 0 V to VDD, IS = 10 mA VDD = 1.65 V, VS = 0.7 V, IS = 10 mA VDD = 1.95 V VS = 0.6 V/1.65 V, VD = 1.65 V/0.6 V; Test Circuit 2 VS = VD = 0.6 V or 1.65 V; Test Circuit 3
0.2 0.4 0.2 0.6
4 10
25 75 0.65 VDD 0.35 VDD
nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ
0.005 0.1 4 28 37 7 9 21 20 -67 -90
VIN = VINL or VINH
38 10
39 11 5
-67
dB typ
Total Harmonic Distortion, THD Insertion Loss -3 dB Bandwidth CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD
0.14 -0.08 57 25 75 0.003 1.0 4
% dB typ MHz typ pF typ pF typ A typ A max
RL = 50 , CL = 35 pF VS = 1.5 V/0 V; Test Circuit 4 RL = 50 , CL = 35 pF VS = 1.5 V/0 V; Test Circuit 4 RL = 50 , CL = 35 pF VS1 = VS2 = 1 V; Test Circuit 5 VS = 1 V, RS = 0 , CL = 1 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 7 S1A-S2A/S1B-S2B; RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 10 S1A-S1B/S2A-S2B; RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 9 RL = 32 , f = 20 Hz to 20 kHz, VS = 1.2 V p-p RL = 50 , CL = 5 pF; Test Circuit 8 RL = 50 , CL = 5 pF; Test Circuit 8
VDD = 1.95 V Digital Inputs = 0 V or 1.95 V
NOTES 1 Temperature range is as follows: Y version: -40C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
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ADG836
ABSOLUTE MAXIMUM RATINGS1
(TA = 25C, unless otherwise noted.)
Table I. ADG836 Truth Table
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +4.6 V Analog Inputs2 . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Digital Inputs2 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.6 V or 10 mA, Whichever Occurs First Peak Current, S or D 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA 2.5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 mA 1.8 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 mA (Pulsed at 1ms, 10% Duty Cycle Max) Continuous Current, S or D 3.3 V Operation 300 mA 2.5 V Operation 275 mA 1.8 V Operation 250 mA Operating Temperature Range Automotive (Y Version) . . . . . . . . . . . . . . . . -40C to +125C Storage Temperature Range . . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .150C MSOP Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 206C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 44C/W LFCSP Package JA Thermal Impedance (3-Layer Board) . . . . . . . . . 61.1C/W IR Reflow, Peak Temperature <20 sec . . . . . . . . . . . . . . . .235C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be limited to the maximum ratings given.
Logic 0 1
Switch A Off On
Switch B On Off
ORDERING GUIDE
Model ADG836YRM ADG836YRM-REEL ADG836YRM-REEL7 ADG836YCP ADG836YCP-REEL ADG836YCP-REEL7
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description Mini Small Outline Package (MSOP) Mini Small Outline Package (MSOP) Mini Small Outline Package (MSOP) Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP)
Package Option RM-10 RM-10 RM-10 CP-12 CP-12 CP-12
Branding* S9A S9A S9A S9A S9A S9A
*Branding on this package is limited to three characters due to space constraints.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG836 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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ADG836
PIN CONFIGURATIONS 10-Lead MSOP (RM-10)

12-Lead LFCSP (CP-12)

TERMINOLOGY
VDD IDD GND S D IN VD (VS) RON RFLAT (ON) RON IS (OFF) ID (OFF) ID, IS (ON) VINL VINH IINL (IINH) CS (OFF) CD (OFF) CD, CS (ON) CIN tON tOFF tBBM Charge Injection Off Isolation Crosstalk -3 dB Bandwidth On Response Insertion Loss THD + N
Most positive power supply potential. Positive supply current. Ground (0 V) reference. Source terminal. May be an input or output. Drain terminal. May be an input or output. Logic control input. Analog voltage on terminals D, S. Ohmic resistance between D and S. Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. On resistance match between any two channels. Source leakage current with the switch off. Drain leakage current with the switch off. Channel leakage current with the switch on. Maximum input voltage for Logic 0. Minimum input voltage for Logic 1. Input current of the digital input. Off switch source capacitance. Measured with reference to ground. Off switch drain capacitance. Measured with reference to ground. On switch capacitance. Measured with reference to ground. Digital input capacitance. Delay time between the 50% and the 90% points of the digital input and switch on condition. Delay time between the 50% and the 90% points of the digital input and switch off condition. On or off time measured between the 80% points of both switches when switching from one to another. A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching. A measure of unwanted signal coupling through an off switch. A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. The frequency at which the output is attenuated by 3 dB. The frequency response of the on switch. The loss due to the on resistance of the switch. The ratio of the harmonics amplitude plus noise of a signal, to the fundamental. -6- REV. 0
Typical Performance Characteristics-ADG836
0.60 TA = 25C 0.55 0.50 ON RESISTANCE () 0.45 0.40 0.35 0.30 0.25 0.20 0.2 VDD = 3.6V VDD = 3.3V VDD = 3V VDD = 2.7V ON RESISTANCE () 1.0 1.2 VDD = 3.3V
0.8 +125C +85C
0.6
0.4 +25C -40C
0
0.5
1.0
1.5
2.0 VD, VS (V)
2.5
3.0
3.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
VD, VS (V)
TPC 1. On Resistance vs. VD (VS) VDD = 2.7 V to 3.6 V
TPC 4. On Resistance vs. VD (VS) for Different Temperatures, 3.3 V
1.2 VDD = 2.5V
0.8 TA = 25C 0.7 VDD = 2.3V ON RESISTANCE ()
1.0 +125C 0.8 +85C 0.6 +25C -40C 0.2
ON RESISTANCE ()
0.6
0.5
VDD = 2.5V
VDD = 2.7V
0.4
0.4
0.3
0.2
0
0.5
1.0
1.5 VD, VS (V)
2.0
2.5
0
0
0.5
1.0
1.5 VD, VS (V)
2.0
2.5
TPC 2. On Resistance vs. VD (VS) VDD = 2.5 V 0.2 V
TPC 5. On Resistance vs. VD (VS) for Different Temperature, 2.5 V
1.4 VDD = 1.8V 1.2 +125C ON RESISTANCE () 1.0 0.8 0.7 0.5 0.2 0 +85C
1.8 TA = 25C 1.6 1.4 ON RESISTANCE () 1.2 VDD = 1.8V 1.0 0.8 0.6 0.4 0.2 VDD = 1.65V
-40C +25C
VDD = 1.95V
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VD, VS (V)
VD, VS (V)
TPC 3. On Resistance vs. VD (VS), VDD = 1.8 V 0.15 V
TPC 6. On Resistance vs. VD (VS) for Different Temperatures, 1.8 V
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ADG836
80 VDD = 3.3V 60 ID, IS (ON) 40 20 0 -20 IS (OFF) -40 -60 -80 30 20 10 0 20 40 60 80 100 120 0 90 80 70 60 50 40 TA = 25C
VCC = 3.3V
VCC = 2.5V VCC = 1.8V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5

TPC 7. Leakage Currents vs. Temperature, 3.3 V
60 50 40 30 CURRENT (nA) 20 10 0 -10 -20 -30 -40 0 20 40 60 80 100 120 IS (OFF) ID, IS (ON)
TPC 10. Charge Injection vs. Source Voltage
VDD = 2.5V

TEMPERATURE (C)

TPC 8. Leakage Current vs. Temperature, 2.5 V
50 40 30 CURRENT (nA) IS, ID (ON) 20 10 0 -10 -20 IS (OFF) ATTENUATION (dB)
TPC 11. tON/tOFF Times vs. Temperature
TA = 25C VCC = 3.3V/2.5V/1.8V
VDD = 1.8V
0
20
40
60
80
100
120

TEMPERATURE (C)

TPC 9. Leakage Current vs. Temperature, 1.8 V
TPC 12. Bandwidth
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ADG836
0 -10 -20 ATTENUATION (dB) -30 -40 -50 -60 -70 -80 0 20 TA = 25C VCC = 3.3V/2.5V/1.8V THD + N (%) 0.06 0.10 VDD = 2.5V TA = 25C S1A-D1 32 LOAD 0.08 1.5V p-p
0.04
0.02

50
100
200
500
1k
2k
5k
10k
20k

FREQUENCY (Hz)
TPC 13. Off Isolation vs. Frequency
TPC 15. Total Harmonic Distortion + Noise
-10 -20 -30 ATTENUATION (dB) -40 -50 -60 -70 -80 -90 -100 TA = 25C VCC = 3.3V/2.5V/1.8V

TPC 14. Crosstalk vs. Frequency
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ADG836 Test Circuits

Test Circuit 1. On Resistance
Test Circuit 2. Off Leakage
Test Circuit 3. On Leakage

Test Circuit 4. Switching Times, tON, tOFF

Test Circuit 5. Break-before-Make Time Delay, tBBM

Test Circuit 6. Charge Injection
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ADG836

Test Circuit 7. Off Isolation
Test Circuit 9. Channel-to-Channel Crosstalk (S1A-S1B)

Test Circuit 8. Bandwidth
Test Circuit 10. Channel-to-Channel Crosstalk (S1A-S2A)
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ADG836
OUTLINE DIMENSIONS 10-Lead Mini Small Outline Package [MSOP] (RM-10)
Dimensions shown in millimeters C04308-0-8/03(0)
0.23 0.08 8 0 0.80 0.60 0.40 0.60 MAX 0.45 PIN 1 INDICATOR
TOP VIEW
3.00 BSC
10
6
3.00 BSC
1 5
4.90 BSC
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 1.10 MAX
SEATING PLANE
COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA
12-Lead Lead Frame Chip Scale Package [LFCSP] (CP-12)
Dimensions shown in millimeters
0.75 0.55 0.35
3.00 BSC SQ
PIN 1 INDICATOR 1.45 1.30 SQ* 1.15
9 8 7
10
11
12
1 2 3
2.75 BSC SQ
BOTTOM VIEW 6 5 4
12 MAX 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF
0.50 BSC
0.25 MIN
COPLANARITY 0.08
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1 EXCEPT FOR EXPOSED PAD DIMENSION
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