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CS4362 114 dB, 192 kHz 6-Channel D/A Converter
Features
l 24-Bit
Description
The CS4362 is a complete 6-channel digital-to-analog system including digital interpolation, fifth-order deltasigma digital-to-analog conversion, digital de-emphasis, volume control and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. The CS4362 accepts PCM data at sample rates from 4 kHz to 192 kHz, DSD audio data, and operates over a wide power supply range. These features are ideal for multi-channel audio systems including DVD players. SACD players, A/V receivers, digital TV's and VCR's, mixing consoles, effects processors and set-top box systems. ORDERING INFORMATION CS4362-KQ -10 to 70 CS4362-BQ -40 to 85 CDB4362 48-pin LQFP 48-pin LQFP Evaluation Board
Conversion l Up to 192 kHz Sample Rates l 114 dB Dynamic Range l -100 dB THD+N l Supports PCM or DSD Data Formats l Selectable Digital Filters l Volume Control with Soft Ramp
- 1 dB Step Size - Zero Crossing Click-Free Transitions
l Dedicated
DSD inputs l Low Clock Jitter Sensitivity l Simultaneous Support for Two Synchronous Sample Rates for DVD Audio l C or Stand-Alone Operation
I
M3/DSD_SCLK
M 1/SCL/CCLK
M2/SDA/CDIN
M 0/AD0/CS VLC
MUTEC[1:6] 6
RST
Control Port/Mode Select
E xt e rn a l M ut e C o n tr ol
D A C
VLS S CLK1 LRCK1 S C LK 2 S e ri a l P o rt L R CK 2 SD I N1 SD I N2 SD I N3
V olu m e C o nt r o l Mixer V olu m e C ontro l
I n t e r p o l a t i o n F i lt e r
A n a lo g F i lt e r
A O U T A1+ A O U T A1A O U T B1+ A O U T B1A O U T A2+ A O U T A2A O U T B2+ A O U T B2A O U T A3+ A O U T A3A O U T B3+ A O U T B3VQ FILT+
I n t e r p o l a t i o n F i lt e r
D A C
A n a l o g F i lt e r
V olu m e C o nt r o l Mixer V olu m e C ontro l
I n t e r p o l a t i o n F i lt e r
D A C
A n a lo g F i lt e r
I n t e r p o l a t i o n F i lt e r
D A C
A n a l o g F i lt e r
V olu m e C o nt r o l M CLK Mixer V olu m e C ontro l
I n t e r p o l a t i o n F i lt e r
D A C
A n a lo g F i lt e r
I n t e r p o l a t i o n F i lt e r
D A C
A n a l o g F i lt e r
/2
DSDxx 6
VD
GND
GND
VA
Advance Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001 (All Rights Reserved)
MAY `01 DS257PP1 1
CS4362
TABLE OF CONTENTS
1. 2. 3. 4. 5. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 REGISTER QUICK REFERENCE .......................................................................................... 14 REGISTER DESCRIPTION .................................................................................................... 15 PIN DESCRIPTION ................................................................................................................. 24 APPLICATIONS ...................................................................................................................... 27 5.1 Grounding and Power Supply Decoupling ....................................................................... 27 5.2 Oversampling Modes ....................................................................................................... 27 5.3 Recommended Power-up Sequence ............................................................................... 27 5.4 Analog Output and Filtering ............................................................................................. 27 5.5 Interpolation Filter ............................................................................................................ 27 5.6 Clock Source Selection .................................................................................................... 28 5.7 Using DSD mode ............................................................................................................. 28 CONTROL PORT INTERFACE .............................................................................................. 28 6.1 Enabling the Control Port ................................................................................................. 28 6.2 Format Selection .............................................................................................................. 28 6.3 Two-Wire Format ............................................................................................................. 29 6.3.1 Writing in Two-Wire Format ................................................................................ 29 6.3.2 Reading in Two-Wire Format .............................................................................. 29 6.4 SPI Format ....................................................................................................................... 29 6.4.1 Writing in SPI ...................................................................................................... 29 6.5 Memory Address Pointer (MAP) ...................................................................................... 30 PARAMETER DEFINITIONS .................................................................................................. 38 REFERENCES ........................................................................................................................ 38 PACKAGE DIMENSIONS ....................................................................................................... 39
6.
7. 8. 9.
LIST OF FIGURES
Figure 1. Serial Mode Input Timing ................................................................................................. 8 Figure 2. Direct Stream Digital - Serial Audio Input Timing............................................................. 9 Figure 3. Control Port Timing - Two-Wire Format ......................................................................... 10 Figure 4. Control Port Timing - SPI Format................................................................................... 11 Figure 5. Typical Connection Diagram Control Port...................................................................... 12 Figure 6. Typical Connection Diagram Stand-Alone ..................................................................... 13 Figure 7. Control Port Timing, Two-Wire Format .......................................................................... 29 Figure 1. Control Port Timing, Two-Wire Format .......................................................................... 29 Figure 8. Control Port Timing, SPI Format .................................................................................... 30 Figure 9. Single Speed (fast) Stopband Rejection ........................................................................ 31
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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CS4362
Figure 10. Single Speed (fast) Transition Band ............................................................................ 31 Figure 11. Single Speed (fast) Transition Band (detail) ................................................................ 31 Figure 12. Single Speed (fast) Passband Ripple .......................................................................... 31 Figure 13. Single Speed (slow) Stopband Rejection..................................................................... 31 Figure 14. Single Speed (slow) Transition Band........................................................................... 31 Figure 15. Single Speed (slow) Transition Band (detail)............................................................... 32 Figure 16. Single Speed (slow) Passband Ripple......................................................................... 32 Figure 17. Double Speed (fast) Stopband Rejection..................................................................... 32 Figure 18. Double Speed (fast) Transition Band........................................................................... 32 Figure 19. Double Speed (fast) Transition Band (detail)............................................................... 32 Figure 20. Double Speed (fast) Passband Ripple......................................................................... 32 Figure 21. Double Speed (slow) Stopband Rejection ................................................................... 33 Figure 22. Double Speed (slow) Transition Band ......................................................................... 33 Figure 23. Double Speed (slow) Transition Band (detail) ............................................................. 33 Figure 24. Double Speed (slow) Passband Ripple ....................................................................... 33 Figure 25. Quad Speed (fast) Stopband Rejection ....................................................................... 33 Figure 26. Quad Speed (fast) Transition Band ............................................................................. 33 Figure 27. Quad Speed (fast) Transition Band (detail) ................................................................. 34 Figure 28. Quad Speed (fast) Passband Ripple ........................................................................... 34 Figure 29. Quad Speed (slow) Stopband Rejection...................................................................... 34 Figure 30. Quad Speed (slow) Transition Band ............................................................................ 34 Figure 31. Quad Speed (slow) Transition Band (detail) ................................................................ 34 Figure 32. Quad Speed (slow) Passband Ripple .......................................................................... 34 Figure 33. Format 0 - Left Justified up to 24-bit Data.................................................................... 35 Figure 34. Format 1 - I2S up to 24-bit Data................................................................................... 35 Figure 35. Format 2 - Right Justified 16-bit Data .......................................................................... 35 Figure 36. Format 3 - Right Justified 24-bit Data .......................................................................... 35 Figure 37. Format 4 - Right Justified 20-bit Data .......................................................................... 36 Figure 38. Format 5 - Right Justified 18-bit Data .......................................................................... 36 Figure 39. De-Emphasis Curve..................................................................................................... 36 Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, or 3) ....................................... 36 Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, or 3) ...................................................... 37 Figure 42. Recommended Output Filter........................................................................................ 37
LIST OF TABLES
Table 1. Digital Interface Formats - PCM Mode............................................................................ 16 Table 2. Digital Interface Formats - DSD Mode ............................................................................ 16 Table 3. ATAPI Decode ................................................................................................................ 21 Table 4. Example Digital Volume Settings .................................................................................... 22 Table 5. Common Clock Frequencies........................................................................................... 26 Table 6. Digital Interface Format, Stand-Alone Mode Options...................................................... 26 Table 7. Mode Selection, Stand-Alone Mode Options .................................................................. 26 Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................... 26
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CS4362
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth
10 Hz to 20 kHz, unless otherwise specified; Test load RL = 3 k, CL = 100 pF, VA = 5 V, VD = 3 V (see Figure 5) For Single speed Mode Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz; For Double Speed Mode Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz; For Quad Speed Mode Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz; For Direct Stream Digital Mode Fs = 128 x 48 kHz, DSD_SCLK = 6.144 MHz, MCLK = 12.288 MHz). Parameters Specified Temperature Range Dynamic Range (Note 2) unweighted A-Weighted 16-bit unweighted (Note 3) A-Weighted 24-bit (Note 2) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB (1 kHz) TA unweighted A-Weighted 16-bit unweighted (Note 3) A-Weighted 24-bit (Note 2) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB (1 kHz) 24-bit 24-bit Symbol TA Min -10 TBD TBD -40 TBD TBD Typ 111 114 94 97 -100 -91 -51 -94 -74 -34 114 90 111 114 94 97 -100 -91 -51 -94 -74 -34 114 90 Max 70 TBD 85 TBD Unit C dB dB dB dB dB dB dB dB dB dB dB dB C dB dB dB dB dB dB dB dB dB dB dB dB CS4362-KQ Dynamic Performance - All PCM modes and DSD (Note 1)
Total Harmonic Distortion + Noise
16-bit (Note 3) Idle Channel Noise / Signal-to-noise ratio Interchannel Isolation Specified Temperature Range Dynamic Range (Note 2)
CS4362-BQ Dynamic Performance - All PCM modes and DSD (Note 4)
Total Harmonic Distortion + Noise
16-bit (Note 3) Idle Channel Noise / Signal-to-noise ratio Interchannel Isolation
Notes: 1. CS4362-KQ parts are tested at 25 C. 2. One-half LSB of triangular PDF dither is added to data. 3. Performance limited by 16-bit quantization noise. 4. CS4362-BQ parts are tested at the extremes of the specified temperature range and Min/Max performance numbers are guaranteed across the specified temperature range, TA. Typical numbers are taken at 25 C.
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CS4362
ANALOG CHARACTERISTICS (Continued)
Parameters Analog Output - All PCM modes and DSD Full Scale Differential Output Voltage Quiescent Voltage Max Current from VQ Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance Load Capacitance Symbol Min 96% VA 3 Typ 98% VA 50% VA 1 0.1 100 100 Max 100% VA 100 Units Vpp VDC A dB ppm/C k pF
VQ IQMAX
ZOUT RL CL
POWER AND THERMAL CHARACTERISTICS
Parameters Power Supplies Power Supply Current (Note 5) normal operation, VA= 5V VD= 5V VD= 3V Interface current, VLC=5V (Note 6) VLS=5V power-down state (all supplies) (Note 7) Power Dissipation (Note 5) VA = 5 V, VD = 3 V normal operation power-down (Note 7) VA = 5 V, VD = 5 V normal operation power-down (Note 7) Package Thermal Resistance (1 kHz) (60 Hz) Symbol IA ID ID ILC ILS Ipd Min Typ 40 42 25 2 84 200 275 1 410 1 48 TBD 60 40 Max TBD TBD Units mA mA mA A A A mW mW mW mW C/Watt C/Watt dB dB
Power Supply Rejection Ratio (Note 8)
JA JC PSRR
Notes: 5. Current consumption increases with increasing FS and increasing MCLK. Max values are based on highest FS and highest MCLK. Variance between speed modes is negligible. 6. ILC measured with no external loading on the SDA pin. 7. Power down mode is defined as RST pin = Low with all clock and data lines held static. 8. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.
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CS4362
ANALOG FILTER RESPONSE
Fast Roll-Off Slow Roll-Off (Note 9) Parameter Min Typ Max Min Typ Max Unit Combined Digital and On-chip Analog Filter Response - Single Speed Mode (Note 10) Passband (Note 11) to -0.01 dB corner 0 .4535 0 0.4166 Fs to -3 dB corner 0 .4998 0 0.4998 Fs Frequency Response 10 Hz to 20 kHz -0.01 +0.01 -0.01 +0.01 dB StopBand .5465 .5834 Fs StopBand Attenuation (Note 12) 90 64 dB Group Delay 12/Fs 6.5/Fs s Passband Group Delay Deviation 0 - 20 kHz 0.41/Fs 0.14/Fs s De-emphasis Error (Note 13) Fs = 32 kHz 0.23 0.23 dB (Relative to 1kHz) Fs = 44.1 kHz 0.14 0.14 dB Fs = 48 kHz 0.09 0.09 dB Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96kHz (Note 10) Passband (Note 11) to -0.01 dB corner 0 .4166 0 .2083 Fs to -3 dB corner 0 .4998 0 .4998 Fs Frequency Response 10 Hz to 20 kHz -0.01 0.01 -0.01 0.01 dB StopBand .5834 .7917 Fs StopBand Attenuation (Note 12) 80 70 dB Group Delay 4.6/Fs 3.9/Fs s Passband Group Delay Deviation 0 - 20 kHz 0.03/Fs 0.01/Fs s Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192kHz (Note 10) Passband (Note 11) to -0.01 dB corner 0 .1046 0 .1042 Fs to -3 dB corner 0 .4897 0 .4813 Fs Frequency Response 10 Hz to 20 kHz -0.01 0.01 -0.01 0.01 dB StopBand .6355 .8683 Fs StopBand Attenuation (Note 12) 90 75 dB Group Delay 4.7/Fs 4.2/Fs s Passband Group Delay Deviation 0 - 20 kHz 0.01/Fs 0.01/Fs s Combined Digital and On-chip Analog Filter Response - DSD Mode (Note 10) Passband (Note 11) to -0.1 dB corner 0 20 kHz to -3 dB corner 0 120 kHz Frequency Response 10 Hz to 20 kHz -.01 0.1 dB Notes: 9. Slow Roll-Off interpolation filter is only available in control port mode. 10. Filter response is not tested but is guaranteed by design. 11. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 to 32) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 12. Single and Double Speed Mode Measurement Bandwidth is from stopband to 3 Fs. Quad Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs. 13. De-emphasis is available only in Single Speed Mode; Only 44.1kHz De-emphasis is available in StandAlone Mode
6
CS4362
DIGITAL CHARACTERISTICS (For KQ TA = -10 to +70 C; For BQ TA = -40 to +85 C; VLC = VLS =
1.8 V to 5.5 V) Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Maximum MUTEC Drive Current MUTEC High-Level Output Voltage MUTEC Low-Level Output Voltage Serial Data Port Control Port Serial Data Port Control Port Symbol Min VIH 70% VLS 70% VLC VIH VIL VIL Iin Typ 8 3 VA 0 Max 20% VLS 20% VLC 10 Units V V V V A pF mA V V
VOH VOL
ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)
Parameters Analog power Digital internal power Serial data port interface power Control port interface power Input Current, Any Pin Except Supplies Digital Input Voltage Serial data port interface Control port interface Ambient Operating Temperature (power applied) Storage Temperature DC Power Supply Symbol VA VD VLS VLC Iin VIND-S VIND-C TA Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 -65 Max 6.0 6.0 6.0 6.0 10 VLS+ 0.4 VLC+ 0.4 125 150 Units V V V V mA V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)
Parameters DC Power Supply Analog power Digital internal power Serial data port interface power Control port interface power Symbol VA VD VLS VLC Min 4.5 2.7 1.8 1.8 Typ 5.0 3.0 5.0 5.0 Max 5.5 5.5 5.5 5.5 Units V V V V
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CS4362
SWITCHING CHARACTERISTICS (For KQ TA = -10 to +70 C; For BQ TA = -40 to +85 C; VLS =
1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30pF) Parameters MCLK Frequency (Note 14) Single Speed Mode Double Speed Mode Quad Speed Mode MCLK Duty Cycle Input Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Fs Fs Fs tsclkl tsclkh tsclkw (Note 15) SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time LRCK1 to LRCK2 frequency ratio (Note 16) tsclkw tslrd tslrs tsdlrs tsdh 1.024 6.400 6.400 40 4 50 100 45 20 20
2 ----------------MCLK 4 ----------------MCLK
Symbol
Min
Typ 50 50 1.00
Max 51.2 51.2 51.2 60 50 100 200 55 4.00
Units MHz MHz MHz % kHz kHz kHz % ns ns ns ns ns ns ns ns
LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Period
20 20 20 20 0.25
Notes: 14. See Table 5 on page 26 for suggested MCLK frequencies 15. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled. 16. The higher frequency LRCK must be an exact integer multiple (1, 2, or 4) of the lower frequency LRCK
.
LRCK t slrd t slrs t sclkl t sclkh
SCLK t sdlrs SDATA t sdh
Figure 1. Serial Mode Input Timing
8
CS4362
DSD - SWITCHING CHARACTERISTICS (TA= -10 to 70C; Logic 0 = GND; VLS = 1.8 V to
5.5 V; Logic 1 = VLS Volts; CL = 30 pF) Parameter Master Clock Frequency MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency Symbol (Note 17) (All DSD modes) tsclkl tsclkh Min 4.096 40 20 20 1.024 2.048 20 20 Typ 50 Max 38.4 60 3.2 6.4 Unit MHz % ns ns MHz MHz ns ns
(64x Oversampled) (128x Oversampled) DSD_L / _R valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_L or DSD_R hold time
tsdlrs tsdh
Note: 17. Min is 4 times 64x DSD or 2 times 128x DSD, and Max is 12 times 64x DSD or 6 times 128x DSD. The proper MCLK to DSD_SCLK ratio must be set either by the DIF registers or the M0:2 pins
t sclkh t sclkl DSD_SCLK t sdlrs
DSD_L, DSD_R
t sdh
Figure 2. Direct Stream Digital - Serial Audio Input Timing
9
CS4362
SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE FORMAT
(Note 18) (For KQ TA = -10 to +70 C; For BQ TA = -40 to +85 C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 20) (Note 19) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trc tfc, tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 Max 100 1 300 (Note 21) Unit kHz ns s s s s s s ns s ns s ns
Notes: 18. The Two-Wire Format is compatible with the I2C protocol. 19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed. 21.
15 15 15 -------------------- for Single-Speed Mode, -------------------- for Double-Speed Mode, ----------------- for Quad-Speed Mode. 256 x Fs 128 x Fs 64 x Fs
RST t Stop irs S tart R e pe ate d S tart t rd t fd Stop
SDA t buf t hdst t high t hdst t fc t susp
SCL t t t sud t ack t sust t rc
lo w
hdd
Figure 3. Control Port Timing - Two-Wire Format
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CS4362
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(For KQ TA = -10 to +70 C; For BQ TA = -40 to +85 C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 23) (Note 24) (Note 24) (Note 22) Symbol fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2 Min 500 500 1.0 20
1 ----------------MCLK 1 ----------------MCLK
Max
MCLK ----------------2
Unit MHz ns ns s ns ns ns ns ns ns ns
100 100
40 15 -
Notes: 22. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 23. Data must be held for sufficient time to bridge the transition time of CCLK. 24. For FSCK < 1 MHz.
RST
t srs
CS t spi t css CCLK t r2
CDIN
t scl
t sch
t csh
t f2
t dsu t dh
Figure 4. Control Port Timing - SPI Format
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CS4362
+ 3 V to + 5 V 1 F + 0 .1 F 4 VD 32 VA 0 .1 F + 1 F
+5 V
6 7 PCM D ig ita l A u d io S o u rc e 9 10 12 8 11 13
M C LK LRCK1 SCLK1 LRC K 2 SC LK 2 S D IN 1 S D IN 2 S D IN 3 A O U TA 2+ 35 36 A n a lo g C o n d itio n in g a n d M u t in g A O U TB 1+ AO U TB 138 37 A n a lo g C o n d itio n in g a n d M u t in g A O U TA 1+ AO U TA 139 40 A n a lo g C o n d itio n in g a n d M u t in g
+ 1 .8 V to + 5 V 0 .1 F
43
VLS
AO U TA 2-
CS4362
A O U TB 2+ AO U TB 23 2 1
34 33 A n a lo g C o n d itio n in g a n d M u t in g
DSDA1 DSDB1 DSDA2 DSDB2 DSDA3 DSDB3 D SD _SC LK
A O U TA 3+ AO U TA 3-
29 30 A n a lo g C o n d itio n in g a n d M u t in g
DSD A u d io S o u rc e
48 47 46 42
A O U TB 3+ AO U TB 3-
28 27 A n a lo g C o n d itio n in g a n d M u t in g
M U TE C 1 M U TE C 2 M U TE C 3
41 26 25 24 23 22 M u te D r iv e
19 M ic ro C o n t ro lle r 15 16 17
M U TE C 4 RST S C L /C C L K S D A /C D IN A D O /C S M U TE C 5 M U TE C 6
N o te * + 1 .8 V to + 5 V 18 0 .1 F F IL T + VLC CM OUT
2 K
2 K
20 21 0 .1 F + 1 F 0 .1 F + 47 F
GND 5 N o t e * : N e c e s s a ry fo r T w o -W ire c o n tro l p o r t o p e ra tio n
GND 31
Figure 5. Typical Connection Diagram Control Port
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CS4362
+ 3 V to + 5 V 1 F + 0 .1 F 4 VD N o te * 47 K 32 VA 0 .1 F + 1 F
+5 V
VLS
6 7 9 PCM D ig ita l A u d io S o u rc e 10 12 8 11 13
M C LK LRCK1 S C LK 1 LRCK2 S C LK 2 S D IN 1 S D IN 2 S D IN 3 AO U TB 1+ AO U TB 138 37 26 A n a lo g C o n d itio n in g a n d M u tin g AO U TA 1+ AO U TA 1M UTEC1 39 40 41 A n a lo g C o n d itio n in g a n d M u tin g
+ 1 .8 V to + 5 V 0 .1 F
43
V LS
M UTEC2
C S4362
AO U TA 2+ AO U TA 23 2 1 DSDA1 DSDB1 DSDA2 DSDB2 DSDA3 DSDB3 AO U TA 3+ 29 30 23 A n a lo g C o n d itio n in g a n d M u tin g AO U TB 2+ AO U TB 2M UTEC4 34 33 24 A n a lo g C o n d itio n in g a n d M u tin g M UTEC3 35 36 25 A n a lo g C o n d itio n in g a n d M u tin g
DSD A u d io S o u rc e
48 47 46
N o te *
AO U TA 3M UTEC5
42 S ta n d -A lo n e M o d e C o n fig u ra tio n 15 16 17 19
M 3 (D S D _ S C L K ) M2 M1 M0 RST
AO U TB 3+ AO U TB 3M UTEC6
28 27 22 A n a lo g C o n d itio n in g a n d M u tin g
+ 1 .8 V to + 5 V
18 0 .1 F
V LC
F IL T + CM OUT
20 21 0 .1 F + 1 F 0 .1 F + 47 F
N o te *: F o r D S D o p e ra tio n : 1 ) L R C K 1 m u s t b e tie d to V L S a n d re m a in s ta tic h ig h . 2 ) M 3 P C M s ta n d -a lo n e c o n fig u ra tio n p in b e c o m e s D S D _ S C L K
GND 5
GND 31
Figure 6. Typical Connection Diagram Stand-Alone
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CS4362
2.
Addr
01h 02h 03h 04h 05h 06h
REGISTER QUICK REFERENCE
Function
Mode Control 1 default Mode Control 2 default Mode Control 3 default Filter Control default Invert Control default Mixing Control Pair 1 (AOUTx1) default Vol. Control A1 default Vol. Control B1 default Mixing Control Pair 2 (AOUTx2) default
7
CPEN 0 Reserved 0 SZC1 1 Reserved 0 Reserved 0 P1_A=B 0 A1_MUTE 0 B1_MUTE 0 P2_A=B 0 A2_MUTE 0 B2_MUTE 0 P3_A=B 0 A3_MUTE 0 B3_MUTE 0 PART3 1
6
FREEZE 0 DIF2 0 SZC0 0 Reserved 0 Reserved 0 P1ATAPI4 0 A1_VOL6 0 B1_VOL6 0 P2ATAPI4 0 A2_VOL6 0 B2_VOL6 0 P3ATAPI4 0 A3_VOL6 0 B3_VOL6 0 PART2 1
5 0
DIF1 0 SNGLVOL 0 Reserved 0 INV_B3 0 P1ATAPI3 1 A1_VOL5 0 B1_VOL5 0 P2ATAPI3 1 A2_VOL5 0 B2_VOL5 0 P3ATAPI3 1 A3_VOL5 0 B3_VOL5 0 PART1 1
4
0 DIF0 0 RMP_UP 0 FILT_SEL 0 INV_A3 0 P1ATAPI2 0 A1_VOL4 0 B1_VOL4 0 P2ATAPI2 0 A2_VOL4 0 B2_VOL4 0 P3ATAPI2 0 A3_VOL4 0 B3_VOL4 0 PART0 0
3
0 Reserved 0 Reserved 0 Reserved 0 INV_B2 0 P1ATAPI1 0 A1_VOL3 0 B1_VOL3 0 P2ATAPI1 0 A2_VOL3 0 B2_VOL3 0 P3ATAPI1 0 A3_VOL3 0 B3_VOL3 0 Reserved -
2
0 0 AMUTE 1 DEM1 0 INV_A2 0 P1ATAPI0 1 A1_VOL2 0 B1_VOL2 0 P2ATAPI0 1 A2_VOL2 0 B2_VOL2 0 P3ATAPI0 1 A3_VOL2 0 B3_VOL2 0 Reserved -
1
0 0 MUTEC1 0 DEM0 0 INV_B1 0 P1FM1 0 A1_VOL1 0 B1_VOL1 0 P2FM1 0 A2_VOL1 0 B2_VOL1 0 P3FM1 0 A3_VOL1 0 B3_VOL1 0 Reserved -
0
PDN 1 0 MUTEC0 0 RMP_DN 0 INV_A1 0 P1FM0 0 A1_VOL0 0 B1_VOL0 0 P2FM0 0 A2_VOL0 0 B2_VOL0 0 P3FM0 0 A3_VOL0 0 B3_VOL0 0 Reserved -
MCLKDIV Reserved DAC3_DIS DAC2_DIS DAC1_DIS
SDIN3CLK SDIN2CLK SDIN1CLK
07h 08h 09h
0Ah Vol. Control A2 default 0Bh Vol. Control B2 default 0Ch Mixing Control Pair 3 (AOUTx3) default 0Dh Vol. Control A3 default 0Eh Vol. Control B3 default 12h Chip Revision default
14
CS4362
3.
Note:
REGISTER DESCRIPTION
All registers are read/write in Two-Wire mode and write only in SPI, unless otherwise noted.
3.1
Mode Control 1 (address 01h)
7 CPEN 0 6 FREEZE 0 5
MCLKDIV 0
4 Reserved 0
3 DAC3_DIS 0
2 DAC2_DIS 0
1 DAC1_DIS 0
0 PDN 1
3.1.1
CONTROL PORT ENABLE (CPEN)
Default = 0 0 - Disabled 1 - Enabled Function: This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean powerup, the user should write this bit within 10 ms following the release of Reset.
3.1.2
FREEZE CONTROLS (FREEZE)
Default = 0 0 - Disabled 1 - Enabled Function: This function allows modifications to be made to the registers without the changes taking effect until the FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
3.1.3
MASTER CLOCK DIVIDE ENABLE (MCLKDIV)
Default = 0 0 - Disabled 1 - Enabled Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry.
3.1.4
DAC PAIR DISABLE (DACX_DIS)
Default = 0 0 - Enabled 1 - Disabled Function: When enabled the respective DAC channel pairx (AOUTAx and AOUTBx) will remain in a reset state. It is advised that changes to these bits be made while the power down bit is enabled to eliminate the possibility of audible artifacts.
15
CS4362
3.1.5 POWER DOWN (PDN)
Default = 1 0 - Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to `enabled' on power-up and must be disabled before normal operation in Control Port mode can occur.
3.2
Mode Control 2 (address 02h)
6 DIF2 0 5 DIF1 0 4 DIF0 0 3 Reserved 0 2 SDIN3CLK 0 1 SDIN2CLK 0 0 SDIN1CLK 0
7 Reserved 0
3.2.1
DIGITAL INTERFACE FORMAT (DIF)
Default = 000 - Format 0 (Left Justified, up to 24-bit data) Function: These bits select the interface format for the serial audio input. The Functional Mode bits determine whether PCM or DSD mode is selected. PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 33-38.
DIF2
0 0 0 0 1 1 1 1
DIF1
0 0 1 1 0 0 1 1
DIF0
0 1 0 1 0 1 0 1
DESCRIPTION Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 16-bit data Right Justified, 18-bit data Reserved Reserved
Format
0 1 2 3 4 5
FIGURE
33 34 35 36 37 38
Table 1. Digital Interface Formats - PCM Mode DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required Master clock to DSD data rate is defined by the Digital Interface Format pins. DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIFO 0 1 0 1 0 1 0 1 DESCRIPTION 64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 2. Digital Interface Formats - DSD Mode
16
CS4362
3.2.2 SERIAL AUDIO DATA CLOCK SOURCE (SDINXCLK)
Default = 0 0 - SDINx clocked by SCLK1 and LRCK1 1 - SDINx clocked by SCLK2 and LRCK2 Function: The SDINxCLK bit specifies which SCLK/LRCK input pair is used to clock in the data on the given SDINx line. For more details see "Clock Source Selection" on page 28.
3.3
Mode Control 3 (address 03h)
7 SZC1 1 6 SZC0 0 5 SNGLVOL 0 4 RMP_UP 0 3 Reserved 0 2 AMUTE 1 1 MUTEC1 0 0 MUTEC0 0
3.3.1
SOFT RAMP AND ZERO CROSS CONTROL (SZC)
Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
17
CS4362
3.3.2 SINGLE VOLUME CONTROL (SNGLVOL)
Default = 0 0 - Disabled 1 - Enabled Function: The individual channel volume levels are independently controlled by their respective Volume Control Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.
3.3.3
SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP)
Default = 0 0 - Disabled 1 - Enabled Function: An un-mute will be performed after executing a filter mode change, after a LRCK/MCLK ratio change or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate un-mute is performed in these instances. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
3.3.4
AUTO-MUTE (AMUTE)
Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Mode Control 3 register.
3.3.5
MUTE PIN CONTROL(MUTEC1, MUTEC0)
Default = 00 00 - Six mute control signals 01 - Three mute control signals 10 - One mute control signal 11 - Reserved Function: Selects how the internal mute control signals are routed to the MUTEC1 through MUTEC6 pins. When set to `00', there is one mute control signal for each channel: AOUT1A on MUTEC1, AOUT1B on MUTEC2, etc. When set to `01', there are three mute control signals, one for each stereo pair: AOUT1A and AOUT1B on MUTEC1, AOUT2A and AOUT2B on MUTEC2, and AOUT3A and AOUT3B on MUTEC3. When set to `10', there is a single mute control signal on the MUTEC1 pin.
18
CS4362
3.4 Filter Control (address 04h)
6 Reserved 0 5 Reserved 0 4 FILT_SEL 0 3 Reserved 0 2 DEM1 0 1 DEM0 0 0 RMP_DN 0
7 Reserved 0
3.4.1
INTERPOLATION FILTER SELECT (FILT_SEL)
Default = 0 0 - Fast roll-off 1 - Slow roll-off Function: This Function allows the user to select whether the interpolation filter has a fast or slow roll off. For filter characteristics please see Section 1.
3.4.2
DE-EMPHASIS CONTROL (DEM)
Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 39) De-emphasis is only available in Single Speed Mode.
3.4.3
SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN)
Default = 0 0 - Disabled 1 - Enabled Function: A mute will be performed prior to executing a filter mode change. When this feature is enabled, this mute is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate mute is performed prior to executing a filter mode change. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
19
CS4362
3.5 Invert control (address 05h)
6 Reserved 0 5 INV_B3 0 4 INV_A3 0 3 INV_B2 0 2 INV_A2 0 1 INV_B1 0 0 INV_A1 0
7 Reserved 0
3.5.1
INVERT SIGNAL POLARITY (INV_XX)
Default = 0 0 - Disabled 1 - Enabled Function: When enabled, these bits will invert the signal polarity of their respective channels.
3.6
Mixing Control Pair 1 (Channels A1 & B1)(address 06h) Mixing Control Pair 2 (Channels A2 & B2)(address 09h) Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)
7 Px_A=B 0 6 PxATAPI4 0 5 PxATAPI3 1 4 PxATAPI2 0 3 PxATAPI1 0 2 PxATAPI0 1 1 PxFM1 0 0 PxFM0 0
3.6.1
CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)
Default = 0 0 - Disabled 1 - Enabled Function: The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are determined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled.
3.6.2
ATAPI CHANNEL MIXING AND MUTING (ATAPI)
Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4362 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 3 and Figure 41 for additional information.
20
CS4362
ATAPI4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
AOUTAx MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL [(aL+bR)/2] [(aL+bR)/2] [(bL+aR)/2] [(aL+bR)/2]
AOUTBx MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(bL+aR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2]
Table 3. ATAPI Decode
3.6.3
FUNCTIONAL MODE (FM)
Default = 00 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Direct Stream Digital Mode Function: Selects the required range of input sample rates or DSD Mode. When DSD mode is selected for any channel pair then all pairs will switch to DSD mode.
21
CS4362
3.7 Volume control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh)
6 xx_VOL6 0 5 xx_VOL5 0 4 xx_VOL4 0 3 xx_VOL3 0 2 xx_VOL2 0 1 xx_VOL1 0 0 xx_VOL0 0
7 xx_MUTE 0
3.7.1
MUTE (MUTE)
Default = 0 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross bits. The MUTE pins will go active during the mute period according to the MUTEC bits.
3.7.2
VOLUME CONTROL (XX_VOL)
Default = 0 (No attenuation) Function: The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments from 0 to -127 dB. Volume settings are decoded as shown in Table 4. The volume changes are implemented as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent to enabling the MUTE bit.
Binary Code
Decimal Value
Volume Setting
0000000 0010100 0101000 0111100 1011010
0 20 40 60 90
0 dB -20 dB -40 dB -60 dB -90 dB
Table 4. Example Digital Volume Settings
22
CS4362
3.8 Chip Revision (address 12h)
7 PART3 1 6 PART2 1 5 PART1 1 4 PART0 0 3 Reserved 2 Reserved 1 Reserved 0 Reserved -
3.8.1
PART NUMBER ID (PART) [READ ONLY]
1110 - CS4362 Function: This read-only register can be used to identify the model number of the device.
23
CS4362
4. PIN DESCRIPTION
M3(DSD_SCLK) AO UTB1+ AOUTA1+ MUTEC1 AO UTB1AOUTA1-
DSDA3
DSDB2
DSDB3
TST
48 47 46 45 44 43 42 41 40 39 38 37
TST
VLS
DSDA2 DSDB1 DSDA1 VD GND MCLK LRCK1(DSD_EN) SDIN1 SCLK1 LRCK2 SDIN2 SCLK2
1 2 3 4 5 6 7 8 9 10 11 12 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 21 2 2 2 3 2 4 M 2(S C L/C C LK ) M 1 (S DA /C DIN )
36 35 34 33 32
AOUTA2AOUTA2+ AOUTB2+ AOUTB2VA GND AOUTA3AOUTA3+ AOUTB3+ AOUTB3MUTEC2 MUTEC3
CS4362
31 30 29 28 27 26 25
M0(AD0/CS)
S D IN 3
Pin Name
VD GND MCLK LRCK1 LRCK2 SDIN1 SDIN2 SDIN3 SCLK1 SCLK2 TST
#
4 5 31 6 7 10 8 11 13 9 12 14 44 45 19 32 43 18
Pin Description
Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operating Conditions for appropriate voltages. Ground (Input) - Ground reference. Should be connected to analog ground. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 5 illustrates several standard audio sample rates and the required master clock frequencies. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs. Serial Data Input (Input) - Input for two's complement serial audio data.
Serial Clock (Input) - Serial clocks for the serial audio interface. Test - These pins need to be tied to analog ground.
RST VA VLS VLC
Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Operating Conditions for appropriate voltages. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages. Control Port Power (Input) - Determines the required signal level for the control port and stand alone configuration pins. Refer to the Recommended Operating Conditions for appropriate voltages.
24
M UT EC 6
M UT EC 4
M U TE C5
FIL T+
RST
TS T
VLC
VQ
CS4362
Pin Name
VQ
#
21
Pin Description
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source impedance and any current drawn from this pin will alter device performance. However, VQ can be used to bias the analog circuitry assuming there is no AC signal component and the DC current is less then the maximum specified in the Analog Characteristics and Specifications section. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Requires the capacitive decoupling to analog ground as shown in the Typical Connection Diagram.
FILT+
20
AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,MUTEC1 MUTEC2 MUTEC3 MUTEC4 MUTEC5 MUTEC6
39,40 Differential Analog Output (Output) - The full scale differential analog output level is specified 37,38 in the Analog Characteristics specification table. 35,36 33,34 29,30 27,28 41 26 25 24 23 22 Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. These pins are intended to be used as a control for external mute circuits on the line outputs to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables 6 and 7.
Stand Alone Definitions
M0 M1 M2 M3 SCL/CCLK 17 16 15 42 15
Control Port Definitions
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up resistor to the logic interface voltage in Two-Wire mode as shown in the Typical Connection Diagram. Serial Control Port Data (Input/Output) - SDA is a data I/O line in Two-Wire mode and is open drain, requiring an external pull-up resistor to the logic interface voltage, as shown in the Typical Connection Diagram; CDIN is the input data line for the control port interface in SPI mode. Address Bit 0 (Two-Wire) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in Two-Wire mode; CS is the chip select signal for SPI mode. Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
SDA/CDIN
16
AD0/CS
17
DSD Definitions
DSDA1 DSDB1 DSDA2 DSDB2 DSDA3 DSDB3 DSD_SCLK DSD_EN 3 2 1 48 47 46 42 7
DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface. DSD Enable (Input) - When held at logic `1' the device will enter DSD mode (Stand-Alone mode only).
25
CS4362
Mode (sample-rate range) MCLK Ratio Single Speed (4 to 50 kHz) MCLK Ratio Double Speed (50 to 100 kHz)
Sample Rate (kHz) 32 44.1 48 64 88.2 96 256x 8.1920 11.2896 12.2880 128x 8.1920 11.2896 12.2880 64x 11.2896 12.2880
MCLK (MHz)
Control port only modes 768x 24.5760 33.8688 36.8640 384x 24.5760 33.8688 36.8640 192x 33.8688 36.8640 1024x* 32.7680 45.1584 49.1520 512x* 32.7680 45.1584 49.1520 256x* 45.1584 49.1520
MCLK Ratio 176.4 Quad Speed (100 to 200 kHz) 192
384x 12.2880 16.9344 18.4320 192x 12.2880 16.9344 18.4320 96x 16.9344 18.4320
512x 16.3840 22.5792 24.5760 256x 16.3840 22.5792 24.5760 128x 22.5792 24.5760
Table 5. Common Clock Frequencies *Note: These modes are only available in control port mode by setting the MCLKDIV bit = 1. M1 (DIF1) 0 0 1 1 M0 (DIF0) 0 1 0 1 DESCRIPTION Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data Table 6. Digital Interface Format, Stand-Alone Mode Options M3 0 0 1 1 M2 (DEM) 0 1 0 1 DESCRIPTION Single-Speed without De-Emphasis (4 to 50 kHz sample rates) Single-Speed with 44.1kHz De-Emphasis; see Figure 39 Double-Speed (50 to 100 kHz sample rates) Quad-Speed (100 to 200 kHz sample rates) Table 7. Mode Selection, Stand-Alone Mode Options DSD_Mode (LRCK1) 1 1 1 1 1 1 1 1 M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 DESCRIPTION 64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate FORMAT 0 1 2 3 FIGURE 33 34 35 36
Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options
26
CS4362
5. APPLICATIONS 5.1 Grounding and Power Supply Decoupling
gle-Speed Mode (1024 LRCK cycles in DoubleSpeed Mode, and 2048 LRCK cycles in QuadSpeed Mode). Writing this bit will halt the StandAlone power-up sequence and initialize the control port to its default settings. The desired register settings can be loaded while keeping the PDN bit set to 1. 3. If Control Port Mode is selected via the CPEN bit, set the PDN bit to 0 which will initiate the power-up sequence.
As with any high resolution converter, the CS4362 requires careful attention to power supply and grounding arrangements to optimize performance. Figures 5 & 6 show the recommended power arrangement with VA, VD, VLS and VLC connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin (see Section 1 for recommended voltages).
5.4
Analog Output and Filtering
5.2
Oversampling Modes
The CS4362 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the M3 and M2 pins in StandAlone mode or the FM bits in Control Port mode. Single-Speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
The application note "Design Notes for a 2-Pole Filter with Differential Input" discusses the second-order Butterworth filter and differential to single-ended converter which was implemented on the CS4362 evaluation board, CDB4362, as seen in Figure 42. The CS4362 does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.
5.5
Interpolation Filter
5.3
Recommended Power-up Sequence
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control port is reset to its default settings and VQ will remain low. 2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the Stand-Alone power-up sequence. The control port will be accessible at this time. If Control Port operation is desired, write the CPEN bit prior to the completion of the Stand-Alone power-up sequence, approximately 512 LRCK cycles in Sin-
To accommodate the increasingly complex requirements of digital audio systems, the CS4362 incorporates selectable interpolation filters for each mode of operation. A "fast" and a "slow" roll-off filter is available in each of Single, Double, and Quad Speed modes. These filters have been designed to accommodate a variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the control port section for more details). When in stand-alone mode, only the "fast" roll-off filter is available. Filter specifications can be found in Section 1, and filter response plots can be found in Figures 9 to 32.
27
CS4362
5.6 Clock Source Selection 6. CONTROL PORT INTERFACE
The control port is used to load all the internal settings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The CS4362 has MAP auto increment capability, enabled by the INCR bit in the MAP register, which is the MSB. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.
The CS4362 has two serial clock and two left/right clock inputs. The SDINxCLK bits in the control port allow the user to set which SCLK/LRCK pair is used to latch the data for each SDINx pin. The clocks applied to LRCK1 and LRCK2 must be derived from the same MCLK and must be exact frequency multiples of each other as specified in the "Switching Characteristics" on page 8. When using both SCLK1/LRCK1 and SCLK2/LRCK2, if either SCLK/LRCK pair loses synchronization then both SCLK/LRCK pairs will go through a retime period where the device is re-evaluating clock ratios. During the retime period all DAC pairs are temporarily inactive, outputs are muted, and the mute control pins will go active according to the MUTEC bits. If unused, SCLK2 and LRCK2 should be tied static low and SDINx bits should all be set to SCLK1/LRCK1. In stand-alone mode all DAC pairs use SCLK1 and LRCK1 for timing and SCLK2/LRCK2 should be tied to ground.
6.1
Enabling the Control Port
On the CS4362 the control port pins are shared with stand-alone configuration pins. To enable the control port, the user must set the CPEN bit. This is done by performing a Two-Wire or SPI write. Once the control port is enabled, these pins are dedicated to control port functionality. To prevent audible artifacts the CPEN bit (see Section 3.1.1) should be set prior to the completion of the Stand-Alone power-up sequence, approximately 1024 LRCK cycles. Writing this bit will halt the Stand-Alone power-up sequence and initialize the control port to its default settings. Note, the CP_EN bit can be set any time after RST goes high; however, setting this bit after the Stand-Alone powerup sequence has completed can cause audible artifacts.
5.7
Using DSD mode
In stand-alone mode, DSD operation is selected by holding DSD_EN(LRCK1) high and applying the DSD data and clocks to the appropriate pins. The M2:0 pins set the expected DSD rate and MCLK ratio. In control-port mode the FM bits set the device into DSD mode (DSD_EN pin is not required to be held high). The DIF register then controls the expected DSD rate and MCLK ratio. During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except LRCK1 in Stand-Alone mode). When the DSD related pins are not being used they should either be tied static low, or remain active with clocks (except M3 in Stand-Alone mode).
6.2
Format Selection
The control port has 2 formats: SPI and Two-Wire, with the CS4362 operating as a slave device. If Two-Wire operation is desired, AD0/CS should be tied to VLC or GND. If the CS4362 ever detects a high to low transition on AD0/CS after power-up and after the control port is activated , SPI format will be selected.
28
CS4362
6.3 Two-Wire Format
address. The eighth bit of the address byte is the R/W bit (high for a read). The contents of the register pointed to by the MAP will be output after the chip address. To read multiple registers, continue providing a clock and issue an ACK after each byte. To end the transaction, send a STOP condition.
In Two-Wire Format, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with a clock to data relationship as shown in Figure 7. The receiving device should send an acknowledge (ACK) after each byte received. There is no CS pin. Pin AD0 forms the partial chip address and should be tied to VLC or GND as required. The upper 6 bits of the 7 bit address field must be 001000. Note: MCLK is required during all two-wire transactions. The Two-Wire format is compatible with the I2C protocol. Please see reference 4 for further details.
6.4
SPI Format
In SPI format, CS is the CS4362 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller and the chip address is 0010000. CS, CCLK and CDIN are all inputs and data is clocked in on the rising edge of CCLK. Note that the CS4362 is write-only when in SPI format.
6.3.1
Writing in Two-Wire Format
To communicate with the CS4362, initiate a START condition of the bus. Next, send the chip address. The eighth bit of the address byte is the R/W bit (low for a write). The next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. To write multiple registers, continue providing a clock and data, waiting for the CS4362 to acknowledge between each byte. To end the transaction, send a STOP condition.
6.4.1
Writing in SPI
6.3.2
Reading in Two-Wire Format
To communicate with the CS4362, initiate a START condition of the bus. Next, send the chip
Figure 8 shows the operation of the control port in SPI format. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address and must be 0010000. The eighth bit is a read/write indicator (R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into register designated by the MAP. To write multiple registers, keep CS low and continue providing clocks on CCLK. End the read transaction by setting CS high.
Note 1
SDA
001000
ADDR AD0
R/W
ACK
DATA 1-8
ACK
DATA 1-8
ACK
SCL Start Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 1. Control Port Timing, Two-Wire Format
29
CS4362
CS CCLK CHIP ADDRESS CDIN
0010000
R/W
MAP
MSB
DATA
LSB
byte 1 MAP = Memory Address Pointer
byte n
Figure 8. Control Port Timing, SPI Format
6.5
Memory Address Pointer (MAP)
7 INCR 0 6 Reserved 0 5 Reserved 0 4 MAP4 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0
6.5.1
INCR (AUTO MAP INCREMENT ENABLE)
Default = `0' 0 - Disabled 1 - Enabled
6.5.2
MAP4-0 (MEMORY ADDRESS POINTER)
Default = `00000'
30
CS4362
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 9. Single Speed (fast) Stopband Rejection
0
Figure 10. Single Speed (fast) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 11. Single Speed (fast) Transition Band (detail)
Figure 12. Single Speed (fast) Passband Ripple
0
0
20
20
Amplitude (dB)
40
60
Amplitude (dB)
0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1
40
60
80
80
100
100
120
120
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 13. Single Speed (slow) Stopband Rejection
Figure 14. Single Speed (slow) Transition Band
31
CS4362
0
0.02
1
0.015
2
0.01
3
0.005
Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.02
0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 15. Single Speed (slow) Transition Band (detail)
Figure 16. Single Speed (slow) Passband Ripple
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 17. Double Speed (fast) Stopband Rejection
0
Figure 18. Double Speed (fast) Transition Band
0.02
1
0.015
2
0.01
3
Amplitude (dB)
5
Amplitude (dB)
4
0.005
0
6
0.005
7
0.01
8
9
0.015
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 19. Double Speed (fast) Transition Band (detail)
Figure 20. Double Speed (fast) Passband Ripple
32
CS4362
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 21. Double Speed (slow) Stopband Rejection
0
Figure 22. Double Speed (slow) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15 0.2 Frequency(normalized to Fs)
0.25
0.3
0.35
Figure 23. Double Speed (slow) Transition Band (detail)
0
Figure 24. Double Speed (slow) Passband Ripple
0
20
20
40 Amplitude (dB)
Amplitude (dB)
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 25. Quad Speed (fast) Stopband Rejection
Figure 26. Quad Speed (fast) Transition Band
33
CS4362
0
0.2
1
0.15
2
0.1
3
0.05
Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.05
7
0.1
8
0.15
9
0.2
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0
0.05
0.1 0.15 Frequency(normalized to Fs)
0.2
0.25
Figure 27. Quad Speed (fast) Transition Band (detail)
Figure 28. Quad Speed (fast) Passband Ripple
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.1
0.2
0.3
0.4 0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
0.9
Figure 29. Quad Speed (slow) Stopband Rejection
0
Figure 30. Quad Speed (slow) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.02
0.04 0.06 0.08 Frequency(normalized to Fs)
0.1
0.12
Figure 31. Quad Speed (slow) Transition Band (detail)
Figure 32. Quad Speed (slow) Passband Ripple
34
CS4362
LRCK SCLK
Left Channel
Right Channel
SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 33. Format 0 - Left Justified up to 24-bit Data
LRCK SCLK
Left Channel
Right Channel
SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 34. Format 1 - I2S up to 24-bit Data
LRCK
Left Channel
Right Channel
SCLK
SDINx
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 35. Format 2 - Right Justified 16-bit Data
LRCK
Left Channel
Right Channel
SCLK
SDINx
0
23 22 21 20 19 18
76543210
23 22 21 20 19 18
76543210
32 clocks
Figure 36. Format 3 - Right Justified 24-bit Data
35
CS4362
LRCK
Left Channel
Right Channel
SCLK
SDINx
10
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 37. Format 4 - Right Justified 20-bit Data
LRCK
Left Channel
Right Channel
SCLK
SDINx
10
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 38. Format 5 - Right Justified 18-bit Data
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 39. De-Emphasis Curve
L Channel Pair x Control R
DAC
AOUTAx+ AOUTAx-
SDINx
DAC
AOUTBx+ AOUTBx-
Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, or 3)
36
CS4362
Left Channel Audio Data
A Channel Volume Control
MUTE
Aout Ax
SDINx
Right Channel Audio Data
B Channel Volume Control
MUTE
AoutBx
Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, or 3)
Figure 42. Recommended Output Filter
37
CS4362
7. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
8. REFERENCES
1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB4392 Evaluation Board Datasheet 3. "Design Notes for a 2-Pole Filter with Differential Input" by Steven Green. Cirrus Logic Application Note AN48 4. "The I2C-Bus Specification: Version 2.0" Philips Semiconductors, December 1998. http://www.semiconductors.philips.com
38
CS4362
9. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
INCHES NOM 0.055 0.004 0.009 0.354 0.28 0.354 0.28 0.020 0.24 4 MILLIMETERS NOM 1.40 0.10 0.22 9.0 BSC 7.0 BSC 9.0 BSC 7.0 BSC 0.50 BSC 0.60 4
MIN --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000 * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS022
DIM A A1 B D D1 E E1 e* L
MAX 0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000
MIN --0.05 0.17 8.70 6.90 8.70 6.90 0.40 0.45 0.00
MAX 1.60 0.15 0.27 9.30 7.10 9.30 7.10 0.60 0.75 7.00
39

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