View USBLC6-2_354491.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
USBLC6-2
VERY LOW CAPACITANCE ESD PROTECTION
ASD
(Application Specific Devices)
MAIN APPLICATIONS USB2.0 ports at 480Mbps (high speed) and USB OTG ports Backwards Compatible with USB1.1 Low and full speed Ethernet port: 10/100Mb/s SIM card protection Video line protection Portable and mobile electronics DESCRIPTION The USBLC6-2P6 and USBLC6-2SC6 are two monolithic Application Specific Devices dedicated to ESD protection of high speed interfaces such as USB2.0, Ethernet links and Video lines. The very low line capacitance secures a high level of signal integrity without compromising in protection sensitive chips against the most stringent characterized ESD strikes. FEATURES 2 data lines protection Protects VBUS Very low capacitance: 3.5pF max Very low leakage current: 1A max SOT-666 and SOT23-6L packages RoHS compliant BENEFITS Very low capacitance between lines to GND for optimized data integrity and speed Ultra low PCB space consuming: 2.9mm max for SOT-666 package and 9mm max for SOT23-6L package Enhanced ESD protection: IEC61000-4-2 level 4 compliance guaranteed at device level, hence greater immunity at system level ESD protection of VBUS. Allows ESD current flowing to Ground when ESD event occurs on data line High reliability offered by monolithic integration Very low leakage current for longer operation of battery powered devices Fast response time Consistant D+/D- signal balance - Best capacitance matching tolerance I/O to GND of 0.04pF - Compliance with USB2.0 requirement (<1pF) SOT23-6L USBLC6-2SC6 SOT-666 USBLC6-2P6
Table 1: Order Codes Part Number USBLC6-2SC6 USBLC6-2P6
Marking UL26 F
Figure 1: Functional Diagram
I/O1
1
6
I/O1
GND
2
5
VBUS
I/O2
3
4
I/O2
COMPLIES WITH THE FOLLOWING STANDARDS: IEC61000-4-2 level 4: 15kV (air discharge) 8kV (contact discharge)
June 2005
REV. 2
1/11
USBLC6-2
Table 2: Absolute Ratings Symbol VPP Tstg Tj TL Parameter At device level: IEC61000-4-2 air discharge IEC61000-4-2 contact discharge MIL STD883C-Method 3015-6 Value 15 15 25 -55 to +150 125 260 Unit
Peak pulse voltage
kV
Storage temperature range Maximum junction temperature Lead solder temperature (10 seconds duration)
C C C
Table 3: Electrical Characteristics (Tamb = 25C) Symbol VRM IRM VBR VF Parameter Reverse stand-off voltage Leakage current Breakdown voltage between VBUS and GND Forward voltage VRM = 5V IF = 1mA IF = 10mA IPP = 1A, tp = 8/20s Any I/O pin to GND IPP = 5A, tp = 8/20s Any I/O pin to GND V = 0V F = 1MHz any I/O pin to GND 2.5 6 1.1 12 17 3.5 pF 0.04 Capacitance between I/O V = 0V F = 1MHz between I/O, GND not connected 1.2 1.7 pF 0.04 Test Conditions Value Min. Typ. Max. 5 1 Unit V A V V V V
VCL
Clamping voltage
Ci/o-GND Ci/o-GND Ci/o-i/o Ci/o-i/o
Capacitance between I/O and GND
2/11
USBLC6-2
Figure 2: Capacitance versus line voltage (typical values)
C(pF)
3.0
CO=I/O-GND
Figure 3: Line capacitance versus frequency (typical values)
C(pF)
2.8 2.6 2.4 2.2
VOSC=30mVRMS Tj=25C VLINE=0V to 3.3V
2.5
F=1MHz VOSC=30mVRMS Tj=25C
2.0
2.0 1.8 1.6 1.4
1.5
Cj=I/O-I/O
1.2 1.0 0.8 0.6 0.4
1.0
0.5
Data line voltage (V)
0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.2 0.0 1 10
F(MHz)
100 1000
Figure 4: Relative variation of leakage current versus junction temperature (typical values)
IRM[Tj] / IRM[Tj=25C]
100
VBUS=5V
Figure 5: Frequency response
0.00 S21(dB) -5.00
-10.00
10
-15.00
Tj(C)
1 25 50 75 100 125
F(Hz)
-20.00 100.0k 1.0M 10.0M 100.0M 1.0G
3/11
USBLC6-2
TECHNICAL INFORMATION 1. SURGE PROTECTION The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follow : VCL+ = VBUS + VF for positive surge VCL- = - VF for negative surge with: VF = VT + Rd.Ip (VF forward drop voltage) / (VT threshold voltage) We assume that the value of the dynamic resistance of the clamping diode is typically: Rd = 0.5 and VT = 1.2V. For an IEC61000-4-2 surge Level 4 (Contact Discharge: Vg=8kV, Rg=330), VBUS = +5V, and if in first approximation, we assume that : Ip = Vg / Rg = 24A. So, we find: VCL+ = +17V VCL- = -12V Note: the calculations do not take into account phenomena due to parasitic inductances. 2. SURGE PROTECTION APPLICATION EXAMPLE If we consider that the connections from the pin VBUS to VCC and from GND to PCB GND are done by two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances Lw of these tracks are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the voltage VCL has an extra value equal to Lw.dI/dt. The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be : VCL+ = +17 + 144 = 161V VCL- = -12 - 144 = -156V We can reduce as much as possible these phenomena with simple layout optimization. It's the reason why some recommendations have to be followed (see paragraph "How to ensure a good ESD protection"). Figure 6: ESD behavior; parasitic phenomena due to unsuitable layout
VCL+
183V
ESD SURGE
VBUS
Lw +VCC VF Lw di dt
Lw di dt POSITIVE SURGE
VCC+VF I/O
tr=1ns t
VI/O Lw di dt
di VCL+ = VBUS+VF+Lw dt surge >0 di surge <0 VCL- = -VF-Lw dt
tr=1ns t
-VF -Lw di dt NEGATIVE SURGE
GND
-178V
VCL-
4/11
USBLC6-2
3. HOW TO ENSURE A GOOD ESD PROTECTION While the USBLC6-2 provides a high immunity to ESD surge, an efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from the VBUS pin to the power supply +VCC and from the GND pin to GND must be as short as possible to avoid overvoltages due to parasitic phenomena (see figure 6). It's often harder to connect the power supply near to the USBLC6-2 unlike the ground thanks to the ground plane that allows a short connection. To ensure the same efficiency for positive surges when the connections can't be short enough, we recommend to put close to the USBLC6-2, between VBUS and ground, a capacitance of 100nF to prevent from these kinds of overvoltage disturbances (see figure 7). The add of this capacitance will allow a better protection by providing during surge a constant voltage. The figures 8, 9 and 10 show the improvement of the ESD protection according to the recommendations described above. Figure 7: ESD behavior: optimized layout and add of a capacitance of 100nF Figure 8: ESD behavior: measurements conditions (with coupling capacitance)
ESD SURGE
VCL+
ESD SURGE Lw
REF2=+VCC
C=100nF
t
TEST BOARD
POSITIVE SURGE
USBLC6-2SC6
I/O
VCL+ = VCC+VF surge >0
VI/O
t
+5V
VCL- = -VF
surge <0
NEGATIVE SURGE
REF1=GND
VCL-
C=100nF
Figure 9: Remaining voltage after the USBLC6-2 during positive ESD surge
Figure 10: Remaining voltage after USBLC6-2 during negative ESD surge
Vin
the
Vin
Vout
Vout
IMPORTANT: A main precaution to take is to put the protection device closer to the disturbance source (generally the connector). Note: The measurements have been done with the USBLC6-2 in open circuit.
5/11
USBLC6-2
4. CROSSTALK BEHAVIOR 4.1. Crosstalk phenomena Figure 11: Crosstalk phenomena
RG1 Line 1 1 VG1 + 12VG2
VG1 RG2 Line 2
RL1
VG2
RL2
2VG2 + 21VG1
DRIVERS
RECEIVERS
The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (12 or 21) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k). Figure 12: Analog crosstalk measurements
TRACKING GENERATOR TEST BOARD
USBLC6-2SC6
SPECTRUM ANALYSER
50
Vg
50 Vin
C=100nF
Vout
VBUS
Figure 12 gives the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240MHz) the effect on disturbed line is less than -55 dB (please see figure 13). Figure 13: Analog crosstalk results
Analog Crosstalk APLAC 7.91 User: ST Microelectronics Jan 12 2005
0.00 dB -30.00
-60.00
As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. The frequency response (figure 5) gives attenuation information and shows that the USBLC6-2 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable signals like GSM (900MHz) frequencies, for instance.
-90.00
-120.00 100.0k
1.0M
10.0M 100.0M f/Hz
1.0G
Attenuation
6/11
USBLC6-2
5. APPLICATION EXAMPLES Figure 14: USB2.0 port application diagram using USBLC6-2
+ 3.3V DEVICEUPSTREAM RPU TRANSCEIVER
SW2
VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS -
+ 5V
USB connector
Protecting Bus Switch
HUBDOWNSTREAM TRANSCEIVER
SW1
VBUS D+
DRS RS
VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS -
GND
RS RS RPD RPD
GND TX LS/FS + TX LS/FS -
USBLC6-2SC6
+ 3.3V DEVICEUPSTREAM RPU TRANSCEIVER
SW2
VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS -
SW1
USB connector
VBUS D+
DRS RS
RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS -
GND
RS
USBLC6-4SC6
GND TX LS/FS +
USBLC6-2P6
RS RPD RPD
TX LS/FS -
Mode Low Speed LS Full Speed FS High Speed HS
SW1 Open Closed
SW2 Closed Open
Closed then open Open
Figure 15: T1/E1/Ethernet protection
+VCC
USBLC6-2SC6
Tx
SMP75-8
100nF
DATA TRANSCEIVER
+VCC
USBLC6-2SC6
Rx
SMP75-8
100nF
7/11
USBLC6-2
6. PSPICE MODEL Figure 16 shows the PSPICE model of one USBLC6-2 cell. In this model, the diodes are defined by the PSPICE parameters given in figure 17. Figure 16: PSPICE model
LI/O D+in
RI/O MODEL = Dlow MODEL = Dhigh
RI/O
LI/O D+out
LGND GND
RGND
MODEL = Dzener
RI/O
LI/O VBUS
MODEL = Dlow LI/O D-in RI/O
MODEL = Dhigh RI/O LI/O D-out
Note: This simulation model is available only for an ambient temperature of 27C. Figure 17: PSPICE parameters Figure 18: considerations USBLC6-2 PCB layout
Dlow BV CJ0 IBV M RS VJ TT 50 0.9p 1m 0.3333 0.2 0.6 0.1u
Dhigh 50 2.0p 1m 0.3333 0.52 0.6 0.1u
Dzener 7.3 40p 1m 0.3333 0.84 0.6 0.1u
LI/O RI/O LGND RGND
750p 110m 550p 60m
D+in
1
D+out
VBUS
GND D-in
CBUS = 100nF
USBLC6-2
D-out
8/11
USBLC6-2
Figure 19: Ordering Information Scheme
USB
Product Designation Low capacitance Breakdown Voltage 6 = 6 Volts Number of lines protected 2 = 2 lines Packages SC6 = SOT23-6L P6 = SOT-666
LC
6-2
xxx
Figure 20: SOT-666 Package Mechanical Data DIMENSIONS REF.
bp
Millimeters Min.
Max.
Inches Min. Max.
A
D E
0.50 0.17 0.08 1.50 1.10
0.60 0.27 0.18 1.70 1.30
0.020 0.007 0.003 0.060 0.043
0.024 0.011 0.007 0.067 0.051
bp
A Lp He
c
U
D E e e1 He Lp
1.00 typ. 0.50 typ. 1.50 0.10 1.70 0.30
0.040 typ. 0.020 typ. 0.059 0.004 0.067 0.012
e1 e
Figure 21: Foot Print Dimensions (in millimeters)
0.5
1.16
0.43
0.3
2.75
9/11
USBLC6-2
Figure 22: SOT23-6L Package Mechanical Data
A E
DIMENSIONS REF. A Millimeters Min. 0.90 0 0.90 0.35 0.09 2.80 1.50 0.95 2.60 0.10 0 3.00 0.102 0.60 0.004 10 0 Typ. Max. 0.10 Min. 0 1.45 0.035 1.30 0.035 0.50 0.014 0.20 0.004 3.05 0.110 1.75 0.059 0.037 0.118 0.024 10 Inches Typ. Max. 0.057 0.004 0.051 0.02 0.008 0.120 0.069
e B e D
A1 A2 b C
A2
D E e
c
A1
H L
L H
Figure 23: Foot Print Dimensions (in millimeters)
0.60
1.20
0.95 3.50 2.30 1.10
Table 4: Ordering Information Ordering code USBLC6-2SC6 USBLC6-2P6 Marking UL26 F Package SOT23-6L SOT-666 Weight 16.7 mg 2.9 mg Base qty 3000 3000 Delivery mode Tape & reel Tape & reel
Table 5: Revision History Date 14-Mar-2005 07-Jun-2005 Revision 1 2 First issue. Format change to figure 3; no content changed. Description of Changes
10/11
USBLC6-2
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
11/11

▲Up To Search▲

Price & Availability of USBLC6-2

	To Download USBLC6-2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .