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Final Electrical Specifications LT1720 Dual, 4.5ns, Single Supply 3V/5V Comparator with Rail-to-Rail Outputs September 1998 FEATURES s s s s DESCRIPTION The LT (R)1720 is an UltraFastTM dual comparator optimized for single supply operation, with a supply voltage range of 2.7V to 6V. The input voltage range extends from 100mV below ground to 1.2V below the supply voltage. Internal hysteresis makes the LT1720 easy to use even with slow moving input signals. The rail-to-rail outputs directly interface to TTL and CMOS. Alternatively the symmetric output drive can be harnessed for analog applications or easy translation to other single supply logic levels. The LT1720 is available in the 8-pin SO package; three pins per comparator plus power and ground. The LT1720 is ideal for systems where small size and low power are paramount. The pinout of the LT1720 minimizes parasitic effects by placing the most sensitive inputs (inverting) away from the outputs, shielded by the power rails. , LTC and LT are registered trademarks of Linear Technology Corporation. UltraFast is a trademark of Linear Technology Corporation. s s s UltraFast: 4.5ns at 20mV Overdrive 7ns at 5mV Overdrive Low Power: 4mA per Comparator Optimized for 3V and 5V Operation Input Voltage Range Extends 100mV Below Negative Rail TTL/CMOS Compatible Rail-to-Rail Outputs Internal Hysteresis with Specified Limits Low Dynamic Current Drain; 15A/(V-MHz), Dominated by Load In Most Circuits APPLICATIONS s s s s s s Crystal Oscillator Circuits Window Comparators Threshold Detectors/Discriminators Line Receivers Zero-Crossing Detectors High Speed Sampling Circuits TYPICAL APPLICATION 2.7V to 6V Crystal Oscillator with TTL/CMOS Output 2.7V TO 6V 2k 1MHz-10MHz CRYSTAL (AT-CUT) 220 GROUND CASE OUTPUT DELAY (ns) 620 5 4 3 2 FALLING EDGE (tPDHL) 8 7 6 RISING EDGE (tPDLH) TJ = 25C VSTEP = 100mV VCC = 5V CLOAD = 10pF Propagation Delay vs Overdrive + C1 1/2 LT1720 - 2k 0.068F 1720 TA01 1 0 0 10 20 30 OVERDRIVE (mV) 40 50 1720 TA02 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U U U 1 LT1720 ABSOLUTE MAXIMUM RATINGS (Note 9) PACKAGE/ORDER INFORMATION TOP VIEW +IN A 1 -IN A 2 -IN B 3 +IN B 4 8 7 6 5 VCC OUT A OUT B GND Supply Voltage, VCC to GND ...................................... 7V Input Current ...................................................... 10mA Output Current (Continuous) ............................. 20mA Operating Temperature Range C Grade .................................................. 0C to 70C I Grade............................................... - 40C to 85C Junction Temperature ........................................... 150C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C ORDER PART NUMBER LT1720CS8 LT1720IS8 S8 PART MARKING 1720 1720I S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150C, JA = 200C/ W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS VCC = 5V, VCM = 1V, COUT = 10pF, TA = 25C, VOVERDRIVE = 20mV, unless otherwise specified. SYMBOL VCC VCMR VTRIP+ VTRIP- VOS VHYST VOS/T IB IOS CMRR PSRR AV VOH VOL ICC PARAMETER Supply Voltage Input Voltage Range Input Trip Points Input Offset Voltage Input Hysteresis Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Common Mode Rejection Ratio Power Supply Rejection Ratio Voltage Gain Output High Voltage Output Low Voltage Supply Current (Per Comparator) (Note 2) (Note 3) (Note 4) IO = - 4mA, VIN = VTRIP+ + 10mV IO = 10mA, VIN = VTRIP - 10mV VCC = 5V q - CONDITIONS MIN 2.7 - 0.1 TYP MAX 6 VCC - 1.2 5.5 2.0 UNITS V V mV mV mV mV mV V/C A A dB dB V (Note 1) (Note 1) q - 2.0 - 5.5 1.0 q q 3.0 4.5 5.0 0 0.4 (Note 1) 2.0 -4 3.5 10 q q 55 65 VCC - 0.4 70 80 q q 0.4 4.5 7.0 4 6 4.5 6.5 8.0 10 13 1.5 VCC = 3V q tPD20 tPD5 tPD tSKEW tr tf Propagation Delay Propagation Delay Differential Propagation Delay Propagation Delay Skew Output Rise Time Output Fall Time VOVERDRIVE = 20mV (Note 5) q VOVERDRIVE = 5mV (Notes 5, 6) q 7 0.3 1.0 2.5 2.2 (Note 7) Between Channels (Note 8) Between t PD+/tPD- 2 U W U U WW W V mA mA mA mA ns ns ns ns ns ns ns ns LT1720 ELECTRICAL CHARACTERISTICS The q denotes specifications that apply over the full operating temperature range. Note 1: The LT1720 comparators include internal hysteresis. The trip points are the input voltage needed to change the output state in each direction. The offset voltage is defined as the average of VTRIP+ and VTRIP-, while the hysteresis voltage is the difference of these two. Note 2: The common mode rejection ratio is measured with VCC = 5V and is defined as the change in offset voltage measured from VCM = - 0.1V to VCM = 3.8V, divided by 3.9V. Note 3: The power supply rejection ratio is measured with VCM = 1V and is defined as the change in offset voltage measured from VCC = 2.7V to VCC = 6V, divided by 3.3V. Note 4: Because of internal hysteresis, there is no small-signal region in which to measure gain. Proper operation of internal circuity is ensured by measuring VOH and VOL with only 10mV of overdrive. Note 5: Propagation delay measurements made with 100mV steps. Overdrive is measured relative to VTRIP. Note 6: t PD cannot be measured in automatic handling equipment with low values of overdrive. The LT1720 is 100% tested with a 100mV step and 20mV overdrive. Correlation tests have shown that t PD limits can be guaranteed with this test, if additional DC tests are performed to guarantee that all internal bias conditions are correct. Note 7: Differential propagation delay is defined as: t PD = |tPDA - t PDB| Note 8: Propagation Delay Skew is defined as: tSKEW = |tPDLH - tPDHL| Note 9: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. PIN FUNCTIONS +IN A (Pin 1): Noninverting Input of Comparator A. -IN A (Pin 2): Inverting Input of Comparator A. -IN B (Pin 3): Inverting Input of Comparator B. +IN B (Pin 4): Noninverting Input of Comparator B. GND (Pin 5): Ground. OUT B (Pin 6): Output of Comparator B. OUT A (Pin 7): Output of Comparator A. VCC (Pin 8): Positive Supply Voltage. TYPICAL PERFORMANCE CHARACTERISTICS Input Offset and Trip Voltages vs Supply Voltage 3 VTRIP+ VOS AND TRIP VOLTAGE (mV) 2 1 DELAY (ns) VOS 0 -1 -2 -3 2.5 5.0 TJ = 25C VSTEP = 100mV OVERDRIVE = 20mV CLOAD = 10pF DELAY (ns) VTRIP- TJ = 25C VCM = 1V 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.5 6.0 4.0 2.5 3.0 FALLING EDGE (tPDHL) UW U U U Propagation Delay vs VCC 9 8 7 6 4.5 RISING EDGE (tPDLH) Propagation Delay vs Load Capacitance TJ = 25C VSTEP = 100mV OVERDRIVE = 20mV VCC = 5V RISING EDGE (tPDLH) 5 4 3 2 1 FALLING EDGE (tPDHL) 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.5 6.0 0 0 10 20 40 30 OUTPUT LOAD CAPACITANCE (pF) 50 1720 G03 1720 G01 1720 G02 3 LT1720 TEST CIRCUITS VTRIP Test Circuit 1/4 LTC203 BANDWIDTH-LIMITED TRIANGLE WAVE ~ 1kHz, VCM 7.5V VCC 50k 0.1F 10nF 1F 1 8 - VCM 11 10 1/2 LT1112 + 1000 x VHYST 10k 1/4 LTC203 14 15 3 2 1000 x VTRIP+ + 50 50 DUT 1/2 LT1720 16 9 200k - 6 7 1/4 LTC203 1/4 LTC203 1000 x VOS 10k 1/4 LTC203 1/4 LTC203 3 1/2 LT1638 100k 100k 1 8 + 2 14 15 1000 x VTRIP- 10nF 2.4k 16 9 1F 100k 100k 1/2 LT1638 0.15F 6 7 11 10 - + NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM 15V. 200k PULL-DOWN PROTECTS LTC203 LOGIC INPUTS WHEN DUT IS NOT POWERED 0V -3V 4 - + - 1/2 LT1112 1/4 LTC203 1/4 LTC203 1720 TC Response Time Test Circuit +VCC - VCM -100mV 0V + 25 25 50k 50 0.01F 10 x SCOPE PROBE (CIN 10pF) DUT 1/2 LT1720 - 0.01F 0.1F PULSE IN 130 2N3866 V1* -VCM 50 400 750 *V1 = -1000 * (OVERDRIVE + VTRIP+) NOTE: RISING EDGE TEST SHOWN. FOR FALLING EDGE, REVERSE LT1720 INPUTS -5V 1720 TC02 LT1720 APPLICATIONS INFORMATION Input Voltage Considerations The LT1720 is specified for a common mode range of -100mV to 3.8V when used with a single 5V supply. A more general consideration is that the common mode range is -100mV below ground to 1.2V below VCC. The criterion for this common mode limit is that the output still responds correctly to a small differential input signal. Also, if one input is within the common mode limit, the other input signal can go outside the common mode limits, up to the absolute maximum limits, and the output will retain the correct polarity. When either input signal falls below the negative common mode limit, the internal PN diode formed with the substrate can turn on, resulting in significant current flow through the die. An external Schottky clamp diode between the input and the negative rail can speed up recovery from negative overdrive by preventing the substrate diode from turning on. When both input signals are below the negative common mode limit, phase reversal protection circuitry prevents false output inversion to at least - 400mV common mode. However, the offset and hysteresis in this mode will increase dramatically, to as much as 15mV each. The input bias currents will also increase. When both input signals are above the positive common mode limit, the input stage will get debiased and the output polarity will be random. However, the internal hysteresis will hold the output to a valid logic level, and because the biasing of the two comparators are completely independent, there will be no impact on the other comparator. When at least one of the inputs returns to within the common mode limits, recovery from this state will take as long as 1s. The input stage is protected against damage from large differential signals, up to and beyond a differential voltage equal to the supply voltage, limited only by the absolute maximum currents noted. The propagation delay does not increase significantly when driven with large differential voltages, but with low levels of overdrive, an apparent increase may be seen with large source resistances due to an RC delay caused by the 2pF typical input capacitance. Input Bias Current Input bias current is measured with both inputs held at 1V. As with any PNP differential input stage, the LT1720 bias current flows out of the device. It will go to zero on the higher of the two inputs and double on the lower of the two inputs. With more than two diode drops of differential input voltage, the LT1720's input protection circuitry activates, and current out of the lower input will increase an additional 30% and there will be a small bias current into the higher of the two input pins, of 4A or less. High Speed Design Considerations Application of high speed comparators is often plagued by oscillations. The LT1720 has 4mV of internal hysteresis, which will prevent oscillations as long as parasitic output to input feedback is kept below 4mV. However, with the 2V/ns slew rate of the LT1720 outputs, a 4mV step can be created at a 100 input source with only 0.02pF of output to input coupling. The LT1720's pinout has been arranged to minimize problems by placing the most sensitive inputs (inverting) away from the outputs, shielded by the power rails. The input and output traces of the circuit board should also be separated, and the requisite level of isolation is readily achieved if a topside ground plane runs between the outputs and the inputs. For multilayer boards where the ground plane is internal, a topside ground or supply trace should be run between the inputs and outputs. The supply bypass should include an adjacent 0.01F ceramic capacitor and a 2.2F tantalum capacitor no farther than 5cm away; use more capacitance if driving more than 4mA loads. To prevent oscillations, it is helpful to balance the impedance at the inverting and noninverting inputs; source impedances should be kept low, preferably 1k or less. The outputs of the LT1720 are capable of very high slew rates. To prevent overshoot, ringing and other problems with transmission line effects, keep the output traces shorter than 10cm, or be sure to terminate the lines to maintain signal integrity. The LT1720 can drive DC terminations of 250 or more, but lower characteristic impedance traces can be used with series termination or AC termination topologies. U W U U 5 LT1720 APPLICATIONS INFORMATION Hysteresis The LT1720 includes internal hysteresis, which makes it easier to use than other comparable speed comparators. The exact amount of hysteresis will vary from part to part as indicated in the specifications table. The hysteresis level will also vary slightly with changes in supply voltage and common mode voltage. If a comparator is used to detect a threshold crossing in one direction only, that trip point will be all that matters. Therefore, a stable offset voltage with an unpredictable level of hysteresis, as seen in many competing comparators, is useless. The LT1720 is many times better than prior comparators in these regards. In fact, the CMRR and PSRR tests are performed by checking for changes in either trip point to the limits indicated in the specifications table. Because the offset voltage is the average of the trip points, the CMRR and PSRR of the offset voltage is therefore guaranteed to be at least as good as those limits. This more stringent test also puts a limit on the common mode and power supply dependence of the hysteresis voltage. Additional hysteresis may be added externally. The rail-torail outputs of the LT1720 make this more predictable than with TTL output comparators due to the LT1720's small variability of VOH (output high voltage). VTRIP Test Circuit The input trip points test circuit uses a 1kHz triangle wave to repeatedly trip the LT1720. The output is fed to a switched-capacitor stage that samples the slowly moving triangle wave which is fed to the LT1720 through a 1000:1 divider. Simple Crystal Oscillator The Crystal Oscillator shown on the front page of this data sheet operates from 2.7V to 6V with a simple AT-cut crystal from 1MHz to 10MHz using one comparator of an LT1720. As the power is applied, the circuit remains off until the LT1720 bias circuits activate, at a typical VCC of 2V to 2.2V (25C), at which point the desired frequency output is generated. 50% Duty Cycle Crystal Oscillator If a 50% duty cycle is required, the circuit shown in Figure 1 uses the other half of the LT1720 and an op amp configured as a differential integrator to drive the duty 0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 1000 800 OUTPUT SKEW (ps) 6 U W U U cycle to precisely 50%. Again, the circuit operates from 2.7V to 6 V, and the skew between the edges of the two outputs are shown in Figure 2. There is a slight duty cycle dependence on comparator loading, so equal capacitive and resistive loading should be used in critical applications. Another variation of this circuit would be to create nonstandard duty cycles, either fixed or electronically variable, by adding additional fixed or variable inputs to the LT1636 input nodes through suitably scaled resistors. Voltage-Controlled Clock Skew A tuning voltage of 0V to 2V creates approximately 10ns of skew between two output clocks. Refer to the circuit shown in Figure 3 which operates from 2.7V to 6V. 2.7V TO 6V 2k 1MHz-10MHz CRYSTAL (AT-CUT) 220 620 + - GROUND CASE OUTPUT 100k 2k 0.068F 680 0.1F A1 LT1636 C1 1/2 LT1720 + 0.1F - + C2 1/2 LT1720 100k OUTPUT 1710 F01 - Figure 1 600 400 200 1720 F02 Figure 2 SI PLIFIED SCHE ATIC W OUTPUT 1720 SS VCC 150 -IN 150 +IN GND W LT1720 7 LT1720 TYPICAL APPLICATION CLOCK INPUT VCC 2.7V TO 6V 10ns TRIM "FIXED" + A1 LT1077 L1** VCC 2.2F 6.2M* VC 1.82M* 200pF + VIN LT1317 SW FB GND + 1.1M 100k = 1N4148 = 74HC04 * 1% FILM RESISTOR ** SUMIDA CD43-100 POLYSTYRENE, 5% RELATED PARTS PART NUMBER LT1016 LT1116 LT1394 LT1671 DESCRIPTION UltraFast Precision Comparator 12ns Single Supply Ground-Sensing Comparator 7ns, UltraFast, Single Supply Comparator 60ns, Low Power, Single Supply Comparator COMMENTS Industry Standard 10ns Comparator Single Supply Version of LT1016 6mA Single Supply Comparator 450A Single Supply Comparator 8 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U + C1 1/2 LT1720 Q VCC 2.5k FIXED OUTPUT - 2k 2.5k* 2k* 14k 2.5k "SKEWED" 12pF MV-209 VARACTOR DIODE 0.005F 36pF + C2 1/2 LT1720 Q SKEWED OUTPUT - 1M 0.1F 1M 47F INPUT 0V TO 2V 10ns SKEW - 1720 F03 Figure 3. Voltage-Controlled Clock Skew 1720i LT/TP 0998 4K * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 1998 |
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