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| PD - 9.1222 IRFI1310G HEXFET(R) Power MOSFET Advanced Process Technology Ultra Low On-Resistance Isolated Package High Voltage Isolation = 2.5KVRMS Sink to Lead Creepage Dist. = 4.8mm Repetitive Avalanche Rated 175C Operating Temperature Description Fourth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The TO-220 Fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. The moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The Fullpak is mounted to a heatsink using a single clip or by a single screw fixing. VDSS = 100V RDS(on) = 0.04 ID = 22A Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Collector Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw. Max. 22 15 88 48 0.32 20 120 22 4.8 5.5 -55 to + 175 300 (1.6mm from case) 10 lbf*in (1.1N*m) Units A W W/C V mJ A mJ V/ns C Thermal Resistance Parameter RJC RJA Junction-to-Case Junction-to-Ambient Min. ---- Typ. ---- ---- Max. 3.1 ---- Units C/W 65 Revision 0 IRFI1310G Electrical Characteristics @ T = 25C (unless otherwise specified) J V(BR)DSS V(BR)DSS/TJ RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. 100 --- --- 2.0 12 --- --- --- --- --- --- --- --- --- --- --- Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 0.04 VGS = 10V, ID = 13A 4.0 V VDS = VGS, ID = 250A --- S VDS = 50V, ID = 25A 25 VDS = 100V, VGS = 0V A 250 VDS = 80V, VGS = 0V, TJ = 150C 100 VGS = 20V nA -100 VGS = -20V 110 ID = 25A 18 nC VDS = 80V 42 VGS = 10V, See Fig. 6 and 13 --- VDD = 50V --- ID = 25A ns --- RG = 9.1 --- RD = 2.0, See Fig. 10 Between lead, --- 4.5 --- 6mm (0.25in.) nH from package --- 7.5 --- and center of die contact --- 2500 --- VGS = 0V --- 630 --- pF VDS = 25V --- 130 --- = 1.0MHz, See Fig. 5 Typ. --- 0.10 --- --- --- --- --- --- --- --- --- --- 13 77 82 64 Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units --- --- --- --- --- --- --- --- 140 0.79 22 A 88 2.5 210 1.2 V ns C Conditions MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 13A, VGS = 0V TJ = 25C, IF = 25A di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) ISD 25A, di/dt 170A/s, VDD V(BR)DSS, TJ 175C Pulse width 300s; duty cycle 2%. t=60s, =60Hz VDD = 25V, starting TJ = 25C, L = 1.0mH RG = 25, IAS = 13A. (See Figure 12) IRFI1310G 1000 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 100 0 I , Drain-to-Source Current (A) D I , Drain-to-Source Current (A) D VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 100 10 0 10 10 4.5V 4.5V 1 0.1 1 20s PULSE WIDTH TC = 25C 10 100 1 0.1 1 20s PULSE WIDTH TC = 175C 10 100 V , Drain-to-Source Voltage (V) DS VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics, TC = 25oC Fig 2. Typical Output Characteristics, TC = 175oC R DS(on) , Drain-to-Source On Resistance (Normalized) 1000 3.0 ID = 25A 2.5 I D , D ra in-to-So urce Current (A ) T J = 2 5C 100 2.0 TJ = 1 7 5C 1.5 10 1.0 0.5 1 4 5 6 7 V DS = 50V 2 0 s P U L S E W ID TH 8 9 10 0.0 -6 0 -4 0 -20 0 20 40 60 VGS = 10V 80 100 120 140 160 180 V G S , G a te-to-S o urce V olta ge (V ) TJ , Junction Temperature (C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature IRFI1310G 4 00 0 , Gate-to-Source Voltage (V) V GS = 0V, f = 1MHz C iss = C gs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd 20 I D = 25A V DS = 80V V DS = 50V V DS = 20V 16 C, Capacitance (pF) 3 00 0 Ciss 12 2 00 0 Coss 1 00 0 8 GS 4 Crss 0 1 10 10 0 0 0 30 60 V FOR TEST CIRCUIT SEE FIGURE 13 90 120 V DS, Drain-to-Source Voltage (V) QG , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000 1000 ISD , Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY RDS(on) 100 ID , Drain Current (A) 100 TJ = 175C TJ = 25C 10 100s 10 1ms 10ms 1 0 0.5 1 1.5 VGS = 0V 2 2.5 1 1 T C = 25C T J = 175C Single Pulse 10 100ms 100 1000 VSD , Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area IRFI1310G VDS 25 RD VGS RG D.U.T. VDD ID, Drain Current (Amps) 20 10 V Pulse Width 1 s Duty Factor 0.1 % 15 Fig 10a. Switching Time Test Circuit 10 5 0 25 50 75 100 125 150 175 TC , Case Temperature (C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig 10b. Switching Time Waveforms 10 T herm al R es pons e (Z th JC ) D = 0 .5 0 1 0.20 0.10 0.05 0.1 0.02 0.01 PDM t 0.01 S IN G LE P U LS E (TH E RM A L R E S PO N S E) N ote s: 1. D u ty fa ct or D = t 1 /t 2 1 t2 0.001 0.00001 2. P e ak T J = P D M x Z thJ C + T C 0.0001 0.001 0.01 0.1 1 10 t 1 , R e c ta n g u la r P u ls e D u ra tio n (s e c ) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case IRFI1310G 300 EAS , Single Pulse Avalanche Energy (mJ) TOP 250 ID 5.3A 9.2A BOTTOM 13A 10 V 200 Fig 12a. Unclamped Inductive Test Circuit 150 100 50 0 VDD = 25V 25 50 75 100 125 150 175 Starting TJ , Juntion Temperature (C) Fig 12b. Unclamped Inductive Waveforms Fig 12c. Maximum Avalanche Energy Vs. Drain Current 10 V Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit Appendix A: Figure 14, Peak Diode Recovery dv/dt Test Circuit Appendix B: Package Outline Mechanical Drawing Appendix C: Part Marking Information IRFI1310G Peak Diode Recovery dv/dt Test Circuit D.U.T Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD * * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS IRFI1310G Package Outline TO-220 Full-Pak Part Marking Information TO-220 Full-Pak WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: (44) 0883 713215 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 3L1, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: 6172 37066 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: (39) 1145 10111 IR FAR EAST: K&H Bldg., 2F, 3-30-4 Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo 171 Tel: (03)3983 0641 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, 0316 Tel: 65 221 8371 Data and specifications subject to change without notice. |
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