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CS5101 Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters
The CS5101 is a bipolar monolithic secondary side post regulator (SSPR) which provides tight regulation of multiple output voltages in AC-DC or DC-DC converters. Leading edge pulse width modulation is used with the CS5101. The CS5101 is designed to operate over an 8.0 V to 45 V supply voltage (VCC) range and up to a 75 V drive voltage (VC). The CS5101 features include a totem pole output with 1.5 A peak output current capability, externally programmable overcurrent protection, an on chip 2.0% precision 5.0 V reference, internally compensated error amplifier, externally synchronized switching frequency, and a power switch drain voltage monitor. It is available in a 14 lead plastic DIP or a 16 lead wide body SO package. Features * 1.5 A Peak Output (Grounded Totem Pole) * 8.0 V to 75 V Gate Drive Voltage * 8.0 V to 45 V Supply Voltage * 300 ns Propagation Delay * 1.0% Error Amplifier Reference Voltage * Lossless Turn On and Turn Off * Sleep Mode: < 100 A * Overcurrent Protection with Dedicated Differential Amp * Synchronization to External Clock * External Power Switch Drain Voltage Monitor
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DIP-14 N SUFFIX CASE 646 1 SO-16L DW SUFFIX CASE 751G 1
14
16
PIN CONNECTIONS AND MARKING DIAGRAMS
1 SYNC VCC VREF LGND VFB COMP RAMP DIP-14 1 SYNC VCC VREF DGND AGND VFB COMP RAMP 16 VD VC VG PGND PGND IS COMP IS- IS+ 14 VD VC VG PGND IS COMP IS- IS+
SO-16L A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device CS5101EN14 CS5101EDW16 CS5101EDWR16 Package DIP-14 SO-16L Shipping 25 Units/Rail 46 Units/Rail
CS5101 AWLYYWW AWLYYWW CS5101
SO-16L 1000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2001
1
February, 2001 - Rev. 4
Publication Order Number: CS5101/D
CS5101
VSY L1 CR4
1
TR
3
Q1
4 5
R10
VOUT
6
CR5 R5 R6
R8
R11
R13 + C6
R9
R12
R14
GND CR1 + R1 R2 CR3 R7
C5
VSYNC VCC R3 CR2 VREF LGND VFB COMP + C1 C2 R4 RAMP
VD VC VG C4
CS5101 SSPR
PGND IS COMP IS- IS+
2
C3 CR
Figure 1. Application Diagram ABSOLUTE MAXIMUM RATINGS*
Rating Power Supply Voltage, VCC VSYNC and Output Supply Voltages, VC, VG, VSYNC, VD VIS+, VIS- (VCC - 4.0 V, up to 24 V) VREF, VFB, VCOMP, VRAMP, VISCOMP Operating Junction Temperature, TJ Operating Temperature Range Storage Temperature Range Output Energy (Capacitive Load Per Cycle) ESD Human Body Lead Temperature Soldering 1. 10 second maximum 2. 60 second maximum above 183C *The maximum package power dissipation must be observed. Wave Solder (through hole styles only)(Note 1.) Reflow (SMD styles only) (Note 2.) Value -0.3 to 45 -0.3 to 75 -0.3 to 24 -0.3 to 10 -40 to +150 -40 to +85 -65 to +150 5.0 2.0 260 peak 230 peak Unit V V V V C C C J kV C C
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CS5101
ELECTRICAL CHARACTERISTICS: (-40C TA 85C, -40C TJ 150C, 10 V < VCC < 45 V, 8.0 V < VC < 75 V; unless otherwise specified.)
Characteristic Error Amplifier Input Voltage Initial Accuracy Input Voltage Input Bias Current Open Loop Gain Unity Gain Bandwidth Output Sink Current Output Source Current VCOMP High VCOMP Low PSRR Voltage Reference Output Voltage Initial Accuracy Output Voltage Line Regulation Load Regulation Current Limit VREF-OK FAULT V VREF-OK V VREF-OK Hysteresis Current Sense Amplifier IS COMP High V IS COMP Low V Source Current Sink Current Open Loop Gain CMRR PSRR Unity Gain Bandwidth Input Offset Voltage Input Bias Currents Input Offset Current (IS+, IS-) Input Signal Voltage Range Note 3. IS+ = 5.0 V, IS- = IS COMP IS+ = 0 V, IS- = IS COMP IS+ = 5.0 V, IS- = 0 V IS- = 5.0 V, IS+ = 0 V 1.5 V VCOMP 4.5 V, RL = 4.0 k Note 3. 10 V < VCC < 45 V, Note 3. 1.5 V VCOMP 4.5 V, RL = 4.0 k, Note 3. VIS+ = 2.5 V, VIS- = VISCOMP VIS+ = VIS- = 0 V, IIS flows out of pins - 4.7 0.5 2.0 10 60 60 60 0.5 -8.0 - -250 -0.3 5.0 1.0 10 20 80 80 80 0.8 0 20 0 - 5.3 1.3 - - - - - - 8.0 250 250 VCC - 4.0 V V mA mA dB dB dB MHz mV nA nA V VCC = 15 V, T = 25C, Note 3. 0 A < IREF < 8.0 mA 10 V < VCC < 45 V, IREF = 0 A 0 A < IREF < 8.0 mA VREF = 4.8 V VSYNC = 5.0 V, VREF = VLOAD VSYNC = 5.0 V, VREF = VLOAD - 4.9 4.8 - - 10 4.10 4.30 40 5.0 5.0 10 20 50 4.40 4.50 100 5.1 5.2 60 60 - 4.60 4.80 250 V V mV mV mA V V mV VFB = VCOMP, VCC = 15 V, T = 25C, Note 3. VFB = VCOMP, includes line and temp VFB = 0 V, IVFB flows out of pin 1.5 V < VCOMP < 3.0 V 1.5 V < VCOMP < 3.0 V, Note 3. VCOMP = 2.0 V, VFB = 2.2 V VCOMP = 2.0 V, VFB = 1.8 V VFB = 1.8 V VFB = 2.2 V 10 V < VCC < 45 V, VFB = VCOMP, Note 3. 1.98 1.94 - 60 0.7 2.0 2.0 3.3 0.85 60 2.00 2.00 - 70 1.0 8.0 6.0 3.5 1.0 70 2.02 2.06 500 - - - - 3.7 1.15 - V V nA dB MHz mA mA V V dB Test Conditions Min Typ Max Unit
3. Guaranteed by design. Not 100% tested in production.
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CS5101
ELECTRICAL CHARACTERISTICS: (continued) (-40C TA 85C, -40C TJ 150C, 10 V < VCC < 45 V,
8.0 V < VC < 75 V; unless otherwise specified.) Characteristic RAMP/SYNC Generator RAMP Source Current Initial Accuracy RAMP Source Current RAMP Sink Current RAMP Peak Voltage RAMP Valley Voltage RAMP Dynamic Range RAMP Sleep Threshold Voltage SYNC Threshold SYNC Input Bias Current Output Stage VG, High VG, Low VG Rise Time VG Fall Time VG Resistance to GND VD Resistance to GND General ICC, Operating ICC in UVL ICC in Sleep Mode High ICC in Sleep Mode Low IC, Operating High IC, Operating Low UVLO Start Voltage UVLO Stop Voltage UVLO Hysteresis Leading Edge, tDELAY Trailing Edge, tDELAY VSYNC = 5.0 V VCC = 6.0 V VRAMP = 0 V, VCC = 45 V VRAMP = 0 V, VCC = 10 V VSYNC = 5.0 V, VFB = VIS- = 0 V, VC = 75 V VSYNC = 5.0 V, VFB = VIS- = 0 V, VC = 8.0 V - - - VSYNC = 2.5 V to VG = 8.0 V VSYNC = 2.5 V to VG = 2.0 V - - - - - - 7.4 6.4 0.8 - - 12 300 80 20 4.0 3.0 8.0 7.0 1.0 280 750 18 500 200 50 8.0 6.0 9.2 8.3 1.2 - - mA A A A mA mA V V V ns ns VSYNC = 5.0 V, IVG = 200 mA, VC - VG VSYNC = 0 V, IVG = 200 mA Switch VSYNC High, CG = 1.0 nF, VCC = 15 V, measure 2.0 V to 8.0 V Switch VSYNC Low, CG = 1.0 nF, VCC = 15 V, measure 8.0 V to 2.0 V Remove supplies, VG = 10 V Remove supplies, VD = 10 V - - - - - 500 1.6 0.9 30 40 50 1500 2.5 1.5 75 100 100 - V V ns ns k VSYNC = 5.0 V, VRAMP = 2.5 V, T = 25C, Note 4. VSYNC = 5.0 V, VRAMP = 2.5 V VSYNC = 0 V, VRAMP = 2.5 V VSYNC = 5.0 V VSYNC = 0 V VRAMPDR = VRAMPPK - VRAMPVY VRAMP @ VREF < 2.0 V VSYNC @ VRAMP > 2.5 V VSYNC = 0 V, ISYNC flows out of pin 0.18 0.16 1.0 3.3 1.4 1.7 0.3 2.3 - 0.20 0.20 4.0 3.5 1.5 2.0 0.6 2.5 1.0 0.22 0.24 - 3.7 1.6 2.3 1.0 2.7 20 mA mA mA V V V V V A Test Conditions Min Typ Max Unit
4. Guaranteed by design. Not 100% tested in production.
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CS5101
PACKAGE PIN DESCRIPTION
PACKAGE LEAD # DIP-14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 - - SO-16L 1 2 3 - 6 7 8 9 10 11 12, 13 14 15 16 5 4 LEAD SYMBOL SYNC VCC VREF LGND VFB COMP RAMP IS+ IS- IS COMP PGND VG VC VD AGND DGND Synchronization input. Logic supply (10 V to 45 V). 5.0 V voltage reference. Logic level ground (analog and digital ground tied). Error amplifier inverting input. Error amplifier output and compensation. RAMP programmable with the external capacitor. Current sense amplifier non-inverting input. Current sense amplifier inverting input. Current sense amplifier compensation and output. Power ground. External power switch gate drive. Output power stage supply voltage (8.0 V to 75 V). External FET DRAIN voltage monitor. Analog ground. Digital ground. FUNCTION
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CS5101
CIRCUIT DESCRIPTION
VCC VCC REF VREF LGND 5.0 V OK + UVL + -
+ - 8.0 V/7.0 V
VD VC + SLEEP - 0.7 V + -
Q1
VG
Q2
PGND
IS COMP
VCC 5.0 V VFB - EA +
+ - 2.0 V
24.6 k
5.0 V IS
- +
IS- IS+
10 k
10 k
- BUF +
+ 2.4 V -
VC
- - + PWM +
5.0 V
Q3
COMP
5.0 V
Q I = 200 A RAMP 5.0 V + RAMP -
+ - 1.65 V + - 1.5 V
S
5.0 V 0.7 V + - -
VCC-OK
LATCH Q R 5.0 V +
+
Q4
G1
REF_OK
5.0 V + SYNC - G2
-
+ - 4.5 V/4.4 V
VCC
SYNC
+ - 2.5 V
Figure 2. Block Diagram Theory of Operation SYNC Function
The CS5101 is designed to regulate voltages in multiple output power supplies. Functionally, it is similar to a magnetic amplifier, operating as a switch with a delayed turn-on. It can be used with both single ended and dual ended topologies. The VFB voltage is monitored by the error amplifier EA. It is compared to an internal reference voltage and the amplified differential signal is fed through an inverting amplifier into the buffer, BUF. The buffered signal is compared at the PWM comparator with the ramp voltage generated by capacitor CR. When the ramp voltage VR, exceeds the control voltage VC, the output of the PWM comparator goes high, latching its state through the LATCH, the output stage transistor Q1 turns on, and the external power switch, usually an N-FET, turns on.
The SYNC circuit is activated at time t1 (Figure 3) when the voltage at the SYNC pin exceeds the threshold level (2.5V) of the SYNC comparator. The external ramp capacitor CR is allowed to charge through the internal current source I (200 A). At time t2, the ramp voltage intersects with the control voltage VC and the output of the PWM comparator goes high, turning on the output stage and the external power switch. At the same time, the PWM comparator is latched by the RS latch, LATCH.
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CS5101
1
VSY 0V VSY
RAMP Function
2
VSY + VD
VC VRAMP VDS
The value of the ramp capacitor CR is based on the switching frequency of the regulator and the maximum duty cycle of the secondary pulse VSY. If the RAMP pin is pulled externally to 0.3 V or below, the SSPR is disabled. Current drawn by the IC is reduced to less than 100 A, and the IC is in SLEEP mode.
FAULT Function
3
0V VSY VD
VS
4
0V
VSY - VOUT
VL1
VOUT + VD
5
0V
VSY + VC
VD
VG
6
0V t1 t2 t3 t4 t1
Ground Level (Gate doesn't go below GND)
Figure 3. Waveforms for CS5101. The Number to the Left of Each Curve Refers to a Node On the Application Diagram on Page 2.
The logic state of the LATCH can be changed only when both the voltage level of the trailing edge of the power pulse at the SYNC pin is less than the threshold voltage of the SYNC comparator (2.5 V) and the RAMP voltage is less than the threshold voltage of the RAMP comparator (1.65 V). On the negative going transition of the secondary side pulse VSY, gate G2 output goes high, resetting the latch at time t3. Capacitor CR is discharged through transistor Q4. CR's output goes low disabling the output stage, and the external power switch (an N-FET) is turned off.
The voltage at the VCC pin is monitored by the undervoltage lockout comparator with hysteresis. When VCC falls below the UVL threshold, the 5.0 V reference and all the circuitry running off of it is disabled. Under this condition the supply current is reduced to less than 500 A. The VCC supply voltage is further monitored by the VCC_OK comparator. When VCC is reduced below VREF - 0.7 V, a fault signal is sent to gate G1. This fault signal, which determines if VCC is absent, works in conjunction with the ramp signal to disable the output, but only after the current cycle has finished and the RS latch is reset. Therefore this fault will not cause the output to turn off during the middle of an on pulse, but rather will utilize lossless turn-off. This feature protects the FET from overvoltage stress. This is accomplished through gate G1 by driving transistor Q4 on. An additional fault signal is derived from the REF_OK comparator. VREF is monitored so to disable the output through gate G1 when the VREF voltage falls below the OK threshold. As in the VCC_OK fault, the REF_OK fault disables the output after the current cycle has been completed. The fault logic will operate normally only when VREF voltage is within the specification limits of REF_OK.
DRAIN Function
The drain pin, VD monitors the voltage on the drain of the power switch and derives energy from it to keep the output stage in an off state when VC or VCC is below the minimum specified voltage.
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CS5101
S1 8.0 V - 45 V C1 1.0 F SW SPST R1 100 k
V1 100 kHz 0 V to 5.0 V Square Wave
R2 100 k
VSYNC VCC VREF LGND VFB COMP RAMP
CS5101
VD VC VG C3 1.0 nF
C2 0.1 F
R3 5.0 k
PGND IS COMP IS- IS+ R4 2.2 k
R6 10 k
C4 0.1 F
R7 10 k C5 680 pF
R5 10 k
Figure 4. CS5101 Bench Test on DIP-14 Package
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CS5101
PACKAGE DIMENSIONS
DIP-14 N SUFFIX CASE 646-04 ISSUE M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.740 0.240 0.260 0.160 0.180 0.015 0.020 0.040 0.060 0.100 BSC 0.052 0.072 0.008 0.012 0.115 0.135 0.290 0.310 --10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 4.06 4.57 0.38 0.51 1.02 1.52 2.54 BSC 1.32 1.83 0.20 0.30 2.92 3.43 7.37 7.87 --10 _ 0.51 1.02
14
8
B
1 7
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
DIM A B C D F G H J K L M N
SO-16L DW SUFFIX CASE 751G-03 ISSUE B
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1 16X
8
B TA
S
B B
S
0.25
M
A
h X 45 _
SEATING PLANE
M
8X
0.25
E
A1
14X
e
T
C
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical DIP-14 23 105 SO-16L 48 85 Unit C/W C/W
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L
CS5101
Notes
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CS5101
Notes
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CS5101
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CS5101/D

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