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L6382D5
POWER MANAGEMENT UNIT FOR MICROCONTROLLED BALLAST
1

FEATURES
INTEGRATED HIGH-VOLTAGE START-UP 4 DRIVERS FOR PFC, HALF-BRIDGE & PREHEATING MOSFETS FULLY INTEGRATE POWER MANAGEMENT FOR ALL OPERATING MODES 5V MICROCONTROLLER COMPATIBLE INTERNAL TWO POINT Vcc REGULATOR OVER-CURRENT PROTECTION WITH DIGITAL OUTPUT SIGNAL CROSS-CONDUCTION PROTECTION (INTERLOCKING) UNDER VOLTAGE LOCK OUT INTEGRATED BOOTSTRAP DIODE
Figure 1. Package
SO20

Table 1. Order Codes
Part Number L6382D5 L6382D5TR Package SO20 tube SO20 in Tape & Reel

2
APPLICATIONS
DIMMABLE/NON-DIMMABLE BALLST
plications managed by a microcontroller. It allows the designer to use the same ballast circuit for different lamp wattage/type by simply changing the C software. The digital input pins - able to receive signals up to 400KHz - are connected to level shifters that provide the control signals to their relevant drivers; in particular the L6382D5 embeds one driver for the PFC pre-regulator stage, two drivers for the ballast
3
DESCRIPTION
Designed in High-voltage BCD Off-line technology, the L6382D5 is provided with 4 inputs pin and a high voltage start-up generator conceived for apFigure 2. Block Diagram
HVSU TPR
BOOTSTRAP >600V HIGH "ON"
BOOT
IC BIAS
P UVLO
VOLTAGE START-UP "OFF" GENERATOR
R
Q
LEVEL SHIFT 5V 600V
HSD
HSG OUT
LSD
S
Q RQ
LSG
ON
PSW
5V SUPPLY
L O G I C
TPR
S
Q
CSO
OCP
CSI
HED
HEG
PFD
DIM
PFG Vcc HSI LSI HEI PFI
REF
GND
January 2005
Rev. 1 1/14
L6382D5
half-bridge stage (High Voltage, including also the bootstrap function) and the last one to provide supplementary features like preheating of filaments supplied through isolated filaments in dimmable applications. A precise reference voltage (+5V 1%) able to provide up to 30mA is available to supply the C in operating mode. Instead, during start-up and save mode the current available at VREF is up to 10mA and it is provided by the internal high voltage start-up generator. The chip has been conceived with advanced power management logic to minimize power losses and increase the application reliability. In the half-bridge section, a patented integrated bootstrap section replaces the external bootstrap diode. The L6382D5 integrates also a function that regulates the IC supply voltage (without the need of any external charge pump) and optimizes the current consumption. Figure 3. Pin Connection (Top View)
PFI LSI HSI HEI PFG N.C. TPR GND LSG VCC
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VREF CSI CSO HEG N.C. HVSU N.C. OUT HSG BOOT
Figure 4. Typical System Block Diagram
PFC CIRCUIT
AC MAINS
HV START-UP
CHARGE PUMP REGULATOR
BOOTSTRAP
HB DRIVER
TL
PFC DRIVER
5V SUPPLY
PROTECTION
C
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Table 2. Pin Functions
N. 1 2 3 4 5 Pin PFI LSI HSI HEI PFG Function Digital input signal to control the PFC gate driver. This pin has to be connected to a 5V CMOS compatible signal. Digital input signal to control the half-bridge low side driver. This pin has to be connected to a 5V CMOS compatible signal. Digital input signal to control the half-bridge high side driver. This pin has to be connected to a 5V CMOS compatible signal. Digital input signal to control the HEG output. This pin has to be connected to a 5V CMOS compatible signal. PFC Driver Output. This pin must be connected to the PFC power MOSFET gate. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 10K resistor toward ground avoids spurious and undesired MOSFET turn-on The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 250mA sink. Not connected Input for two point regulator; by coupling the pin with a capacitor to a switching circuit, it is possible to implement a charge circuit for the Vcc. Chip ground. Current return for both the low-side gate-drive currents and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return. Low Side Driver Output. This pin must be connected to the gate of the half-bridge low side power MOSFET. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 20K resistor toward ground avoids spurious and undesired MOSFET turn-on. The totem pole output stage is able to drive power with a peak current of 120mA source and 120mA sink. Supply Voltage for the signal part of the IC and for the drivers. High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this pin and pin 13 (OUT) is fed by an internal synchronous bootstrap diode driven in phase with the low-side gate-drive. This patented structure normally replaces the external diode. High Side Driver Output. This pin must be connected to the gate of the half bridge high side power MOSFET . A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 20K resistor toward OUT pin avoids spurious and undesired MOSFET turn-on The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 120mA sink. High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground. Not connected High-voltage start-up. The current flowing into this pin charges the capacitor connected between pin Vcc and GND to start up the IC. Whilst the chip is in save mode, the generator is cycled on-off between turn-on and save mode voltages. When the chip works in operating mode the generator is shut down and it is re-enabled when the Vcc voltage falls below the UVLO threshold. According to the required VREF pin current, this pin can be connected to the rectified mains voltage either directly or through a resistor. High-voltage spacer. The pin is not connected internally to isolate the high-voltage pin and comply with safety regulations (creepage distance) on the PCB. Output for the HEI block; this driver can be used to drive the MOS employed in isolated filaments preheating. An internal 20K resistor toward ground avoids spurious and undesired MOSFET turn-on.
6 7 8
N.C. TPR GND
9
LSG
10 11
Vcc BOOT
12
HSG
13 14 15
OUT N.C. HVSU
16 17
N.C. HEG
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Table 2. Pin Functions (continued)
N. 18 Pin CSO Function Output of current sense comparator, compatible with 5V CMOS logic; during operating mode, the pin is forced low whereas whenever the OC comparator is triggered (CSI> 0.55 typ.) the pin latches high. Input of current sense comparator, it is enabled only during operating mode; when the pin voltage exceeds the internal threshold, the CSO pin is forced high and the half bridge drivers are disabled. It exits from this condition by either cycling the Vcc below the UVLO or with LGI=HGI=low simultaneously. Voltage reference. During operating mode an internal generator provides an accurate voltage reference that can be used to supply up to 30mA to an external circuit. A small film capacitor (0.22F min.), connected between this pin and GND is recommended to ensure the stability of the generator and to prevent noise from affecting the reference.
19
CSI
20
VREF
Table 3. Absolute Maximum Ratings
Symbol VCC VHVSU VBOOT VOUT ITPR(RMS) ITPR(PK) VTPR Pin 10 15 11 13 6 6 6 19 1, 2, 3, 4 9, 12, 17 5 Tstg Tj
(*) excluding operating mode
Parameter IC supply voltage (ICC = 20mA) High voltage start-up generator voltage range Floating supply voltage Floating ground voltage Maximum TPR RMS current Maximum TPR peak current Maximum TPR voltage (*) CSI input voltage Logic input voltage Operating frequency Operating frequency Storage Temperature Ambient Temperature operating range
Value Self-limited -0.3 to 600 -1 to VHVSU+VCC -1 to 600 200 600 14 -0.3 to 7 -0.3 to 7 15 to 400 15 to 600 -40 to +150 -40 to +125
Unit
V V V mA mA V V V KHz KHz C C
Table 4. Thermal Data
Symbol Rth j-amb Parameter Max. Thermal Resistance, Junction-to-ambient Value 120 Unit C/W
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Table 5. Electrical Characteristcs (Tj = 25C, VCC=12V unless otherwise specified)
Symbol Pin Parameter Test condition min. typ max UNIT
SUPPLY VOLTAGE VccON VccOFF VccSM VSMhys VREF(OFF) IvccON IvccSM 10 10 10 10 10 10 10 Turn-on voltage Turn-off voltage Save mode voltage Save mode hysteresys Reference turn-off Start-up current Save Mode consumption current (1) Ivcc Vz 10 10 Quiescent current operating mode Internal Zener in Vcc=13V; LGI=HGI=high; no load on VREF. TBD 150 12.75 13 14 9.3 13.8 0.115 7.65 150 190 230 2 14.85 15 V V V V V A A A mA V
HIGH VOLTAGE START-UP IMSS 15 15 ILSS 15 Maximum current Turn-on Voltage Leakage current off state VHVSU > 50V IHVSU=5mA VHVSU = 600V 20 TBD 40 mA V A
TWO POINT REGULATOR (TPR) PROTECTION TPRst TPR(ON) TPR(OFF) 10 10 10 7 7 7 Vcc Protection level Vcc Turn-on level Vcc Turn-off level Output voltage on state Forward Diode voltage
Operating mode Operating mode; after the first falling edge on LSG Operating mode; after the first falling edge on LSG
ITPR = 200mA
14.0 12.5 12.45
15.0 13.5 13.48 2 2 5
V V V V V A
drop @ 600mA forward current. VTPR = 13V
Leakage current off state
LSG, HEG & PFG DRIVERS VOH(LS) VOL(LS) 5, 9, 17 5, 9, 17 HIGH Output Voltage LOW Output Voltage Sink Current Capability ILSG = 10mA ILSG = 10mA LSG and PFG HEG 120 50 VCC -0.5 0.5 V V mA mA
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Table 5. Electrical Characteristcs (continued)
Symbol Pin Parameter Source Current Capability LSG HEG PFG TRISE TFALL TDELAY 5, 9, 17 5, 9, 17 Rise time Fall time Cload = 1nF Cload = 1nF Test condition min. 120 70 250 TBD TBD 300 200 250 200 20 50 10 ns ns ns ns ns ns K K K typ max UNIT mA
Propagation delay (input LSG; high to low and low to to output) high HEG; high to low and low to high PFG; high to low PFG; low to high
RB
Pull down Resistor
LSG HEG PFG
HSG DRIVER (VOLTAGES REFERRED TO OUT) VOH(HS) VOL(HS) 12 12 12 12 TRISE TFALL TDELAY RB 12 12 12 12 HIGH Output Voltage LOW Output Voltage Sink Current Capability Source Current Capability Rise time Fall time Cload = 1nF Cload = 1nF IHSG = 10 mA IHSG = 10 mA 120 120 TBD TBD 300 20 VCC -0.5 0.5 V V mA mA ns ns ns K
Propagation delay (LGI to high to low and low to high LSG) Pull down Resistor to OUT
HIGH-SIDE FLOATING GATE-DRIVER SUPPLY ILKBOOT ILKOUT RDS(on) 11 13 VBOOT current pin leakage VBOOT = 580V VOUT = 562V VLVG = HIGH at 10 mA forward current at 5V forward voltage drop 25 100 1.9 2.4 5 5 A A V mA
OUT pin leakage current Synchronous bootstrap diode on-resistance Forward Voltage Drop Forward Current
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Table 5. Electrical Characteristcs (continued)
Symbol VREF VREF 20 Reference voltage 15mA load. 15mA load, (1) 20 20 20 20 Load regulation Voltage change VREF latched protection VREF Clamp @3mA VCC from 0 to VCCON during start-up; Vcc from VREF(OFF) to 0 during shut-down; VREF<2V -3 Save mode OVERCURRENT BUFFER STAGE VCSI ICSI 19 19 Comparator Level Input Bias Current Propagation delay 18 18 DIM Normal Mode Time Out Vref enabling drivers TED LOGIC INPUT 1 to 4 1 to 4 LGI Low Level Logic Input Voltage High Level Logic Input Voltage Pull down resistor 3.7 100 1.3 V V K Time enabling drivers 65 100 4.6 10 135 s V s High output voltage Low output voltage CSO turn off to LSG low I CSO= 200A I CSO = -150A VREF0.5V 0.5 V Bandgap 0.52 0.54 0.56 500 200 V nA ns -3 IRef = -3 to +30 mA 15mA load; Vcc = 9V to 15V 3.2 1.2 4.9 4.85 -20 5 5.1 5.15 2 15 V V mV mV V V Pin Parameter Test condition min. typ max UNIT
IREF
20
Current Drive Capability
+30 +10
mA mA
Notes: 1. Specification over the -40C to +125C junction temperature range are ensured by design, characterization and statistical correlation.
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L6382D5
4
APPLICATION INFORMATION
4.1 POWER MANAGEMENT The L6382D5 has two stable states (save mode and operating mode) and two additional states that manage the Start-up and fault conditions: the Over Current Protection is a parallel asynchronous process enabled when in operating mode. Following paragraphs will describe each mode and the condition necessary to shift between them. Figure 5.
START-UP
VCCVCC>VCC(ON)
VCCSAVE MODE
VCCSHUT DOWN
VREF>4.6V & TDE>10s
LGI low for more than 100s
VCC < VCC(OFF) or VREF<3.2V
OPERATING MODE
4.1.1 START-UP mode With reference to the timing diagram of figure 6, when power is first applied to the converter, the voltage on the bulk capacitor (Vin) builds up and the HV generator is enabled to operate drawing about 10mA. This current, diminished by the IC consumption (less than 150A), charges the bypass capacitor connected between pin Vcc and ground and makes its voltage rise almost linearly. During this phase, all IC's functions are disabled except for:
the current sinking circuit on VREF pin that maintains low the voltage by keeping disabled the microcontroller connected to this pin;
the High-Voltage Start-Up (HVSU) that is ON (conductive) to charge the external capacitor on pin Vcc. As the Vcc voltage reaches the start-up threshold (14V typ.) the chip starts operating and the HV generator is switched off. Summarizing: the high-voltage start-up generator is active; VREF is disabled with additional sinking circuit on pin VREF is enabled; TPR is disabled; OCP is disabled; the drivers are disabled.
4.1.2 SAVE Mode This mode is entered after the Vcc voltage reaches the turn-on threshold; the VREF is enabled in low current source mode to supply the C connected to it, whose wake-up required current must be less than 10mA: if no switching activity is detected at LGI input, the high voltage start-up generator cycles ON-OFF keeping the Vcc voltage between VccON and VccSM.
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L6382D5
Summarizing: the high-voltage start-up generator is cycling; VREF is enabled in low source current capability (IREF 10mA); TPR circuit is disabled; OCP is disabled; the drivers are disabled. If the Vcc voltage falls below the VREF(OFF) threshold, the device enters the start-up mode. 4.1.3 OPERATING Mode After 10s in save mode and only if the votage at VREF is higher than 4.6V, on the falling edge on the HGI input, the driver are enabled as well as all the IC's functions; this is the mode correspondent to the proper lamp behaviour. Summarizing: HVSU is OFF VREF is enabled in high source current mode (IREF < 30mA) TPR circuit is enabled OCP is enabled the drivers are enabled If there is no switching activity on LGI for more than 100s, the IC returns in save mode. 4.1.4 Shut Down This state permits to manage the fault conditions in operating mode and it is entered by the occurrence on one of the following conditions: - 1. VccVcc
VCCon TPR(OFF) TPR(ON)
Vcc
VCCon VccSM VccOFF
TPR Switching
VREF
VREF
LGI
LGI
LGI
HGI
PSW
HVSU
10s
OPERATING MODE
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L6382D5
5
BLOCK DESCRIPTION
5.1 SUPPLY SECTION
PUVLO ( Power Under Voltage Lock Out): This block controls the power management of the L6382D5 ensuring the right current consumption in each operating state, the correct VREF current capability, the driver enabling and the high-voltage start-up generator switching. During Start-up the device sinks the current necessary to charge the external capacitor on pin VCC from the high voltage bus; in this state the other IC's functions are disabled and the current consumption of the whole IC is less than 150A. When the voltage on VCC pin reaches VccON, the IC enters the save mode where the PUVLO block controls Vcc between VccON and VccSM by switching ON/OFF the high voltage start-up generator. HVSU (High-Voltage Start-Up generator): a 600V internal MOS transistor structure controls the Vcc supply voltage during START UP and SAVE MODE conditions and it reduces the power losses during NORMAL MODE by switching OFF the MOS transistor. The transistor has a source current capability of up to 30mA. TPR (Two Point Regulator) & PWS: during operating mode, the TPR block controls the PSW switch in order to regulate the IC supply voltage (VCC) to a value in the range between TPR(ON) and TPR(OFF) by switching ON and OFF the PSW transistor. - Vcc > TPRst: the PSW is switched ON immediately; - TPR(ON) < Vcc < TPRst: the PSW is switched ON at the following falling edge of LGI;
- Vcc < TPR(OFF): the PSW is switched OFF at the following falling edge on LGI. When the PSW switch is OFF, the diodes build a charge pump structure so that, connecting the TPR pin to a switching voltage (through a capacitor) it is possible to supply the low voltage section of the chip without adding any further external component. The diodes and the switch are designed to withstand a peak current of at least 200mARMS. 5.2 5V REFERENCE VOLTAGE This block is used to supply the microcontroller; this source is able to supply 10mA in save mode and 30mA in normal mode; moreover, during start-up when VREF is not yet available, an additional circuit is ensures that, even sinking 3mA, the pin voltage doesn't exceed 1.2V. The reference is available until Vcc is above VREF(OFF); below that it turns off and the additional sinking circuit is enabled again. 5.3 DRIVERS
LSD (Low Side Driver): it consists of a level shifter from 5V logic signal (LGI) to Vcc MOS driving level; conceived for the half-bridge low-side power MOS, it is able to source and sink 120mA (min). HSD (Level Shifter and High Side Driver): it consists of a level shifter from 5V logic signal (HGI) to the high side gate driver input up to 600V. Conceived for the half-bridge high-side power MOS, the HSD is able to source 120mA from HSB to HSG (turn-on) and to sink 120mA to HSS (turn-off). PFD (Power Factor Driver): it consists of a level shifter from 5V logic signal (PFI) to Vcc MOS driving level: the driver is able to source 120mA from Vcc to PFG (turn-on) and to sink 250mA to GND (turnoff); it is suitable to drive the MOS of the PFC pre-regulator stage. HED (Heat Driver): it consists of a level shifter from 5V logic signal (HEI) to Vcc MOS driving level; the driver is able to source 30mA from Vcc to HEG and to sink 75mA to GND and it is suitable for the filament heating when they are supplied by independent winding.

Bootstrap Circuit: it generates the supply voltage for the high side Driver (HSD). This circuit sources current from Vcc to PIN HSB when LSG in ON. A patented integrated bootstrap section replaces an
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external bootstrap diode. This section together with a bootstrap capacitor provides the bootstrap voltage to drive the high side power MOSFET. This function is achieved using a high voltage DMOS driver which is driven synchronously with the low side external power MOSFET. For a safe operation, current flow between BOOT pin and Vcc is always inhibited, even though ZVS operation may not be ensured. 5.4 INTERNAL LOGIC, OVER CURRENT PROTECTION (OCP) AND INTERLOCKING FUNCTION. The DIM (Digital Input Monitor) block manages the input signals delivered to the drivers ensuring that they are low during the described start-up procedure; the DIM block controls the L6382D5 behaviour during both save and operating modes. When the voltage on pin CSI overcomes the internal reference of 0.54V (typ.) the block latches the fault condition: in this state the OCP block forces low both HSD and LSD signals while CSO will be forced high. This condition remains latched until LSI and HSI are simultaneously low and CSI is below 0.54V. This function is suitable to implement an over current protection or hard-switching detection by using an external sense resistor. As the voltage on pin CSI can go negative, the current must be limited below 2mA by external components. Another feature of the DIM block is the internal interlocking that avoids cross-conduction in the halfbridge FET's: if by chance both HGI and LGI input's are brought high at the same time, then LSG and HSG are forced low as long as this critical condition persists.
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Figure 7. SO20 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 13.00 7.60 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.200 0.013 0.512 0.299 inch
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO20
0016022 D
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L6382D5
Table 6. Revision History
Date January 2005 Revision 1 First Issue Description of Changes
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L6382D5
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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