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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview Quad Analog Switch/ Multiplexer/Demultiplexer with Separate Analog and Digital Power Supplies MC74HC4316A 16 1 N SUFFIX PLASTIC PACKAGE CASE 648-08 High-Performance Silicon-Gate CMOS The MC74HC4316A utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF-channel leakage current. This bilateral switch/multiplexer/demultiplexer controls analog and digital voltages that may vary across the full analog power-supply range (from VCC to VEE). The HC4316A is similar in function to the metal-gate CMOS MC14016 and MC14066, and to the High-Speed CMOS HC4016A and HC4066A. Each device has four independent switches. The device control and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal-gate CMOS analog switches. Logic-level translators are provided so that the On/Off Control and Enable logic-level voltages need only be VCC and GND, while the switch is passing signals ranging between VCC and VEE. When the Enable pin (active-low) is high, all four analog switches are turned off. * * * * * * Logic-Level Translator for On/Off Control and Enable Inputs Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Diode Protection on All Inputs/Outputs Analog Power-Supply Voltage Range (VCC - VEE) = 2.0 to 12.0 Volts Digital (Control) Power-Supply Voltage Range (VCC - GND) = 2.0 to 6.0 Volts, Independent of VEE * Improved Linearity of ON Resistance * Chip Complexity: 66 FETs or 16.5 Equivalent Gates LOGIC DIAGRAM XA A ON/OFF CONTROL 1 15 LEVEL TRANSLATOR ANALOG SWITCH LEVEL TRANSLATOR ANALOG SWITCH LEVEL TRANSLATOR ANALOG SWITCH LEVEL TRANSLATOR ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 16 1 D SUFFIX SOIC PACKAGE CASE 751B-05 14 1 DT SUFFIX TSSOP PACKAGE CASE 948G-01 ORDERING INFORMATION MC74HCXXXXAN MC74HCXXXXAD MC74HCXXXXADT Plastic SOIC TSSOP PIN ASSIGNMENT XA YA YB XB B ON/OFF CONTROL C ON/OFF CONTROL ENABLE GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD YD YC XC VEE ANALOG SWITCH 2 YA FUNCTION TABLE 3 YB ANALOG OUTPUTS/INPUTS 11 YC PIN 16 = VCC PIN 8 = GND PIN 9 = VEE GND VEE Inputs On/Off Enable Control L L H X = don't care H L X State of Analog Switch On Off Off XB B ON/OFF CONTROL 4 5 XC C ON/OFF CONTROL 10 6 XD D ON/OFF CONTROL ENABLE 13 14 7 12 YD 10/95 (c) Motorola, Inc. 1995 1 REV 0 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III I III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). A VEE = GND 6.0 2 20 40 VEE = - 6.0 6.0 4 40 160 NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). VCC = 2.0 V 0 1000 ns VCC = 3.0 V 0 600 VCC = 4.5 V 0 500 VCC = 6.0 V 0 400 * For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* MOTOROLA DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted RECOMMENDED OPERATING CONDITIONS MC74HC4316A Symbol Symbol Symbol VCC VEE Tstg VIS VIO* VCC Vin VEE PD TL tr, tf VIS Vin ICC TA VIH VIL I Iin Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) Storage Temperature Power Dissipation in Still Air DC Current Into or Out of Any Pin DC Input Voltage (Ref. to GND) Analog Input Voltage Negative DC Supply Voltage (Ref. to GND) Positive DC Supply Voltage Input Rise and Fall Time (Control or Enable Inputs) (Figure 10) Operating Temperature, All Package Types Static or Dynamic Voltage Across Switch Digital Input Voltage (Ref. to GND) Analog Input Voltage Negative DC Supply Voltage (Ref. to GND) Positive DC Supply Voltage (Ref. to GND) Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current, Control or Enable Inputs Maximum Low-Level Voltage, Control or Enable Inputs Minimum High-Level Voltage, Control or Enable Inputs Parameter Parameter Parameter Plastic DIP SOIC Package TSSOP Package Vin = VCC or GND VIO = 0 V Vin = VCC or GND VEE = - 6.0 V Ron = Per Spec Ron = Per Spec (Ref. to GND) (Ref. to VEE) Test Conditions - 0.5 to VCC + 0.5 - 0.5 to + 7.0 - 0.5 to + 14.0 - 65 to + 150 - 7.0 to + 0.5 VEE - 0.5 to VCC + 0.5 2 GND - 6.0 VEE - 55 Min 2.0 -- Value 25 260 750 500 450 + 125 GND VCC VCC Max 1.2 6.0 VCC V 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Unit Unit mW mA _C _C _C V V V V V V V V V - 55 to 25_C 0.1 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. Guaranteed Limit v 85_C v 125_C High-Speed CMOS Logic Data DL129 -- Rev 6 1.0 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 v 1.0 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 v Unit A V V IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). * At supply voltage (V CC - V EE) approaching 2 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage operation, it is recommended that these devices only be used to control digital signals. High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol Ron Symbol Ron Ion Ioff tPLH, tPHL tPZL, tPZH tPLZ, tPHZ CPD C Maximum On-Channel Leakage Current, Any One Channel Maximum Off-Channel Leakage Current, Any One Channel Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Maximum "ON" Resistance Maximum Capacitance Parameter Parameter Vin = VIH VIS = VCC or VEE (Figure 4) Vin = VIL VIO = VCC or VEE Switch Off (Figure 3) Vin = VIH VIS = 1/2 (VCC - VEE) IS 2.0 mA * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND) DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE) Power Dissipation Capacitance (Per Switch) (Figure 13)* Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) Vin = VIH VIS = VCC to VEE IS 2.0 mA (Figures 1, 2) Vin = VIH VIS = VCC or VEE (Endpoints) IS 2.0 mA (Figures 1, 2) v v v Test Conditions Control Input = GND Analog I/O Feedthrough ON/OFF Control and Enable Inputs 3 VCC V 2.0* 45 4.5 6.0 6.0 6.0 2.0 4.5 4.5 6.0 2.0 4.5 4.5 6.0 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- -- -- - 6.0 - 6.0 0.0 0.0 - 4.5 - 6.0 0.0 0.0 - 4.5 - 6.0 0.0 0.0 - 4.5 - 6.0 VEE V - 55 to 25_C Typical @ 25C, VCC = 5.0 V 140 40 30 130 40 30 - 55 to 25_C 35 1.0 10 40 6 5 -- 160 90 90 0.1 0.1 -- 20 15 15 -- 90 70 70 Guaranteed Limit Guaranteed Limit 175 50 40 160 50 40 35 1.0 10 50 8 7 15 -- 200 110 110 -- 115 90 90 0.5 0.5 -- 25 20 20 250 60 50 200 60 50 35 1.0 10 60 9 8 1.0 1.0 -- 30 25 25 v 85_C v 125_C v 85_C v 125_C MC74HC4316A -- 140 105 105 -- 240 130 130 MOTOROLA Unit pF Unit pF ns ns ns A A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I * Limits not tested. Determined by design and verified by qualification. MOTOROLA ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) MC74HC4316A Symbol THD BW -- -- -- Total Harmonic Distortion (Figure 14) Crosstalk Between Any Two Switches (Figure 12) Feedthrough Noise, Control to Switch (Figure 7) Off-Channel Feedthrough Isolation (Figure 6) Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure 5) Parameter fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads - 3 dB RL = 50 , CL = 10 pF fin = 1 kHz, RL = 10 k, CL = 50 pF THD = THDMeasured - THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF Vin 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 , CL = 50 pF fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF v fin = 1.0 MHz, RL = 50 , CL = 10 pF fin = 1.0 MHz, RL = 50 , CL = 10 pF Test Conditions 4 RL = 10 k, CL = 10 pF VCC V 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 High-Speed CMOS Logic Data DL129 -- Rev 6 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 VEE V Limit* 25_C 0.10 0.06 0.04 - 80 - 80 - 80 - 70 - 70 - 70 - 40 - 40 - 40 - 50 - 50 - 50 30 65 100 60 130 200 150 160 160 mVPP MHz Unit dB dB % MC74HC4316A TBD TBD Figure 1a. Typical On Resistance, VCC - VEE = 2.0 V Figure 1b. Typical On Resistance, VCC - VEE = 4.5 V TBD TBD Figure 1c. Typical On Resistance, VCC - VEE = 6.0 V Figure 1d. Typical On Resistance, VCC - VEE = 9.0 V PLOTTER PROGRAMMABLE POWER SUPPLY MINI COMPUTER DC ANALYZER TBD - + DEVICE UNDER TEST ANALOG IN VCC COMMON OUT GND VEE Figure 1e. Typical On Resistance, VCC - VEE = 12.0 V High-Speed CMOS Logic Data DL129 -- Rev 6 5 Figure 2. On Resistance Test Set-Up MOTOROLA MC74HC4316A VCC VEE VCC A OFF 16 VCC VCC A O/I VEE ON 16 VCC N/C VIL 7 8 9 VEE SELECTED CONTROL INPUT VEE 7 8 9 SELECTED CONTROL INPUT VIH Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up Figure 4. Maximum On Channel Leakage Current, Test Set-Up VIS VCC 16 fin 0.1 F ON RL VCC SELECTED CONTROL INPUT VEE *Includes all probe and jig capacitance. CL* VCC RL VCC 16 TO dB METER fin 0.1 F RL OFF RL CL* TO dB METER 7 8 9 VEE 7 8 9 SELECTED CONTROL INPUT *Includes all probe and jig capacitance. Figure 5. Maximum On-Channel Bandwidth Test Set-Up Figure 6. Off-Channel Feedthrough Isolation, Test Set-Up VCC 16 TEST POINT RL SELECTED CONTROL INPUT CL* ANALOG IN tPLH 50% 50% GND tPHL ON/OFF RL 7 8 9 VEE CONTROL *Includes all probe and jig capacitance. VCC ANALOG OUT Figure 7. Feedthrough Noise, Control to Analog Out, Test Set-Up Figure 8. Propagation Delays, Analog In to Analog Out MOTOROLA 6 High-Speed CMOS Logic Data DL129 -- Rev 6 MC74HC4316A VCC 16 ANALOG I/O ON 50 pF* ANALOG O/I TEST POINT ENABLE 50% CONTROL tPZL 7 8 9 SELECTED CONTROL INPUT VCC ANALOG OUT 50% tPZH 50% *Includes all probe and jig capacitance. tPHZ 10% 90% tPLZ GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE tr tf VCC Figure 9. Propagation Delay Test Set-Up Figure 10. Propagation Delay, ON/OFF Control to Analog Out POSITION 1 WHEN TESTING tPHZ AND tPZH 1 2 VCC 1 2 CONTROL OR ENABLE 8 9 VEE ON/OFF 50 pF* POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 16 1 k TEST POINT fin 0.1 F RL VIS VCC 16 ON RL CL* ANALOG I/O OFF 7 8 9 RL VCC SELECTED CONTROL INPUT CL* TEST POINT *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set-Up Figure 12. Crosstalk Between Any Two Switches, Test Set-Up (Adjacent Channels Used) VCC A 16 N/C ON/OFF N/C 10 F fin ON RL 7 8 9 VEE CONTROL SELECTED CONTROL INPUT VEE CL* VIS VCC 16 VOS TO DISTORTION METER 7 8 9 SELECTED CONTROL INPUT VCC *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set-Up Figure 14. Total Harmonic Distortion, Test Set-Up High-Speed CMOS Logic Data DL129 -- Rev 6 7 MOTOROLA MC74HC4316A 0 - 10 - 20 - 30 dBm - 40 - 50 - 60 - 70 - 80 - 90 - 100 1.0 2.0 FREQUENCY (kHz) 3.0 DEVICE SOURCE FUNDAMENTAL FREQUENCY Figure 15. Plot, Harmonic Distortion APPLICATION INFORMATION The Enable and Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or VEE through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In the example below, the difference between VCC and VEE is twelve volts. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak-to-peak can be controlled. When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn-on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOsorbs (Motorola high current surge protectors). MOsorbs are fast turn-on devices ideally suited for precise dc protection with no inherent wear out mechanism. VCC = 6 V +6V -6 V +6V SELECTED CONTROL INPUT VEE 8 -6 V 16 ANALOG I/O ON ANALOG O/I +6V -6 V Dx VCC 16 ON Dx VEE VCC SELECTED CONTROL INPUT VEE VCC Dx Dx VEE ENABLE CONTROL INPUTS (VCC OR GND) ENABLE CONTROL INPUTS (VCC OR GND) Figure 16. Figure 17. Transient Suppressor Application MOTOROLA 8 High-Speed CMOS Logic Data DL129 -- Rev 6 MC74HC4316A VCC = 5 V +5 V ANALOG SIGNALS R* R* R* R* R* 16 ANALOG SIGNALS ANALOG SIGNALS HCT BUFFER LSTTL/ NMOS 5 6 14 15 16 ANALOG SIGNALS HC4316A TTL 7 5 6 14 15 R* = 2 TO 10 k ENABLE AND CONTROL 9 INPUTS 8 VEE = 0 TO - 6 V HC4016A VEE = 0 TO - 6 V CONTROL INPUTS 9 7 a. Using Pull-Up Resistors b. Using HCT Buffer Figure 18. LSTTL/NMOS to HCMOS Interface VCC = 12 V 12 V POWER SUPPLY R1 GND = 6 V R2 VEE = 0 V R1 = R2 VCC ANALOG INPUT SIGNAL C R3 R4 VEE R1 = R2 R3 = R4 ANALOG OUTPUT SIGNAL 12 V 0 12 VPP 1 OF 4 SWITCHES Figure 19. Switching a 0-to-12 V Signal Using a Single Power Supply (GND 0 V) CHANNEL 4 1 OF 4 SWITCHES 1 OF 4 SWITCHES COMMON I/O 1 OF 4 SWITCHES 1 OF 4 SWITCHES - INPUT 1 OF 4 SWITCHES + 0.01 F 1 2 34 CONTROL INPUTS LF356 OR EQUIVALENT OUTPUT CHANNEL 3 CHANNEL 2 CHANNEL 1 Figure 20. 4-Input Multiplexer Figure 21. Sample/Hold Amplifier High-Speed CMOS Logic Data DL129 -- Rev 6 9 MOTOROLA MC74HC4316A OUTLINE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01 B 1 8 F S C L -T - H G D 16 PL 0.25 (0.010) M SEATING PLANE K J TA M M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.229 0.244 0.010 0.019 -B - 1 8 P 8 PL 0.25 (0.010) M B M G F K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S MOTOROLA 10 High-Speed CMOS Logic Data DL129 -- Rev 6 MC74HC4316A OUTLINE DIMENSIONS DT SUFFIX TSSOP PACKAGE CASE 948G-01 ISSUE O 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E 0.15 (0.006) T U S A -V- J J1 SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 High-Speed CMOS Logic Data DL129 -- Rev 6 CODELINE 11 EEE CCC EEE CCC EEE CCC EEE CCC CCC K K1 *MC74HC4316A/D* MC74HC4316A/D MOTOROLA |
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