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| PRODUCT INFORMATION DPS 9455B Dec/2003 DPS 9455B Display Processor and Scaler with HDTV and PC Input The DPS 9455B is a single-chip digital display processor and scaler, especially designed for FPD-TV sets (LCD-TV, PDPTV) supporting HDTV signal input and deinterlacing as well as PC-signal input. The DPS 9455B is a new member of Micronas' IC family implemented in deep submicron CMOS technology. HS and VS outputs to synchronize - the ext. analog RGB/YCrCb source in the softmix mode (see display modes) - external OSD source Programmable characteristics on R, G, B, for -correction, blue-stretch, white-drive Dithering for 8 to 6-bit digital outputs Display Modes Digital mode: video from the digital input Analog mode: video/graphics/Teletext from the analog RGB/YCrCb input Softmix mode: soft mixing of the video and component input OSD signals can be inserted digitally Display Format Processing Prescaling of the input signal: horizontal scaling factor: 1.0 to 1/64 Upscaling of the output signal: horizontal scaling factor: 1 to 4 (5-zone panorama generator) Vertical scaling factor: 0.5 to 4 De-interlacing with line-doubling/ upscaling Video Inputs Digital input for 50/60 I or 50/60 P signals in ITU-656 (8 bit) or ITU-601 (16 bit) 3x8 bit YCrCb/RGB input 2 analog RGB/YCrCb inputs for Teletext, graphics, 480p, 576p, 1080i and 720p 4 built-in ADCs (8-bit) for RGB + FastBlank with 81 MHz sampling rate PC input up to XGA at 75 Hz and WXGA at 60 Hz Separate HS and VS (2x) inputs Video Processing Full 4:4:4 processing RGB-to-YCrCb conversion Brightness, contrast, saturation for analog component input Dynamic contrast improvement (DCI) Black level expander (BLE) Luma & chroma transition improvement Dynamic peaking Brightness, contrast, saturation, tint Programmable YCrCb-to-RGB matrix OSD digital RGB input (6 or 12 bit/pixel) 64 entry CLUT with 12-bit colors Picture frame and testpattern generation Half-contrast switch (0, 25%, 50%, 100%) Sync Processing 3-level sync-separation for 1080i and 720p Display Resolutions 640x480 (VGA; 4:3 panel) 852x480 (W-VGA; 16:9 panel) 800x600 (SVGA) 1024x768 (XGA) 1366x768 (W-XGA) PRODUCT INFORMATION DPS 9455B Output Interface 2x18 or 24-bit RGB output: dual-pixel mode programmable panel control signals Tuner SIF CVBS Dec/2003 Center Line In Surround Audio SL, SL MSP 34/44xy L, R Main Miscellaneous Up to 2 PWM outputs SCART Subwoofer Y/C Headphones L, R CVBS RGB, FB ITU 656 ITU 656 or ITU 601 Up to 8 general-purpose I/Os I2 DVD/STB VPC 32xy or VSP 94xy FRC 94xy* DPS 9455 L, R Line Out C interface (400 kHz) Analog YCrCb JTAG boundary scan interface 1.8 V and 3.3 V supply PMQFP144 package Digital YCrCb ITUR 656 480p - 1080i (D1 - D4) SDA 600x LVDS PC-Input VGA - WXGA * optional Fig. 1: Application example: LCD-TV with DPS 9455B and HDTV Input System Architecture Figure 2 shows the block diagram of the DPS 9455B. The device has digital outputs. In principle, the device comprises three major functional and clock domain parts. ITU Domain Input Domain Input Video Processing ITU656 ITU601 Decoder Upsampling (422-444) Line-doubling (optional) 648 MHz DTO Divider XOUT CLK20/XIN TDO TCK TMS TDI TEST CS SCL SDA RESET Xtal Oscillator Display Domain Test Controller I2C Interface The functional parts are Video input processing, Scaling, and Display processing. The clock domains are ITU domain, Input domain, and Display domain (compare the block diagram and the different shaded areas). The input and the output signals of the IC can be chosen in various configurations. CLKIN VIN HIN ITU/ 24 RGB/ YUVIN HOUT VOUT VIN2 HIN2 Sync Slicer 16 DPS 9455B LL PLL Cr/RIN1 Y/GIN1 Cb/BIN1 FBL1/HS Cr/RIN2 Y/GIN2 Cb/BIN2 FBL2/HS Source Select 4 ADCs 24 Compontent Input Component Processing RGB YCrCb Contrast Brightness Saturation Format Detection Channel Mixer Scaler and De-Interlacer lin. H/V-Scaler nonlin. H-Scaler De-Interlacing Picture Improvements LTI/CTI Peaking Blacklevel Expander Picture Settings Contrast Brightness Saturation Tint Matrix RGBOUT Pixel Mixer Gamma Dithering and Panel Controlling 36 PCK1/2 PanelCtrl 11 Digital OSD Input 6/12 bit Horizontal Expansion Picture Frame Testpattern 2 CLKF 12 2 OSDFB OSDHV OSDRGB OSDHC OSDCLK Fig. 2: Block diagram of the DPS 9455B All information and data contained in this product information are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our respective order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. Edition Dec. 17, 2003; Order No. 6251-637-1PI Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com www.micronas.com |
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