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STW81100
MULTI-BAND RF FREQUENCY SYNTHESIZER WITH INTEGRATED VCOS
DATASHEET
1

Features
Integer-N Frequency Synthesizer Dual differential integrated VCOs with automatic center frequency calibration: - Direct Output: 3280 - 3900 MHz 3800 - 4400 MHz - Internal divider by 2: 1640 - 1950 MHz 1900 - 2200 MHz - Internal divider by 4: 820 - 975 MHz 950 - 1100 MHz
Figure 1. Package
VFQFPN28
Table 1. Order Codes
Part Number STW81100AT STW81100ATR Package VFQFPN28 VFQFPN28 in Tape & Reel

Fast lock time: 150s Dual modulus prescaler (64/65) and 2 programmable counters to achieve a feedback division ratio from 4096 to 32767. Programmable reference frequency divider (9 bits) Phase frequency comparator and charge pump Programmable charge pump current Digital Lock Detector I2C bus interface with 3 bit programmable address (1100A2A1A0) 3.3V Power Supply Power down mode Small size exposed pad VFQFPN28 package 5x5x1.0mm Process: BICMOS 0.35m SiGe
tors (VCOs). Showing high performance, high integration, low power, and multi-band performances, STW81100 is a low cost one chip alternative to discrete PLL and VCOs solutions. STW81100 includes an Integer-N frequency synthesizer and two fully integrated VCOs featuring low phase noise performance and a noise floor of -153dBc/Hz. The combination of wide frequency range VCOs (thanks to center-frequency calibration over 32 sub-bands) and multiple output options (direct output, divided by 2 or divided by 4) allows to cover the 820MHz-1100MHz, the 1640MHz-2200MHz and the 3280MHz-4400MHz bands. The STW81100 is designed with STMicroelectronics advanced 0.35m SiGe process.

2
Description
3

Applications
Cellular 3G Infrastructure Equipment Other Wireless Communication Systems
The STMicroelectronics STW81100 is an integrated RF synthesizer and voltage controlled oscilla-
April 2005
Rev. 2 1/23
STW81100
Figure 2. Block Diagram
O UT BUF P OUT BUF N V DD_ PLL V SS_ PLL REF_ IN REXT REXT
VDD_OUTBUF VSS_OUTBUF
BUF
VDD_DIV4 VSS_DIV4
VCO BUF BUF
DIV4 BUF BUF BUF
DIV2 DIV2 DIV2 BUF
VSS_CP
VDD_DIV2 VSS_DIV2
REF Divider P F D VCO Divider
UP DN
VDD_CP
DIV2
DIV4
VDD_BUFVCO VSS_BUFVCO
C P
ICP
BUF
EXTVCO_INP EXTVCO_INN
LOCK_DET
EXT VCO BUF
ATPGON
IC BUS
VCO BUFF
SCL SDA
ADD0 ADD1 ADD2
VDD_VCO1 VSS_VCO1
VDD_VCO2 VSS_VCO2
VCO Calibrator
VDD_I2C VSS_I2C
VDD_ESD VSS_ESD
T EST 1
TEST2
EX T_PD
VCTRL
Figure 3. Pin Connections
EXT_PD
VDD_VCO1 VDD_DIV2 VDD_OUTBUF OUTBUFP OUTBUFN VDD_DIV4 VDD_VCO2 VDD_ESD LOCK_DET VDD_CP
VDD_I2C ATPGON VDD_BUFVCO EXTVCO_INP EXTVCO_INN VDD_PLL REF_IN TEST2
AD D2
ADD1
ADD0
SC L
QFN 28
VCTRL
SDA
2/23
TEST1
REXT
I CP
STW81100
Table 2. Pin Description
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name VDD_VCO1 VDD_DIV2 VDD_OUTBUF OUTBUFP OUTBUFN VDD_DIV4 VDD_VCO2 VDD_ESD VCTRL ICP REXT VDD_CP TEST1 LOCK_DET TEST2 REF_IN VDD_PLL EXTVCO_INN EXTVCO_INP VDD_BUFVCO ATPGON VDD_I2C EXT_PD SDA SCL ADD0 ADD1 ADD2 Description VCO power supply Divider by 2 power supply Output buffer power supply LO buffer positive output LO buffer negative output Divider by 4 power supply VCO power supply ESD positive rail power supply VCO control voltage PLL charge pump output External resistance connection for PLL charge pump Power supply for charge pump Test input 1 Lock detector Test input 2 Reference frequency input PLL digital power supply External VCO negative input External VCO positive input VCO buffer power supply SCAN mode activated I2C bus power supply Power down hardware I2CBUS data line I2CBUS clock line I2CBUS address select pin I2CBUS address select pin I2CBUS address select pin CMOS Input CMOS Bidir Schmitt triggered CMOS Input CMOS Input CMOS Input CMOS Input Used only for testing purpose CMOS Output Used only for testing purpose Open collector Open collector Observations
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STW81100
Table 3. Absolute Maximum Ratings
Symbol AVCC DVCC Tstg ESD Parameter Analog Supply voltage Digital Supply voltage Storage temperature Electrical Static Discharge - HBM - CDM-JEDEC Standard Values 0 to 4.6 0 to 4.6 +150 2 0.5 Unit V V C KV
Table 4. Operating Conditions
Symbol AVCC DVCC ICC Tamb Tj Rth j-a Parameter Analog Supply voltage Digital Supply voltage Current Consumption Operating ambient temperature Maximum junction temperature Junction to ambient package thermal resistance Multilayer JEDEC board 35 -40 Test conditions Min 3.0 3.0 Typ 3.3 3.3 Max 3.6 3.6 100 85 125 Unit V V mA C C C/W
Table 5. Digital Logic Level
Symbol Vil Vih Vhyst Vol Voh Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis Low level output voltage High level output voltage 0.85*Vdd 0.8*Vdd 0.8 0.4 Test conditions Min Typ Max 0.2*Vdd Unit V V V V V
4
Electrical Characteristcs
All Electrical Specifications are intended at 3.3V supply voltage. Table 6. Electrical Characteristcs
Symbol REFERENCE fref Reference input frequency Reference input sensitivity fcomp fstep Comparison frequency Frequency step LO direct output LO with Divider by 2 LO with Divider by 4 10 0.35 200 200 100 50 19.2 1 400 400 200 100 100 1.5 10000 10000 5000 2500 MHz Vpeak KHz KHz KHz KHz Parameter Test Condition Min Typ Max Units
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STW81100
Table 6. Electrical Characteristcs (continued)
CHARGE PUMP Symbol ICP VOCP Parameter ICP sink/source1 Output voltage compliance range Spurious2,3 Direct Output Divider by 2 Divider by 4 VCOs KvcoA VCOA sensitivity3 Sub-Band 00000 Sub-Band 01111 Sub-Band 11111 KvcoB VCOB sensitivity3 Sub-Band 00000 Sub-Band 01111 Sub-Band 11111 VCOA Pushing3 VCOB Pushing3 VCO control voltage LO Harmonic Spurious VCO current consumption VCO buffer consumption IDIV2 IDIV4 DIVIDER by 2 consumption DIVIDER by 4 consumption 25 15 18 14 0.4 85 55 35 60 35 20 105 70 50 75 45 25 7 9 135 95 65 100 60 35 10 14 3 -20 MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V V dBc mA mA mA mA Test Condition 3bit programmable 0.4 -65 -70 -70 Min Typ Max 4 Vdd-0.3 -54 -60 -66 Units mA V dBc dBc dBc
LO OUTPUT BUFFER POUT RL ILOBUF Output level Return Loss Current Consumption Matched to 50ohm DIV4 Buff DIV2 Buff Direct Output EXTERNAL VCO (Test purpose only) fINVCO PIN VINDC IEXTBUF Frequency range Input level DC Input level Current Consumption VCO Internal Buffer 3.28 0 2 15 4.4 +6 GHz dBm V mA 0 15 26 23 37 dBm dB mA mA mA
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STW81100
Table 6. Electrical Characteristcs (continued)
PLL MISCELLANEUS IPLL tLOCK Current Consumption Input Buffer, Prescaler, Digital Dividers, misc 40 KHz PLL bandwidth; within 1 ppm of frequency error 10 150 mA s
Lock up time
Notes: 1. : see relationship between ICP and REXT in the Circuit Description section (Charge Pump) 2. : Comparison frequency leakage (400KHz) and harmonics 3. : Guaranteed by design and characterization.
Table 7. Phase Noise Performance1)
Parameter In Band Phase Noise - Closed Loop2) -212 -212+20log(N)+10log(fcomp) ICP=2mA, PLL BW = 50KHz; including reference clock contribution -218+20log(N)+10log(fcomp) -224+20log(N)+10log(fcomp) dBc/Hz dBc/Hz dBc/Hz dBc/Hz Test Condition Min Typ Max Units
Normalized In Band Phase Noise Floor In Band Phase Noise Floor Direct Output In Band Phase Noise Floor Divider by 2 In Band Phase Noise Floor Divider by 4 PLL Integrated Phase Noise with Divider by 2 Integrated Phase Noise (single sided) 400Hz to 4MHz Integrated Phase Noise (single sided) 100Hz to 25MHz Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz Phase Noise @ 40 MHz VCO B Direct (3800MHz-4400MHz) - Open Loop Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10MHz Phase Noise @ 40 MHz VCO A with divider by 2 (1640MHz-1950MHz) - Open Loop Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz Phase Noise @ 20 MHz Phase Noise Floor @ 40 MHz
-39 ICP = 4mA, fcomp = 400KHz (N = 10000), PLL BW = 15KHz -38
-37 -36
dBc dBc
VCO A Direct (3280MHz-3900MHz) - Open Loop -56 -83 -105 -128 -148 -156 -55 -82 -104 -127 -147 -155 -62 -89 -111 -134 -150 -152 -153 -53 -82 -102 -125 -145 -153 -52 -79 -101 -124 -143 -152 -59 -86 -108 -131 -148 -150 -151 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
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STW81100
Table 7. (continued)
Parameter Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10MHz Phase Noise @ 20MHz Phase Noise Floor @ 40 MHz VCO A with divider by 4 (820MHz-975MHz) - Open Loop Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10MHz Phase Noise Floor @ 40 MHz VCO B with divider by 4 (950MHz-1100MHz) - Open Loop Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10MHz Phase Noise Floor @ 40 MHz
Note 1):
Test Condition
Min
Typ -61 -88 -110 -133 -150 -152 -153 -68 -95 -117 -139 -151 -153 -67 -94 -116 -138 -151 -153
Max -58 -85 -107 -130 -148 -150 -151 -65 -92 -114 -136 -149 -151 -64 -91 -113 -135 -149 -151
Units dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
VCO B with divider by 2 (1900MHz-2200MHz) - Open Loop
Note 2):
Phase Noise SSB. VCO amplitude set to maximum value [11]. The phase noise is measured with the Agilent E5052A Signal Source Analyzer. All the closed-loop performances are specified using a Reference Clock signal at 19.2 MHz with phase noise of -141dBc/Hz @1KHz offset and -146dBc/Hz @10KHz offset. All figures are guaranteed by design and characterization. Normalized PN = Measured PN - 20log(N) - 10log(fcomp) where N is the VCO divider ratio (N=B*P+A) and fcomp is the comparison frequency at the PFD input
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STW81100
5
Typical Performance Characteristics
The phase noise is measured with the Agilent E5052A Signal Source Analyzer. All the closed-loop measurements are done with fcomp=800 KHz and using a Reference Clock signal at 19.2 MHz with phase noise of -141dBc/Hz @1KHz offset and -146dBc/Hz @10KHz offset. Figure 4. VCO A (Direct output) open loop phase noise Figure 6. VCO B (Direct output) open loop phase noise
Figure 5. VCO A (Direct output) closed loop phase noise
Figure 7. VCO B (Direct output) closed loop phase noise
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STW81100
Figure 8. VCO A (Divider by 2 output) closed loop phase noise Figure 10. VCO B (Divider by 2 output) closed loop phase noise
Figure 9. VCO A (Divider by 4 output) closed loop phase noise
Figure 11. VCO B (Divider by 4 output) closed loop phase noise
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STW81100
6
General Description
The block diagram of Figure 2 shows the different blocks, which have been integrated to achieve an integer-N PLL frequency synthesizer. The STW81100 consists of 2 internal low-noise VCOs with buffer blocks, a divider by 2, a divider by 4, a low-noise PFD (Phase Frequency Detector), a precise charge pump, a 9-bit programmable reference divider, two programmable counters and a dual-modulus prescaler. The A-counter (6 bits) and B counter (9 bits) counters, in conjunction with the dual modulus prescaler P/ P+1 (64/65), implement an N integer divider, where N = B*P +A. The division ratio of both reference and VCO dividers is controlled through an I2C bus interface. All devices operate with a power supply of 3.3 V and can be powered down when not in use.
7
Circuit Description
7.1 Reference input stage The reference input stage is shown in Figure 12. The resistor network feeds a DC bias at the Fref input while the inverter used as the frequency reference buffer is AC coupled. Figure 12. Reference Frequency Input Buffer
VDD
Fref
INV
BUF
Power Down
7.2 Reference Divider The 9-bit programmable reference counter allows the input reference frequency to be divided to produce the input clock to the PFD. The division ratio is programmed through the I2C bus interface. 7.3 Prescaler The dual-modulus prescaler 64/65 takes the CML clock from the VCO buffer and divides it down to a manageable frequency for the CMOS A and B counters. It is based on a synchronous 4/5 core which division ratio depends on the state of the modulus input. 7.4 A and B Counters The A (6 bits) and B (9 bits) counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the reference frequency divided by the reference division ratio. Thus, the division ratio and the VCO output frequency are given by these formulas: N=BxP+A
( B P + A ) F ref F VCO = ----------------------------------------R
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STW81100
where: - FVCO: output frequency of VCO. - P: modulus of dual modulus prescaler. - B: division ratio of the main counter. - A: division ratio of the swallow counter. - Fref: input reference frequency. - R: division ratio of reference counter. - N: division ratio of PLL For a correct work of the VCO divider, B must be strictly higher than A. A can take any value ranging from 0 to 63. The range of the N number can vary from 4096 to 32767. Figure 13. VCO Divider Diagram
VCOBUF-
Prescaler 64/65
VCOBUF+ modulus To PFD
6 bit A counter
9 bit B counter
7.5 Phase frequency detector (PFD) The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer function. Figure 6 is a simplified schematic of the PFD. Figure 14. PDF Diagram
VDD
D FF
Fref
Up
R Delay R D FF Down ABL
Fref VDD
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STW81100
7.6 Lock Detect This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found to be shorter than the fixed delay (roughly 5 ns). Lock Detect signal is high when the PLL is locked. When Power Down is activated, Lock Detect is let to high level (Lock Detect consumes current only during PLL transients). 7.7 Change Pump This block drives two matched current sources, Iup and Idown, which are controlled respectively by UP and DOWN PFD outputs. The nominal value of the output current is controlled by an external resistor (to be connected to the REXT input pin) and a selection among 8 by a 3 bit word. The minimum value of the output current is: IMIN = 2*VBG/REXT (VBG~1.17 V) Table 8. Current Value vs Selection
CPSEL2 CPSEL1 CPSEL0 Current Value for REXT=9.1 K
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
IMIN 2*IMIN 3*IMIN 4*IMIN 5*IMIN 6*IMIN 7*IMIN 8*IMIN
0.25 mA 0.50 mA 0.75 mA 1.00 mA
1.25 mA
1.50 mA 1.75 mA 2.00 mA
Note: The current is output on pin ICP. During the VCO auto calibration, ICP and VCTRL pins are forced to VDD/2.
Figure 15. Loop Filter Connection
VDD
VCTRL
BUF
Charge Pump
ICP
C3
R3
R1 C1 BUF Cal bit
C2
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STW81100
7.8 Voltage Controlled Oscillators 7.8.1 VCO Selection Within STW81100 two low-noise VCOs are integrated to cover a wide band from 3280MHz to 4400MHz (direct output), from 1640MHz to 2200MHz (selecting divider by 2) and from 820MHz to 1100MHz (selecting divider by 4). VCO A frequency range 3280MHz-3900MHz VCO B frequency range 3800MHz-4400MHz 7.8.2 VCO Frequency Calibration Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting capacitors to the resonator. These frequency ranges are intended to cover the wide band of operation and compensate for process variation on the VCO center frequency. An automatic selection of the range is performed when the bit SERCAL rises from "0" to "1". The charge pump is inhibited and the pins ICP & VCTRL are at VDD/2 volts. Then the ranges are tested to select the one which with this VCO input voltage is the nearest to the desired output frequency (Fout = N*Fref/R). When this selection is achieved the signal ENDCALB (which means End of Calibration) falls to "0", then the charge pump is enabled again and SERCAL should be reset to "0" before the next channel step. The PLL has just to perform fine adjustment around VDD/2 on the loop filter to reach Fout, which enables a fast settle. Figure 16. VCO Sub-Bands Frequency Characteristics
The SERCAL bit should be set to "1" at each division ratio change. It should be noted that in order to reset the autocalibrator State Machine after a power-up, and anyway before the first calibration, the INITCAL bit should be set to "1" and back to "0" (this operation is automatically performed by the Power On Reset circuitry). The calibration takes approximately 7 periods of the Comparison Frequency. The maximum allowed fcomp to perform the calibration process is 1 MHz. Using an higher fcomp the following procedure should be adopted: 1. 2. Calibrate the VCO at the desired frequency with an fcomp less than 1 MHz Set the A, B and R dividers ratio for the desired fcomp
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STW81100
7.8.3 VCO Voltage Amplitude Control The bits A0 and A1 control the voltage swing of the VCO. The following table gives the voltage level expected on the resonator nodes. Table 9.
Code A[1:0] Differential output voltage (Vp)
00 01 10 11
1.1 1.3 1.9 2.1
8
I2C bus interface
Data transmission from microprocessor to the STW81100 takes place through the 2 wires (SDA and SCL) I2C-BUS interface. The STW81100 is always a slave device. The I2C-bus protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as receiver. The device that controls the data transfer is known as the Master and the others as the slave. The master will always initiate the transfer and will provide the serial clock for synchronization. 8.1 General Features 8.1.1 Power ON Reset The device at Power ON is able to configure itself to a fixed configuration, with all programmable bits set to factory default setting. 8.1.2 Data Validity Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while the clock is HIGH are used to identify START or STOP condition. Figure 17.
SDA
SCL DATA LINE STABLE DATA VALID CHANGE DATA ALLOWED
8.1.3 START condition A Start condition is identified by a HIGH to LOW transition of the data bus SDA while the clock signal SCL is stable in the HIGH state. A Start condition must precede any command for data transfer.
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STW81100
8.1.4 STOP condition A LOW to HIGH transition of the data bus SDA identifies start while the clock signal SCL is stable in the HIGH state. A STOP condition terminates communications between the STW81100 and the Bus Master. Figure 18.
SCL
SDA
START
STOP
8.1.5 Byte format and acknowledge Every byte transferred on the SDA line must contain bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA low to acknowledge the receipt of 8 bits data. Figure 19.
SCL
1
2
3 //
7
8
9
SDA START
MSB // ACKNOWLEDGMENT
FROM RECEIVER
8.1.6 Device addressing To start the communication between the Master and the STW81100, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The first 7 MSB`s are the device address identifier, corresponding to the I2C-Bus definition. For the STW81100 the address is set as "1100A2A1A0", 3bits programmable. The 8th bit (LSB) is the read or write operation bit (RW; set to 1 in read mode and to 0 in write mode). After a START condition the STW81100STW81100 identifies on the bus the device address and, if matched, it will acknowledge the identification on SDA bus during the 9th clock pulse. 8.1.7 Single-byte write mode Following a START condition the master sends a device select code with the RW bit set to 0. The STW81100 gives an acknowledge and waits for the internal sub-address (1 byte). This byte provides access to any of the internal registers. After the reception of the internal byte sub-address the STW81100 again responds with an acknowledge. A single byte write to sub-address 00H would affect DATA_OUT[119:112], so a single byte write with subaddress 07H would affect DATA_OUT[63:56] and so on.
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STW81100
Table 10.
S 1100A2A1A0 0 ack sub-address byte ack DATA IN ack P
8.1.8 Multi-byte write mode The multi-byte write mode can start from any internal address. The master sends the data bytes and each one is acknowledged. The master terminates the transfer by generating a STOP condition. The sub-address decides the starting byte. A multi byte with sub-address 07H and 5 DATA_IN byte would affect the bytes starting from DATA_OUT[63:56] to DATA_OUT[31:24] and so on. Table 11.
S 1100A2A1A0 0 ack sub-address byte ack DATA IN ack .... DATA IN ack P
8.1.9 Current Byte Address Read In the current byte address read mode, following a START condition, the master sends the device address with the rw bit set to 1 (No sub-address is needed as there is only 1 byte read register). The STW81100 acknowledges this and outputs the data byte. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition. Table 12.
S 1100A2A1A0 0 ack sub-address byte ack DATA IN ack .... DATA IN ack P
8.2 Timing Specification Figure 20. Data and clock
SDA SCL
tcwl tcs tch tcwh
Table 13.
Symbol Tcs Parameter Data to clock set up time Minimum time (ns) 2
Tch Tcwh Tcwl
Data to clock hold time Clock pulse width high Clock pulse width low
2 10 5
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STW81100
Figure 21. Start and Stop
SDA
SCL
tstart1 tstart2
tstop2 tstop1
Table 14.
Symbol Parameter Minimum time (ns)
Tstart1,2 Tstop1,2
Clock to data start time Data to clock down stop time
2 2
Figure 22. Ack
SDA
SCL
8
9
td1
td2
Table 15.
Symbol
Td1 Td2
Parameter
Maximum time (ns)
Ack begin delay Ack end delay
2 2
8.3 I2C Register STW81100 has 6 write-only registers and 1 read-only register. The following table gives a short description of the write-only registers list.
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STW81100
Table 16.
HEX CODE DEC CODE DESCRIPTION
0x00 0x01 0x02 0x03 0x04 0x05
0 1 2 3 4 5
FUNCTIONAL_MODE B_COUNTER A_COUNTER REF_DIVIDER CALIBRATION CONTROL
Table 17. Functional_Mode
MSB LSB
b7 PD7
b6 PD6
b5 PD5
b4 PD4
b3 PD3
b2 PD2
b1 PD1
b0 PD0
FUNCTIONAL_MODE register is used to select different functional mode for the STW81100 synthesizer according to the following table: Table 18.
Decimal value Description
0 1 2 3 4 5 6 7 8 9
Power down mode Enable VCO A, output frequency divided by 2 Enable VCO B, output frequency divided by 2 Enable external VCO, output frequency divided by 2 Enable VCO A, output frequency divided by 4 Enable VCO B, output frequency divided by 4 Enable external VCO, output frequency divided by 4 Enable VCO A, direct output Enable VCO B, direct output Enable external VCO, direct output
Table 19. B_COUNTER
MSB LSB
b7 B8
b6 B7
b5 B6
b4 B5
b3 B4
b2 B3
b1 B2
b0 B1
B[8:1] Counter value (bit B0 in the next register)
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STW81100
Table 20. A_COUNTER
MSB LSB
b7 B0
b6 A5
b5 A4
b4 A3
b3 A2
b2 A1
b1 A0
b0 RS
Bit B0 for B Counter, A Counter value and bit R8 for Reference divider.
Table 21. REF_DIVIDER
MSB LSB
b7 R7
b6 R6
b5 R5
b4 R4
b3 R3
b2 R2
b1 R1
b0 R0
Reference Clock divider ratio R[7:0] (bit R8 in the previous register). The LO output frequency is programmed by setting the proper value for A,B and R according to the following formula: F REF_CLK F OUT = D R ( B 64 + A ) -------------------------R
where DR equals
{
b6
1 0.5 0.25
for Direct Output for Output Divided by 2 for Output Divided by 4
Table 22. Calibration
MSB LSB
b7 INIT CAL
b5 SEL EXT CAL
b4 CAL 0
b3 CAL 1
b2 CAL 2
b1 CAL 3
b0 CAL 4
SER CAL
This register controls VCO calibrator. INITCAL: resets the auto-calibrator State Machine (writing to "1" and back to "0") SERCAL: at "1" starts the VCO auto-calibration (should be reset to "0" at the end of calibration) SELEXTCAL: at "1" selects control word EXTCAL[4:0] for the VCO EXTCAL[4:0]: control word for the VCO Table 23. CONTROL
b7 PLL_A0 b6 PLL_A1 b5 CP SEL 0 b4 CP SEL 1 b3 CP SEL 2 b2 NA b1 NA b0 NA
The CONTROL register is used to set the VCO output voltage amplitude and the Charge Pump Current. PLL_A[1:0]: VCO amplitude CPSEL[2:0]: Charge Pump output current
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STW81100
Table 24. READ-ONLY REGISTER
b7 ILLEG AL_SUBAD0 b6 END CALB b5 LOCK_DET b4 INT CAL4 b3 INT CAL3 b2 INT CAL2 b1 INT CAL1 b0 INT CAL0
This register is automatically addressed in the `current byte address read mode'. ILLEGAL_SUBADD: gives "1" if the sub-address value is not correct ENDCALB: at "0" means end of auto-calibration phase LOCK_DET: "1" when PLL is locked INTCAL[4:0]: internal value of the VCO control word Figure 23. Application Diagram
DIV2 BUF LO_OUT OUTBUFP BUF OUTBUFN DIV4 BUF EXT LO EXTVCO_INP
50
EXT VCO BUFF
EXTVCO_INN
CHARGE PUMP
VCTRL ICP REXT
REF_IN
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STW81100
9
Package Information
Figure 24. VFQFPN28 Mechanical Data & Package Dimensions
mm MIN. 0.800 TYP. 0.900 0.020 0.650 0.200 0.180 4.850 0.250 5.000 4.750 1.250 4.850 2.700 5.000 4.750 1.250 2.700 0.500 0.350 0.550 0.750 0.60 14 0.080 0.014 3.250 0.049 3.250 5.150 0.049 0.191 0.300 5.150 MAX. 1.000 0.050 1.000 MIN. 0.031 inch TYP. 0.035 MAX. 0.039
REF. A A1 A2 A3 b D D1 D2 E E1 E2 e L P K ddd
OUTLINE AND MECHANICAL DATA
0.0008 0.0019 0.025 0.0078 0.007 0.0098 0.012 0.191 0.197 0.187 0.106 0.197 0.187 0.106 0.020 0.022 0.029 0.0236 14 0.003 0.128 0.128 0.203 0.203 0.039
Notes: 1) VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Packages No lead. Very thin: A = 1.00 Max. 2) The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. Exact shape and size of this feature is optional.
VFQFPN-28 (5x5x1.0mm) Very Fine Quad Flat Package No lead
7655832 A
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STW81100
10 Revision History
Table 25. Revision History
Date Revision Description of Changes
March 2005 April 2005
1 2
First Issue Changed the maturity from Preliminary to Final datasheet. Modified sections: 1, 2, 4 (Tables 6, 7). Added new section 5 "Typical Performance Characteristics". Modified sub-section 7.8.2 "VCO Frequency Calibration". Changed "Package Informations".
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STW81100
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