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CMOS Static RAM 1 Meg (128K x 8-Bit)
Features
128K x 8 advanced high-speed CMOS static RAM Commercial (0C to +70C), Industrial (-40C to +85C) Equal access and cycle times -- Commercial and Industrial: 12/15/20ns Two Chip Selects plus one Output Enable pin Bidirectional inputs and outputs directly TTL-compatible Low power consumption via chip deselect Available in 300 and 400 mil Plastic SOJ.
IDT71024
x x x
Description
The IDT71024 is a 1,048,576-bit high-speed static RAM organized as 128K x 8. It is fabricated using IDT's high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The IDT71024 has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns available. All bidirectional inputs and outputs of the IDT71024 are TTL-compatible, and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ and 32pin 400 mil Plastic SOJ.
x x
x x
Functional Block Diagram
A0
* * *
A16
ADDRESS DECODER
* * *
1,048,576-BIT MEMORY ARRAY
I/O0-I/O7
8
I/O CONTROL
8
8
WE OE CS1 CS2
CONTROL LOGIC
2964 drw 01
FEBRUARY 2001
1
(c)2000 Integrated Device Technology, Inc. DSC-2964/14
IDT71024 CMOS Static RAM 1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Pin Configuration
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 32 2 31 3 30 4 29 28 5 6 SO32-2 27 7 SO32-3 26 25 8 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3
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Absolute Maximum Ratings(1)
Symbol VTERM TBIAS TSTG PT IOUT
(2)
Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Value -0.5 to +7.0 -55 to +125 -55 to +125 1.25 50
Unit V
o o
C C
W mA
2964 tbl 02
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V.
SOJ Top View
Capacitance Truth Table(1,2)
Inputs WE X X X X H H L CS1 H VHC(3) X X L L L CS2 X X L VLC(3) H H H OE X X X X H L X I/O High-Z High-Z High-Z High-Z High-Z DATAOUT DATAIN Function Deselected - Standby (ISB) Deselected - Standby (ISB1) Deselected - Standby (ISB) Deselected - Standby (ISB1) Outputs Disabled Read Data Write Data
2964 tbl 01
(TA = +25C, f = 1.0MHz, SOJ package)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 7 8 Unit pF pF
2964 tbl 03
NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested.
Recommended DC Operating Conditions
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0
____ ____
Max. 5.5 0 VCC+0.5 0.8
Unit V V V V
2964 tbl 04
NOTES: 1. H = VIH, L = VIL, X = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC.
Recommended Operating Temperature and Supply Voltage
Grade Commercial Industrial Temperature 0C to +70C -40C to +85C GND 0V 0V VCC 5.0V 0.5V 5.0V 0.5V
2964 tbl 05
NOTE: 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle.
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IDT71024 CMOS Static RAM 1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VCC = 5.0V 10%, Commercial and Industrial Temperature Ranges)
IDT71024 Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS1 = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min. Min.
___ ___ ___
Max. 5 5 0.4
___
Unit A A V V
2964 tbl 06
2.4
DC Electrical Characteristics(1)
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
71024S12 Symbol ICC Parameters Dynamic Operating Current, CS2 VIH and CS1 VIL, Outputs Open, VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS1 VIH or CS2 VIL, Outputs Open, VCC = Max., f=fMAX(2) Full Standby Power Supply Current (CMOS Level), CS1 VHC or CS2 VLC, Outputs Open, VCC = Max., f = 0(2), VIN VLC or VIN VHC Com'l. 160 Ind. 160 71024S15 Com'l. 155 Ind. 155 71024S20 Com'l. 140 Ind. 140 Unit mA
ISB
40
40
40
40
40
40
mA
ISB1
10
10
10
10
10
10
mA
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
2964 tbl 07
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
2964 tbl 08
5V 480
5V 480 DATA OUT 30pF 255
DATA OUT 5pF* 255
2964 drw 04
*Including jig and scope capacitance.
2964 drw 03
Figure 2. AC Test Load Figure 1. AC Test Load 6.42 3
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
IDT71024 CMOS Static RAM 1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 5.0V 10%, Commercial and Industrial Temperature Ranges)
71024S12 Symbol Read Cycle tRC tAA tACS tCLZ(1) tCHZ tOE tOLZ(1) tOHZ(1) tOH tPU
(1) (1)
71024S15 Min. Max.
71024S20 Min. Max. Unit
Parameter
Min.
Max.
Read Cycle Time Address Access Time Chip Select Access Time Chip Sele ct to Output in Low-Z Chip Desele ct to Output in High-Z Output Enable to Output Valid Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power-Down Time
12 -- -- 3 0 -- 0 0 4 0 --
-- 12 12 -- 6 6 -- 5 -- -- 12
15 -- -- 3 0 -- 0 0 4 0 --
-- 15 15 -- 7 7 -- 5 -- -- 15
20 -- -- 3 0 -- 0 0 4 0 --
-- 20 20 -- 8 8 -- 7 -- -- 20
ns ns ns ns ns ns ns ns ns ns ns
tPD(1) Write Cycle tWC tAW tCW tAS tWP tWR tDW tDH tOW(1) tWHZ
(1)
Write Cycle Time Address Valid to End-of-Write Chip Select to End-of-Write Address Set-Up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Output Active from End-of-Write Write Enable to Output in High-Z
12 10 10 0 8 0 7 0 3 0
-- -- -- -- -- -- -- -- -- 5
15 12 12 0 12 0 8 0 3 0
-- -- -- -- -- -- -- -- -- 5
20 15 15 0 15 0 9 0 4 0
-- -- -- -- -- -- -- -- -- 8
ns ns ns ns ns ns ns ns ns ns
2964 tbl 09
NOTE: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
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IDT71024 CMOS Static RAM 1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC ADDRESS tAA OE tOE CS1 tOLZ(5)
CS2 tCLZ (5) DATAOUT Vcc SUPPLY CURRENT Icc ISB HIGH IMPEDANCE tPU
tACS (3) tOHZ (5) tCHZ(5) DATAOUT VALID tPD
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Timing Waveform of Read Cycle No. 2(1,2,4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
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NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is HIGH. 3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
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IDT71024 CMOS Static RAM 1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,4,6)
tWC ADDRESS tAW CS1 tCW
CS2 tAS WE tWHZ DATAOUT
(3) (5)
tWR(2) tWP
(6)
tOW HIGH IMPEDANCE tDH tDW DATAIN VALID
(5)
tCHZ
(3)
(5)
DATAIN
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Timing Waveform of Write Cycle No. 2 (CS1 AND CS2 Controlled Timing)(1,4)
tWC ADDRESS tAW CS1
CS2 tAS WE tDW DATAIN DATAIN VALID
2964 drw 08
tCW
tWR
(2)
tDH
NOTES: 1. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE. 2. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS1 LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS1 and CS2 must both be active during the tCW write period. 5. Transition is measured 200mV from steady state. 6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.
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IDT71024 CMOS Static RAM 1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information
IDT 71024 Device Type S Power XX Speed X Package X Process/ Temperature Range Blank I TY Y 12 15 20 Commercial (0C to +70C) Industrial (-40C to +85C) 300-mil SOJ (SO32-2) 400-mil SOJ (SO32-3)
Speed in nanoseconds
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IDT71024 CMOS Static RAM 1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
9/30/99 Pg. 1, 3, 4, 7 Pg. 1-4, 7 Pg. 3 Pg. 6 Pg. 8 Pg. 4 Pg. 3 Pg. 3 Updated to new format Added 12ns industrial speed grade offering Removed military temperature offerings Removed 17ns and 25ns speed grades Revised ICC and ISB1 for 15ns and 20ns industrial speed grades Removed Note 1, reordered notes and footnotes Added Datasheet Document History Changed tWP(min) for 12ns speed grade from 10ns to 8ns. Revised Icc and ISB for Industrial Temperature offerings to meet commercial specifications Revised ISB to accomidate speed functionaility Not recommended for new designs Removed "Not recommended for new designs"
1/6/2000 2/18/00 3/14/00 08/09/00 02/01/01
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: sramhelp@idt.com 800-544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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