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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14517B Dual 64-Bit Static Shift Register
The MC14517B dual 64-bit static shift register consists of two identical, independent, 64-bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data input is entered by clocking, regardless of the state of the write enable input. An output is disabled (open circuited) when the write enable input is high. During this time, data appearing at the data input as well as the 16-bit, 32-bit, and 48-bit taps may be entered into the device by application of a clock pulse. This feature permits the register to be loaded with 64 bits in 16 clock periods, and also permits bus logic to be used. This device is useful in time delay circuits, temporary memory storage circuits, and other serial shift register applications. * * * * * * * * Diode Protection on All Inputs Fully Static Operation Output Transitions Occur on the Rising Edge of the Clock Pulse Exceedingly Slow Input Transition Rates May Be Applied to the Clock Input 3-State Output at 64th-Bit Allows Use in Bus Logic Applications Shift Registers of any Length may be Fully Loaded with 16 Clock Pulses Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
Parameter Value Unit V V L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
DW SUFFIX SOIC CASE 751G
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III IIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS (Voltages referenced to VSS)
Symbol VDD DC Supply Voltage - 0.5 to + 18.0 10 500 Vin, Vout Iin, Iout PD TL Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW Tstg - 65 to + 150 260
PIN ASSIGNMENT
Q16A Q48A WEA CA Q64A Q32A DA VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q16B Q48B WEB CB Q64B Q32B DB
_C _C
Lead Temperature (8-Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C Write Enable 0 1 0 1 0 1 0 1
FUNCTIONAL TRUTH TABLE (X = Don't Care)
Clock 0 0 1 1 Data X X X X Data entered into 1st Bit Data entered into 1st Bit X X 16-Bit Tap Content of 16-Bit Displayed High Impedance Content of 16-Bit Displayed High Impedance Content of 16-Bit Displayed Data at tap entered into 17-Bit Content of 16-Bit Displayed High Impedance 32-Bit Tap Content of 32-Bit Displayed High Impedance Content of 32-Bit Displayed High Impedance Content of 32-Bit Displayed Data at tap entered into 33-Bit Content of 32-Bit Displayed High Impedance 48-Bit Tap Content of 48-Bit Displayed High Impedance Content of 48-Bit Displayed High Impedance Content of 48-Bit Displayed Data at tap entered into 49-Bit Content of 48-Bit Displayed High Impedance 64-Bit Tap Content of 64-Bit Displayed High Impedance Content of 64-Bit Displayed High Impedance Content of 64-Bit Displayed High Impedance Content of 64-Bit Displayed High Impedance
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14517B 403
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Three-State Leakage Current VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD Adc pF Adc IT IT = (4.2 A/kHz) f + IDD IT = (8.8 A/kHz) f + IDD IT = (13.7 A/kHz) f + IDD Adc ITL 15 -- 0.1 -- 0.0001 0.1 -- 3.0 Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.004. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14517B 404
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.65 ns/pF) CL + 9.5 ns Propagation Delay Time tPLH, tPHL = (1.7 ns/pF) CL + 390 ns tPLH, tPHL = (0.66 ns/pF) CL + 177 ns tPLH, tPHL = (0.5 ns/pF) CL + 115 ns Clock Pulse Width Symbol VDD 5.0 10 15 5.0 10 15 tWH 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 0 10 15 150 75 35 400 200 110 380 180 100 Min -- -- -- -- -- -- 330 125 100 -- -- -- Typ # 100 50 40 475 210 140 170 75 60 3.0 6.7 8.3 **See Note - 40 - 15 0 75 25 10 170 65 50 160 55 40 -- -- -- -- -- -- -- -- -- -- -- -- ns Max 200 100 80 770 300 215 -- -- -- 1.5 4.0 5.3 ns Unit ns tTLH, tTHL tPLH, tPHL ns Clock Pulse Frequency fcl MHz Clock Pulse Rise and Fall Time tTLH, tTHL -- Data to Clock Setup Time tsu Data to Clock Hold Time th ns Write Enable to Clock Setup Time tsu ns Write Enable to Clock Release Time trel ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage. VDD CL CL CL CL D C WE Q16 Q32 Q48 Q64 VSS 50 F ID CL CL CL CL D
REPETITIVE WAVEFORM
fo C VDD VSS VDD D (f = 1/2 fo) VSS
C
D C WE
Q16 Q32 Q48 Q64
Figure 1. Power Dissipation Test Circuit and Waveform
MOTOROLA CMOS LOGIC DATA
MC14517B 405
Vout = VOH VDD = VGS VDD = VGS
Vout = VOL
D C WE
Q16 Q32 Q48 Q64
D C WE
Q16 Q32 Q48 Q64
D C WE Q16 Q32 Q48 Q64
IOH
D C WE Q16 Q32 Q48 Q64
IOL
VSS (Output being tested should be in the high-logic state)
EXTERNAL POWER SUPPLY
VSS
EXTERNAL POWER SUPPLY
(Output being tested should be in the low-logic state)
Figure 2. Typical Output Source Current Characteristics Test Circuit
tWH PIN NO'S CLOCK 4 (12) WRITE 3 (13) th1 tsu1 DATA IN 7 (9) tsu1 16-BIT OUTPUT 1 (15) 17-BIT INPUT tsu1 32-BIT OUTPUT 6 (10) 33-BIT INPUT tsu1 48-BIT OUTPUT 2 (14) 49-BIT INPUT th1 th0 tsu0 th1 50% tsu0 th0 tsu0 th0 tsu0 th0 tPHL VDD 20 ns VDD 20 ns VDD 20 ns 64-BIT OUTPUT 5 (11) tPHL tPHL tPHL tPLH 20 ns trel 1 tWL 2 16 17
Figure 3. Typical Output Sink Current Characteristics Test Circuit
18
19 tsu
90% 10%
33
VDD 50% VSS VDD VSS
90% 10% tPLH 90% tTLH 90% tTLH VOH
VDD 50% VSS VDD VSS VDD VSS VDD VSS VDD VSS
th1
tPLH
10% V tTHL OL VOH 50% 10% VOL tTHL VOH V tTHL OL
tTLH tPLH tTLH
tTHL
Figure 4. AC Test Waveforms EXPANDED BLOCK DIAGRAM (1/2 OF DEVICE SHOWN)
CLOCK DATA D C Q D C Q D Q C 16 3-STATE D Q C 17 WE D Q C 32 3-STATE D Q C 33 WE D Q C 48 3-STATE D Q C 49 WE D C 64 Q 3-STATE
1
2
WRITE ENABLE
WRITE ENABLE = 0, 16-BIT OUTPUT WRITE ENABLE = 1, 17-BIT INPUT
32-BIT OUTPUT 33-BIT INPUT
48-BIT OUTPUT 49-BIT INPUT
64-BIT OUTPUT HIGH IMPEDANCE
MC14517B 406
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MOTOROLA CMOS LOGIC DATA
MC14517B 407
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-02 ISSUE A
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
-B-
1 8
8X
P 0.010 (0.25)
M
B
M
16X
D
M
J TA
S
0.010 (0.25)
B
S
F R X 45 _ C -T-
14X DIM A B C D F G J K M P R
G
K
SEATING PLANE
M
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MC14517B 408
*MC14517B/D*
MOTOROLA CMOS LOGIC DATA MC14517B/D

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