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LDRxxyy VERY LOW DROP DUAL VOLTAGE REGULATOR s s s s s s s s s s s OUTPUT CURRENT 1 UP TO 500mA OUTPUT CURRENT 2 UP TO 1.0A LOW DROPOUT VOLTAGE 1 (0.3V @ IO =500mA) LOW DROPOUT VOLTAGE 2 (0.4V @ IO =1A) VERY LOW SUPPLY CURRENT (TYP.50A IN OFF MODE, 1.6mA MAX IN ON MODE) LOGIC-CONTROLLED ELECTRONIC SHUTDOWN OUTPUT VOLTAGE AVAILABILITY FOR EACH REGULATOR: 1.8V, 2.5V, 3.3V INTERNAL CURRENT AND THERMAL LIMIT STABLE WITH LOW VALUE (MIN 4.7F) AND LOW E.S.R. OUTPUT CAPACITORS SUPPLY VOLTAGE REJECTION: 70dB (TYP.) TEMPERATURE RANGE (-40C TO 125C) SPAK-7L PPAK DESCRIPTION The LDRxxyy is a Very Low Drop Dual Voltage Regulator available in PPAK for the version without inhibit and in SPAK-7L for the version with the shutdown feature. The very low drop-voltage Figure 1: Block Diagram VI1 POWER 1 (0.5V) and the very low supply current make it particularly suitable for low noise and low power applications such as PDA, MICRODRIVE and other data storage applications while the used high voltage technology makes this device suitable for consumer applications such as MONITORS AND SET-TOP-BOX. For each VO a Shutdown Logic Control function is available (TTL compatible) to decrease the total power consumption. VO1 INH1 START UP 1 BAND GAP 1 DRIVER 1 + ERROR AMPLIFIER 1 THERMAL 1 THERMAL 2 + ERROR AMPLIFIER 2 INH2 START UP 2 BAND GAP 2 DRIVER 2 VI2 POWER 2 VO2 August 2004 Rev. 2 1/13 LDRxxyy Table 1: Absolute Maximum Ratings Symbol VI1 & VI2 INH IO PTOT TSTG TA DC Input Voltage Shutdown Voltage Output Current Power Dissipation Storage Temperature Range Operating Ambient Temperature Range Parameter Value -0.3 to 15 -0.3 to 15 Internally Limited Internally Limited -50 to +150 -40 to +125 C C Unit V V Absolute Maximum Rating are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 2: Thermal Data Symbol RTHJ-C Parameter Junction to case thermal resistance PPAK 8 SPAK-7L 2 Unit C/W Figure 2: Connection Diagram (top view) PPAK SPAK-7L Table 3: Pin Description Symbol GND VI1 VI2 VINH1 VINH2 VO1 VO2 N.C. 4 5 Pin N for PPAK 3 2 1 Pin N for SPAK-7L 4 2 1 3 5 6 7 Name and Function Ground pin Input 1 Supply Pin. Bypass with a 2.2F capacitor to GND Input 2 Supply Pin. Bypass with a 2.2F capacitor to GND Enable 1 Pin. Internally connected to VI1 in the PPAK version Enable 2 Pin. Internally connected to VI2 in the PPAK version Output 1 Pin. Bypass with a 4.7F capacitor to GND Port Output 2 Pin. Bypass with a 4.7F capacitor to GND Port Not Internally Connected Table 4: Order Codes VO1 1.8 V 1.8 V 2.5 V 2.5 V 3.3 V 3.3 V 2/13 VO2 2.5 V 3.3 V 1.8 V 3.3 V 1.8 V 2.5 V PART NUMBERS TYPE SPAK-7L LDR1825 LDR1833 LDR2518 LDR2533 LDR3318 LDR3325 LDR1825K7-R LDR1833K7-R LDR2518K7-R LDR2533K7-R LDR3318K7-R LDR3325K7-R PPAK LDR1825PT-R LDR1833PT-R LDR2518PT-R LDR2533PT-R LDR3318PT-R LDR3325PT-R LDRxxyy Table 5: Electrical Characteristics (VI1 = VO1+2V, VI2 = VO2+2V, VINH1 = VINH2 = 2.5V, CI1,2 = 2.2F, CO1,2 = 4.7F, IO1 = IO2 = 10mA, TA = -40C to 125C, unless otherwise specified. Typical values are referred at TA = 25C) Symbol VO1 VO2 Parameter Output Voltage 1 Output Voltage 2 IO1 = 500mA IO2 = 1A VI1 = VO1+2V to VO1+7V, IO = 250mA VI2 = VO2+2V to VO2+7V, IO = 500mA VI1 = VO1+2V, IO1 = 10 to 500mA VI2 = VO2+2V, IO2 = 10mA to 1A IO1 = IO2 = NO LOAD NO LOAD IO1 = 500mA, IO2 = 1A TA = 25 TA = 25 500 1 2.4 0.8 VINH = 5V (2) Test Conditions Min. -5 -5 Typ. VNOM1 VNOM2 0.3 0.4 15 15 10 60 2 1 30 800 1.6 Max. +5 +5 0.7 0.8 30 40 Unit %V %V V V mV mV mV mV mA mA mA mA A V V A dB %VO VDROP1 Dropout Voltage 1 (1) VDROP2 Dropout Voltage 2 (1) VO1 Line Regulation 1 VO2 VO1 VO2 ISTOT IS IQMAX ISC1 ISC2 VINH-H VINH-L IINH SVR eN Line Regulation 2 Load Regulation 1 Load Regulation 2 Total Supply Current 1 Channel Supply Current Quiescent Current Short Circuit Current 1 Short Circuit Current 2 Enable Voltage HIGH Enable Voltage LOW Enable Pin Current Supply Voltage Rejection RMS Output Noise (2) 6 70 0.003 VI1,2 = VO1,2 +3V 1V, IO1,2 = 10 mA, f = 120Hz Bandwidth of 10Hz to 100KHz (1): This test is not performed for VO<2.5V. (2): Guaranteed by design, but not tested in production. Figure 3: Typical Application Circuit 3/13 LDRxxyy TYPICAL CHARACTERISTICS (unless otherwise specified Tj = 25C) Figure 4: Dropout Voltage (VO1) vs Temperature Figure 7: Output Voltage (VO2) vs Temperature Figure 5: Dropout Voltage (VO2) vs Temperature Figure 8: Line Regulation (VO1) vs Temperature Figure 6: Output Voltage (VO1) vs Temperature Figure 9: Load Regulation (VO1) vs Temperature 4/13 LDRxxyy Figure 10: Line Regulation (VO2) vs Temperature Figure 13: Short Circuit Current (VO2) vs Drop Voltage Figure 11: Load Regulation (VO2) vs Temperature Figure 14: Inhibit Voltage vs Temperature Figure 12: Short Circuit Current (VO1) vs Drop Voltage Figure 15: One Channel Inhibit Current vs Temperature 5/13 LDRxxyy Figure 16: Supply Voltage Rejection vs (VO1) Temperature Figure 19: Supply Voltage Rejection (VO2) vs Frequency Figure 17: Supply Voltage Rejection vs (VO2) Temperature Figure 20: Maximum Total Quiescent Current vs Temperature Figure 18: Supply Voltage Rejection (VO1) vs Frequency Figure 21: Total Supply Current vs Temperature 6/13 LDRxxyy Figure 22: Quiescent Current (VO1) vs Output Current Figure 25: Load Transient CI1,2=1F, CO1,2=2.2F, VINH1,2 =2.5V, VI1=4.5V, VI2=5.3V, IO1=5mA to 0.5A, IO2=5mA to 1A, tRISE=tFALL=4.2s Figure 23: Quiescent Current (VO2) vs Output Current Figure 26: Line Transient VO1,2 CI1,2=0, CO1,2=2.2F, VI1=4.4 to 10.4V, VI2=5.3 to 11.3V, IO1=0.25A, IO2 =0.5A, tRISE=tFALL =4.4s Figure 24: Thermal Protection vs VO1 Figure 27: Start up Transient VO1 VI1=1.1 to 8.5V, VI2=1.2 to 9.8V, IO1=0.25A, IO2=0.5A, t RISE=5s 7/13 LDRxxyy PPAK MECHANICAL DATA mm. DIM. MIN. A A1 A2 B B2 C C2 D D1 E E1 e G G1 H L2 L4 L5 L6 0.6 1 2.8 4.9 2.38 9.35 0.8 6.4 4.7 1.27 5.25 2.7 10.1 1 1 0.023 0.039 0.110 0.193 0.093 0.368 0.031 2.2 0.9 0.03 0.4 5.2 0.45 0.48 6 5.1 6.6 0.252 0.185 0.050 0.206 0.106 0.397 0.039 0.039 TYP MAX. 2.4 1.1 0.23 0.6 5.4 0.6 0.6 6.2 MIN. 0.086 0.035 0.001 0.015 0.204 0.017 0.019 0.236 0.201 0.260 TYP. MAX. 0.094 0.043 0.009 0.023 0.212 0.023 0.023 0.244 inch 0078180-E 8/13 LDRxxyy SPAK-7L MECHANICAL DATA DIM. A A2 C C1 D D1 F G G1 H1 H2 H3 L L1 L2 M N V 3 8.89 0.79 0.25 6 3 9.27 8.89 10.41 7.49 9.14 1.04 0.350 0.031 0.010 6 1.02 7.87 0.63 1.27 7.62 5.59 9.52 9.14 10.67 0.365 0.350 0.410 0.295 0.360 0.041 mm. MIN. 1.78 0.03 0.25 0.25 1.27 8.13 0.79 0.040 0.310 0.025 0.050 0.3 0.220 0.375 0.360 0.420 TYP MAX. 2.03 0.13 MIN. 0.070 0.001 0.010 0.010 0.050 0.320 0.031 inch TYP. MAX. 0.080 0.005 PO13F2/A 9/13 LDRxxyy Tape & Reel SPAK-xL MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 9.70 10.85 2.30 3.9 11.9 9.80 10.95 2.40 4.0 12.0 12.8 20.2 60 14.4 9.90 11.05 2.50 4.1 12.1 0.382 0.423 0.090 0.153 0.468 0.386 0.427 0.094 0.157 0.472 13.0 TYP MAX. 180 13.2 0.504 0.795 2.362 0.567 0.390 0.431 0.098 0.161 0.476 0.512 MIN. TYP. MAX. 7.086 0.519 inch 10/13 LDRxxyy Tape & Reel DPAK-PPAK MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.80 10.40 2.55 3.9 7.9 6.90 10.50 2.65 4.0 8.0 12.8 20.2 60 22.4 7.00 10.60 2.75 4.1 8.1 0.268 0.409 0.100 0.153 0.311 0.272 0.413 0.104 0.157 0.315 13.0 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.2.76 0.417 0.105 0.161 0.319 0.512 MIN. TYP. MAX. 12.992 0.519 inch 11/13 LDRxxyy Table 6: Revision History Date 03-Aug-2004 Revision 2 Description of Changes Typing correction on tables 1, 3, 5 and figures 3, 6, 10, 11, 14, 17, 22, 23. 12/13 LDRxxyy Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 13/13 |
Price & Availability of LDR2533
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