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INTEGRATED CIRCUITS
DATA SHEET
SAA2521 Masking threshold processor for MPEG layer 1 audio compression applications
Preliminary specification File under Integrated Circuits, IC01 August 1993
Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
FEATURES * Stereo or 2-channel mono encoding * Status may be read continuously * Microcontroller interface * I2S-interfaces * Allocation algorithm including optional emphasis correction (for 44.1 kHz) * Reduced power consumption * 4 V nominal operating voltage capability. ORDERING INFORMATION EXTENDED TYPE NUMBER SAA2521GP Note 1. SOT205-1; 1996 August 23. PACKAGE PINS 44 PIN POSITION QFP MATERIAL plastic GENERAL DESCRIPTION
SAA2521
The SAA2521 performs the adaptive allocation and scaling function for calculating the masking thresholds and sub-band sample accuracy in MPEG layer 1 applications. The SAA2521 is intended for use in conjunction with the stereo filter codec SAA2520.
CODE SOT205AG(1)
August 1993
2
Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SAA2521
VDD
handbook, full pagewidth
SWS FS256
31 39
14,24,40
33 FDAF 34 INTERFACE COMPENSATION DELAY INTERFACE 32
FDAC SCL
NODONE RESOL0 RESOL1 FDIR FRESET FSYNC SCALE TEST3 TEST4
20 21 22 37 36 35 38 15 16 CONTROL
SAA2521
ALLOCATION AND SCALING CALCULATION
LTDATA LTCNT1 LTCNT0 LTENA LTCLK CLK24 RESET PWRDWN
5 1 2 3 4 26 23 30
LT INTERFACE
11 7 8 9 10
LTDATAC LTCNT1C LTCNT0C LTENC LTCLKC
6,25,44 VSS
MLB137
Fig.1 Block diagram.
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SAA2521
FRESET
35 FSYNC
38 SCALE
39 FS256
n.c.
n.c.
handbook, full pagewidth
44
43
42
41
n.c.
40
V DD
VSS
37
36
LTCNT1 LTCNT0 LTENA LTCLK LTDATA V SS LTCNT1C LTCNT0C LTENC
1 2 3 4 5 6 7 8 9
34
FDAF
FDIR
33 FDAC 32 SCL 31 SWS 30 PWRDWN 29 TEST10
SAA2521
28 TEST9 27 TEST8 26 CLK24 25 V SS 24 V DD 23 RESET
LTCLKC 10 LTDATAC 11
12
13
14
15
16
17
18
19
20
21
22
MLB136
RESOL0
Fig.2 Pin configuration.
handbook, full pagewidth
AUDIO SOURCE
AUDIO AMPLIFIER
digital audio interface ADC/DAC control SAA2520 and SAA2521 MPEG interface MPEG source/ receiver
system micro interface MICROCONTROLLER power down reset
NODONE
RESOL1
TEST1
TEST2
V DD
TEST3
TEST4
TEST5
TEST6
TEST7
MLB138
Fig.3 MPEG codec system data flow diagram.
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
PINNING SYMBOL LTCNT1 LTCNT0 LTENA LTCLK LTDATA VSS LTCNT1C LTCNT0C LTENC LTCLKC LTDATAC TEST1 TEST2 VDD TEST3 TEST4 TEST5 TEST6 TEST7 NODONE RESOL0 RESOL1 RESET VDD VSS CLK24 TEST8 TEST9 TEST10 PWRDWN SWS SCL FDAC FDAF FSYNC FRESET FDIR SCALE FS256 VDD August 1993 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DESCRIPTION mode control 1, microcontroller interface input mode control 0, microcontroller interface input enable microcontroller interface input bit clock microcontroller interface input data, microcontroller interface (3-state inputs/outputs) supply ground (0 V) control 1; microcomputer interface control 0; microcomputer interface enable microcontroller interface bit clock; microcontroller interface data; microcontroller interface, (3-state inputs/outputs) test output; do not connect test output; do not connect positive supply voltage (+ 5 V) test mode input; to be connected to VDD test mode input; to be connected to VDD test input; to be connected to VSS test input; to be connected to VSS test input; to be connected to VSS no done state selection input resolution selection 0 input resolution selection 1 input active HIGH reset input positive supply voltage (+ 5 V) supply ground (0 V) 24.576 MHz processing clock input test input; to be connected to VSS test input; to be connected to VSS test input; to be connected to VSS power-down input word selection input; (Filtered) - I2S-interface bit clock input; (Filtered) filtered data (Filtered) I2S-interface (3-state inputs/outputs) I2S-interface, input I2S-interface
SAA2521
TYPE I I I I I/O O O O O I/O
I I I I
I
I I I I/O I/O I I I I I
filtered data (Filtered) - I2S-interface (3-state inputs/outputs) sub-band synchronization on (Filtered) reset signal input from SAA2520 direction of the I2S-interface; input scale factor index select (note 1) system clock input; sample frequency x 256 positive supply voltage (+ 5 V) 5
Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SYMBOL n.c. n.c. n.c. VSS PIN 41 42 43 44 not connected not connected not connected supply ground (0 V) DESCRIPTION
SAA2521
TYPE
Note to the Pinning Description 1. The scale input must be set LOW for use with the SAA2521. FUNCTIONAL DESCRIPTION Coding System This efficient MPEG audio encoder is used in conjunction with the SAA2520 filter codec (bit rates of 384, 256, 192 and 128 k bits/s). The encoder utilizes a system producing sub-band samples from an incoming digital audio signal. This relies upon the audibility of signals above a given level and upon high amplitude signals masking those of lower amplitude. Although each sub-band signal is of approximately 750 Hz bandwidth, it possesses considerable overlap with those adjacent to it. During the process of encoding, the masking threshold processor analyses the broadband audio signal at sampling frequency fs by splitting it into 32 sub-band signals at a sampling frequency (fs/32). The coded signal consists of frames conveying the information corresponding to the sub-band samples. These also include a synchronization pattern identifying the start of each new frame. The allocation information for the 32 sub-bands is transferred as 4-bit values. If the amplitude of a sub-band signal is below the masking threshold it will be omitted from the coded signal. The duration of a MPEG frame depends upon sampling frequency and is adjusted to 384 divided by fs. Adaptive Allocation and Scaling The coding system calculates the masking power of the sub-band signals and adds the masking threshold. Sub-band signals with power below this threshold denote information to be discarded. Non-masked signals are coded using floating point notation in which a mantissa corresponds in length to the difference between peak power and masking threshold. The process is repeated for every MPEG frame and is known as the Adaptive Allocation of the available capacity. Encoding Mode Signal FDIR sets the data flow direction on the Filtered-I2S-interface. In the encoding mode (FDIR LOW) the device will accept samples from FDAF. These will be delayed by a number of sample periods depending upon the setting of the SCALE input. In the instance of operation with the SAA2520 (SCALE = logic 0) this delay will be 480 SWS periods. This will ensure alignment of the data with the computed allocations. After the delay the samples will be presented on FDAC (pin 33). The circuit also performs all the calculations required to build the allocation table which is used in the codec (SAA2520). When used with the SAA2520 the calculated scale factor indices are sent via the LT interface. These operations are performed for every frame of the sub-band codec. In order to synchronize with the codec and utilize the correct tables for the calculations the SAA2521 frequently requests the status of the codec. It monitors the bit-rate, sample frequency, operation mode and the emphasis information and uses the 'ready to receive' bit of the codec to determine the moment of the transfer of allocation information. Decoding Mode In the decoding mode (FDIR HIGH) the SAA2521 will take samples from FDAC which will be presented on the FDAF after a delay of 160 SWS periods. The LT interface between microcontroller and codec (SAA2520) will only be affected by the 'ready to receive' bit from the codec (SAA2520).
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
Microcontroller Interface Operation Information on the interface between microcontroller and codec (SAA2520) will flow in a regular sequence synchronized with the codec (SAA2520): - with every FSYNC the SAA2521 will read the status of the codec (SAA2520) - Following the calculation of the allocation and scale factors the SAA2521 will send the first allocation information unit (16-bits). It will then continuously read the codec (SAA2520) status to ascertain when it is able to receive further allocation information units. When the transfer of these units is complete the SAA2521 will send settings and (for SCALE = logic 0) scale factor indices. - The extended settings will be sent to the codec as soon as possible after reception from the microcontroller. The microcontroller communicates with the SAA2521 in a similar fashion: - status can be read continuously. The SAA2521 will output a copy of the codec (SAA2520) status on the LTDATA line except for the 'ready to receive' bits which are generated by the SAA2521. These indicate whether the SAA2521 is ready to receive the next settings or extended settings. - settings can be sent following every occasion that the 'ready to receive' bit 'S' changes to logic 1. - extended settings can be sent following each occasion that the 'ready to receive' bit 'E' changes to logic 1.
SAA2521
Mode Control Operation is controlled by the FRESET and FDIR signals. FRESET causes a general reset. The FDIR signal is sampled at the falling edge of the FRESET signal to determine the operation mode: FDIR = logic 1 FDIR = 0 decoding mode, SAA2521 in feed-through mode encoding mode, SAA2521 in calculation mode
Fig.4 shows the timing diagram for FRESET and FDIR. Resolution Selection The (SAA2521) is designed for operation with input devices (ADCs) which may possess a different sample resolution capability, i.e. audio sample inputs into the sub-band filters. Pins RESOL0 and RESOL1 (respectively pins 21 and 22) may be utilized to adjust the allocation information calculation to the resolution of the samples. With the instance of pin 20 (NODONE) being HIGH, all available bits in the bit-pool will be allocated. If NODONE is LOW, no bits will be allocated to the sub-bands with energy levels below the theoretical threshold for the selected resolution.
t rH FRESET t suD FDIR
MBC123 - 1
TrH > 5TCLK24 = 210 ns (for CLK24 = 24.576 MHz) min. time FRESET HIGH TsD < 0 ns min. set-up time FDIR to FRESET = LOW
Fig.4 Timing: FRESET and FDIR.
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
Power-down Mode Switching When the potential on the RESET pin (pin 23) is held HIGH for at least 5TCLK24 clock periods, the device will be reset after which it will operate in its decoding mode. The power-down mode is activated when the PWRDWN pin (pin 30) is held HIGH. The 3-state buffers will be set to a high impedance while the normal outputs will retain the state attained prior to this mode being entered. This mode can only be used if other associated circuits react accordingly. The power-down mode is de-activated by a reset action. Fig.5 shows the operation for the power-down mode switching. Table 1 Resolution selection. RESOL0 0 1 0 1
SAA2521
RESOL1 0 0 1 1
RESOLUTION 16-bits 18-bits 14-bits 15-bits
PWRDWN
sleep mode active
RESET t rH
MEA659 - 1
TrH > 5TCLK24 = 210 ns (for CLK24 = 24.576 MHz) minimum time RESET HIGH
Fig.5 Power-down mode switching.
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SAA2521
channel SWS
left 32 bits
right
SCL 1 FDA bit : 2 3 msb 2 2 2 1 2 0 2 1 0 lsb 2 3 msb 2 2 2 1 2 0
MBC149 - 1
7 bits
Fig.6 Format for transferring filtered data.
channel SWS
L
R
L
R
L
R
L
R
L
R
L
R
L
R
FSYNC sub-band 31 0 1 31 0 1
MBC126 - 2
Fig.7 FSYNC related to SWS 0 data transfer period.
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
Table 2 SWS SCL FDAF FDAC FSYNC Table 3 FRESET FDIR (Filtered) - I2S-interfaces Interfaces with the sub-band filter and codec (SAA2520) consist of the following signals. Fig.6 shows the format for transferring filtered data. Fs 256 must be provided as system clock. This frequency is used by the interfaces with the SAA2520. The frequency of the SWS signal (pin 31) is equal to the sample frequency Fs. Bit clock SCL (pin 32) is 64 times the sample frequency; thus each SWS period contains 64 data bits, 48 of which are actually used in data transfer. The half period during which SWS is logic 0 is used to transfer Left-channel information while that during which it is 1 permits transfer of Right-channel data. The 24-bit samples are transferred with the most significant bit first. This bit is transferred during the bit clock period, one bit time after the change in SWS. FSYNC signal is provided for the purposes of synchronization and indicates the portion of the SWS period during which the samples of sub-band 0 are transferred. Fig.7 shows the relationship between FSYNC and the SWS 0 data transfer period. The (Filtered) - I2S-interface. input input bi-directional bi-directional input The (Filtered) - I2S-interface. input input reset Filtered - I2S-interface direction of data flow word selection bit clock filtered data to/from the filter section of SAA2520 filtered data to/from the codec section of SAA2520 filter synchronization Fs
SAA2521
64 Fs
Fs/32
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SAA2521
4T t cH SCL t d4 t d3 output t su1 input
MBC127 - 2
t cL
t h1
OUTPUT applies to FDAF and FDAC in the output mode. INPUT applies to FDAF and FDAC in the input mode, SWS and FSYNC. T = one Fs256 cycle time minimum HIGH time SCL tcH T + 35 ns TcL T + 35 ns minimum LOW time SCL td3 2T - 10 ns hold time output after SCL HIGH td4 3T + 60 ns delay time output after SCL HIGH set-up time input before SCL HIGH ts1 20 ns th1 T + 35 ns hold time input after SCL HIGH
FDIR t W1 FDA HIGH Z t W2 HIGH Z
MEA692 - 1
tw1 3T minimum time high impedance to FDA enabled tw2 2T + 35 ns maximum time FDA enabled to high impedance
Fig.8 (Filtered) - I2S-interface timing.
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
Table 4 LTCLK LTDATA LTCNT0 LTCNT1 LTENA Table 6 SAA2521 interface with microcontroller. input bi-directional input input input bitclock data control line 0 control line 1 enable Table 5 LTCLKC LTDATAC LTCNT0C LTCNT1C LTENC
SAA2521
SAA2521 interface with SAA2520. output bi-directional output output output bit clock data control line 0 control line 1 enable
SAA2521 interface control lines functions. LTCNT0(C) 0 1 0 1 MODE extended settings allocation (see note) settings status FROM microcontroller SAA2521 microcontroller codec TO SAA2520 SAA2520 SAA2520 microcontroller TRANSFER OF 8-bits 16/48 x 16-bits 16-bits 8 or 16-bits
LTCNT1(C) 0 0 1 1
Microcontroller Interface Two microcontroller interfaces are provided; one for connection to the microcontroller interface of the SAA2520, the other to connect to the system controller. Information is conveyed via the SAA2521 which executes monitoring and extracts signals (e.g. settings and synchronization) essential to its operation. Additionally it also sends allocation information to the SAA2520. However, the SAA2521 does not monitor the external settings bits from the microcontroller (see Extended Settings). The SAA2521 is a slave on the interface with the microcontroller which is active only when the enable signal LTENA (pin 3) is logic 1. This permits connection of this interface to other devices. Only the enable signal is not common to all devices. SAA2521 is master on the interface with the SAA2520 and provides all signals with the exception of the data in the instance of status transfer from SAA2520 to SAA2521. Information conveyed via these interfaces is transferred in 8 or 16-bit serial units with the type of information designated by the control lines (LTCNT1(C) and LTCNT0(C)).
A transfer of information begins when the master sets the control lines for the required action. It then sets the LTENA/C line to logic 1. Once this signal is established the slave determines the kind of action required and prepares for the transfer of data. When the master supplies the LTCLK/C signal, data is transferred either to or from the slave in units of 8-bits; the least significant bit is always transferred first. A transfer of 16-bits is made in two, 8-bit units with the most significant 8-bit unit first. In between the two 8-bit units the LTENA/C signal remains logic 1. Fig.9 shows an example of information transfer via SAA2521 interfaces. Note to Table 6 This mode only on the interface between SAA2521 and SAA2520. If SCALE = logic 1 then 16 x 16-bits If SCALE = logic 0 then 48 x 16-bits
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SAA2521
LTENA/C
LTCNT0(C)/1(C)
LTCLK(C)
LTDATA(C) 0 1 2 3 4 5 6 7
MBC128
Fig.9 Example of information transfer via SAA2521 interfaces.
LTENA/C
LTCNT0(C)/1(C)
LTCLK(C)
LTDATA(C) E0 E1 E2 E3 E4 E5 E6 E7
MBC129
Refer to the SAA2520 description for the meaning of these bits as they pass SAA2521 unchanged.
Fig.10 Extended settings (LTCNT1 and LTCNT0)
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
Extended settings (LTCNT1(C) = logic 0, LTCNT0(C) = logic 0) Eight information bits, generated by the microcontroller, are transferred in this mode. The SAA2521 will transfer these bits to the SAA2520 as soon as possible but does not monitor this information. Fig.10 shows the relationship of the extended settings. Allocation and SCALING information (LTCNT1C = logic 0, LTCNT0C = logic 1) In the encoding mode (FDIR = logic 0) the SAA2521 will transfer allocation information to the SAA2520. This will occur once for every SAA2520 frame.
SAA2521
The information will consist of 16 transfers each of 16-bits. To synchronize the SAA2521 operation with that of the SAA2520, following the first 16-bit transfer of allocation data the SAA2521 checks the SAA2520 status to ensure it is ready to receive the remainder of the allocation information. Transfer of allocation data is completed by sending settings. Between 16-bit transfers the LTENC line returns to 0 as shown in Fig.11. Fig.12 shows the order in which the bits occur on the interface during allocation information transfer. The 4-bit sub-band allocation unit contains the number of bits allocated to the sub-band MINUS 1. A value of 0000 indicates no bits allocated to that sub-band.
LTENC 16 bits LTCLKC
MBC130
16 bits
Fig.11 LTENC behaviour for 16-bit transfers.
Table 7
Allocation and SCALING information. BITS - - - - A14 A10 A6 A2 - - - - A13 A9 A5 A1 - - - - A8 A4 A0 LSB A12 CHANNEL L R L R 2* 2* (2 * (2 * SUB-BAND COUNT COUNT COUNT) + 1 COUNT) + 1
MSB A15 A11 A7 A3 Table 8 MSB SL15 SL13 SL7 SL5 - - - -
Allocation and SCALING information. BITS SL14 SL12 - SL11 - SL10 - SL9 SL6 SL4 - SL3 - SL2 - SL1 - SL0 - - SL8 LSB CHANNEL --L --R 00 SCALE FACTOR (COUNT) 00 SCALE FACTOR(COUNT) CONTENTS
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
With stereo encoding, Left and Right channels are designated L and R. This changes to channels I or II for 2-channel mono mode. If SCALE = logic 0 the transfer of allocation information will be followed by the transfer of scale factors. Each 16-bit transfer contains two scale factor indices. Algorithm showing the process of information transfer: COUNT: = logic 0 SEND ALLOCATION (COUNT) REPEAT READ STATUS UNTIL READY-TO-RECEIVE FOR COUNT: = 1 to 15 DO SEND ALLOCATION (COUNT) SEND SETTINGS IF SCALE = logic 0 THEN FOR COUNT; = logic 0 TO 31 DO SEND SCALE FACTORS (COUNT)
SAA2521
LTENA/C
LTCNT0(C)/1(C)
LTCLK(C)
LTDATA(C) bit : A or SL : 8 9 1 0 1 1 1 2 1 3 1 4 1 5 0 1 2 3 4 5 6 7
MEA691
Fig.12 Order of interface bits during allocation information transfer.
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SETTINGS (LTCNT1(C) = logic 1, LTCNT0(C) = logic 0) Without using the information, the SAA2521 transfers microcontroller settings to the SAA2520. Prior to sending settings, the microcontroller would utilize the SAA2521 status readings to ensure its readiness to accept and convey the data. Following reception of the settings the SAA2521 will cause the ready-to-receive bit to be logic 0 until the settings have been sent to the SAA2520. The microcontroller can only send this data when this bit is logic 1. Fig.13 shows the order of the bits on the interface.
SAA2521
LTENA/C
LTCNT0(C)/1(C)
LTCLK(C)
LTDATA(C) bit : S: 8 9 1 0 1 1 1 2 1 3 1 4 1 5 0 1 2 3 4 5 6 7
MBC132
Fig.13 The order of bits on the interface.
Table 9 MSB S15 S11 S9 S8 S7 S6 S5 S4 S3 S1
Microprocessor settings applied to the SAA2520 via the SAA2521. BITS - - S14 S10 - S13 - LSB S12 NAME bitrate index sample frequency DECODE ext 256fs 2-ch mono MUTE not used CH I - - S2 S0 Tr0 - Tr1 EMPHASIS FUNCTION bitrate indication 44.1, 48 or 32 kHz indic. 1 - decode; 0 - encode 1 - ext; 0 - int 1 - 2 ch mono; 0 - stereo 1 - mute; 0 - no mute - 1 - CH I; 0 - CH II transparent bits emphasis indication VALID IN encode encode enc/dec enc/dec encode enc/dec enc/dec decode encode encode
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
Status (LTCNT1(C) = logic 1, LTCNT0(C) = logic 1) The SAA2520 and SAA2521 operation may be checked by reading these bits. All, except the ready-to-receive bits, are generated by the SAA2520. The bit rate index indicates the bit rate of the sub-band signal in units of 32 kbits/s. The SAA2521 is designed for bit rates of 384, 256, 192 and 128 kbits/s only. With EMPHASIS activated (S1 = T1 = 0 and S0 = T0 = 1) only bit rates 384 and 256 kbits/s can be used. A ready-to-receive S or E indicates whether or not the SAA2521 can receive new settings or extended settings respectively from the microcontroller and should be checked prior to sending new information.
SAA2521
The SAA2521 can only be used to encode stereo (mode 00) signals and 2-channel mono (mode 10) signals. During the decoding mode this bit indicates if the operation of the SAA2520 is in synchronization with the MPEG coded signal. Should this not be the case the SAA2520 cannot perform the decoding. CLKOK indicates whether or not the Fs256 clock corresponds with the specified sample frequency. EMPHASIS indication may be used to apply correct de-emphasis. During the encoding 50 / 15 s mode the SAA2521 will correct the calculated allocation if emphasis is applied for a 44.1 kHz sampling frequency.
Table 10 Order of SAA2520 bits as they appear on the interface (see also Fig.14). MSB T15 T11 T9 T8 T7 T5 T4 T3 T1 - - T2 T0 - T6 T14 T10 BITS - T13 - LSB T12 NAME bitrate index ready-to-rec S ready-to-rec E MODE SYNC CLKOK Tr0 - Tr1 EMPHASIS FUNCTION bitrate indication 1 - ready; 0 - not ready 1 - ready; 0 - not ready sub-band signal mode ID synchronization indic. 1 - OK; 0 - not OK transparent bits emphasis indication VALID IN enc/dec enc/dec enc/dec enc/dec enc/dec dec enc/dec enc/dec enc/dec
sample frequency 44.1, 48 or 32 kHz indic.
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SAA2521
LTENA/C
LTCNT0(C)/1(C)
LTCLK(C)
LTDATA(C) bit : T: 8 9 1 0 1 1 1 2 1 3 1 4 1 5 0 1 2 3 4 5 6 7
MBC133
Fig.14 Order of appearance of bits on the interface.
Sample frequency indication. MSB 00 01 10 11 MODE identification. MSB LSB 00 01 10 11 MODE stereo joint stereo 2 - channel mono 1 - channel mono OUTPUT L and R L and R I or II as selected mono, no selection LSB 44.1 kHz 48 kHz 32 kHz -do not use default value
Frequency Range Limitation In encode mode the frequency range will be limited at lower rates. This is implemented by making the samples of higher frequency sub-bands equal to logic 0 before the allocation calculation. This automatically ensures that these sub-bands do not get any bits allocated. The following table shows the sub-bands affected and the resulting frequency range. The transfer of either 8-bits or 16-bits is permitted for the transfer of status information. When only 8-bits are transferred, these will always form the first byte and may be used in checking the ready-to-receive bit.
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
Table 11 Frequency examples. BIT RATE 256 kbit/s 192 kbit/s 128 kbit/s 48 kHz 48 kHz 44.1 kHz 48 kHz 44.1 kHz 32 kHz FS SUB-BANDS SET TO 0 29, 30, 31 20, 21, ... , 30, 31 22, 23, ... , 30, 31 12, 13, ... , 30, 31 13, 14, ... , 30, 31 20, 21, ... , 30, 31 > 15000 > 15159 > 9000 > 8957 >10000
SAA2521
@ FREQUENCY > 21750 Hz
t Le LTENA t su1 LTCNT0/1 t su4 LTCLK t su3 LTDATA bit : 0 1
MEA658 - 2
t h1
t h2
t su2
t cL
t cH
t h3
tle ts1 th1 ts2 th2 tlc thc ts3 th3 ts4
> 210 ns minimum LOW time LTENA prior to transfer > 50 ns set-up time LTCNT0, 1 before LTENA HIGH > 210 ns hold time LTCNT0, 1 after LTENA HIGH > 210 ns set-up time LTENA before LTCLK LOW > 210 ns hold time LTENA after LTCLK HIGH > 210 ns minimum LOW time LTCLK > 210 ns minimum HIGH time LTCLK > 210 ns set-up time LTDATA before LTCLK HIGH > 50 ns hold time LTDATA after LTCLK HIGH > 210 ns set-up time LTCLK before LTENA HIGH
Fig.15 Microcontroller to SAA2521 timing.
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SAA2521
LTENA
LTENA must remain HIGH
LTCNT0/1
LTCLK
MBC135 - 1
t W1 tw1 > 550 ns minimum time between two 8-bit transfers
Fig.16 16-bit transfers.
t Le LTENA t su1 LTCNT0/1 t su4 LTCLK t d1 LTDATA bit : 0 1
MEA657 - 2
t h1
t h2
t su2
t cL
t cH
t d2
t h5
t h6
tle ts1 th1 ts2 th2 tlc thc td1 td2 th5 tS4 th6
> 210 ns minimum LOW time LTENA prior to transfer > 50 ns set-up time LTCNT0, 1 before LTENA HIGH > 210 ns hold time LTCNT0, 1 after LTENA HIGH > 210 ns set-up time LTENA before LTCLK LOW > 210 ns hold time LTENA after LTCLK HIGH > 210 ns minimum LOW time LTCLK > < < > > > 210 ns minimum HIGH time LTCLK 385 ns maximum delay LTDATA after LTENA HIGH 385 ns maximum delay LTDATA after LTCLK HIGH 145 ns hold time LTDATA after LTCLK HIGH 210 ns set-up time LTCLK before LTENA HIGH 0 ns hold time LTDATA after LTENA LOW
Fig.17 SAA2521 to Microcontroller timing.
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SAA2521
LTENA
LTENA must remain HIGH
LTCNT0/1
LTCLK
MBC137
t W2 tw2 > 550 ns minimum time between two 8-bit transfers
Fig.18 16-bit transfers.
t Le LTENC t su1 LTCNT0(C)/1(C) t su4 LTCLKC t su3 LTDATAC bit : 0 1
MBC138 - 2
t h2
t su2
t cL
t cH
t h3
tle ts1 ts2 th2 tlc thc ts3 th3 ts4
> 400 ns minimum LOW time LTENA prior to transfer > 400 ns set-up time LTCNT0, 1C before LTENC HIGH > 200 ns set-up time LTENC before LTCLKC LOW > 400 ns hold time LTENC after LTCLK HIGH > 210 ns minimum LOW time LTCLKC > > > > 210 ns 210 ns 160 ns 900 ns minimum HIGH time LTCLKC set-up time LTDATAC before LTCLKC HIGH hold time LTDATAC after LTCLKC HIGH set-up time LTCLKC before LTENC HIGH
Fig.19 SAA2521 to SAA2520 timing.
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SAA2521
LTENC
LTENC must remain HIGH
LTCNT0(C)/1(C)
LTCLKC
MBC139
t W2 tw2 > 600 ns minimum time between two 8-bit transfers
Fig.20 16-bit transfers.
t Le LTENC t su1 LTCNT0(C)/1(C) t su4 LTCLKC t d1 LTDATAC bit : 0 1
MBC140 - 2
t h2
t su2
t cL
t cH
t d2
t h5
t h6
tle ts1 ts2 th2 tlc thc td1 td2 ts4 th5 th6
> 400 ns minimum LOW time LTENC prior to transfer > 400 ns set-up time LTCNT0, 1C before LTENC HIGH > 200 ns set-up time LTENC before LTCLKC LOW > 400 ns hold time LTENC after LTCLKC HIGH > 210 ns minimum LOW time LTCLKC > 210 ns minimum HIGH time LTCLKC < 300 ns maximum delay LTDATAC after LTENC HIGH < > > > 300 ns maximum delay LTDATAC after LTCLKC HIGH 900 ns set-up time LTCLKC before LTENC HIGH 160 ns hold time after LTCLKCC HIGH 0 ns hold time LTDATAC after LTENC LOW
Fig.21 SAA2520 to SAA2521 timing.
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SAA2521
LTENC
LTENC must remain HIGH
LTCNT0(C)/1(C)
LTCLKC
MBC141
t W2
tw1 > 600 ns
minimum time between two 8-bit transfers
Fig.22 16-bit transfers.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI IDD II Io Ptot Tstg Tamb Ves1 Ves2 Notes 1. Input voltage should not exceed 6.5 V unless otherwise specified. 2. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 3. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. supply voltage input voltage (note 1) supply current input current output current total power dissipation storage temperature operating ambient temperature electrostatic handling (note 2) electrostatic handling (note 3) PARAMETER MIN. -0.5 -0.5 - - - - -55 -40 -1500 -70 MAX. 6.5 VDD + 0.5 100 10 40 550 + 150 + 85 1500 70 V V mA mA mA mW C C V V UNIT
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
DC CHARACTERISTICS VDD = 3.8 to 5.5 V; Tamb = -40 to 85 C; unless otherwise specified. SYMBOL Supply VDD IDD IDD IPWRDWN Inputs VIL VIH II Outputs VOL VOH Ioz Note LOW level output voltage HIGH level output voltage note 1 note 1 - VDD - 0.5 - - - - 0.4 - LOW level input voltage HIGH level input voltage input current 0 0.7 VDD - - - - supply voltage range operating current operating current stand-by current VDD = 3.8 V VDD = 5 V in power-down mode 3.8 - - - 5 15 25 100 5.5 30 50 - PARAMETER CONDITIONS MIN. TYP.
SAA2521
MAX.
UNIT
V mA mA A
0.3 VDD VDD 10
V V A
V V A
3-state outputs OFF state current Vi = 0 to 5.5 V 10
1. Maximum load current for LTDATA, LTCNT1C, LTCNT0C, LTENC, LTCLKC, TEST1, TEST2, FDAC, FDAF = 2 mA; for LTDATAC = 3 mA.
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
AC CHARACTERISTICS VDD = 3.8 to 5.5 V; Tamb = -40 to 85 C. SYMBOL CLOCK CLK24 fs frequency 23 - - note 1 note 2 15 15 24.576 - - - - 26 PARAMETER CONDITIONS MIN. TYP.
SAA2521
MAX.
UNIT
MHz
CLOCK Fs256 fs CI tSU tSU frequency fs = 48 kHz 13 MHz
Inputs FSYNC, SWS, LTCNT1, LTCNT0, LTENA, LTCLK, LTDATA, LTDATAC, FDAF, FDAC, SCL, SWS input capacitance 10 - - pF
INPUT SET-UP TIME set-up time of inputs related to CLK24 rising edge set-up time of inputs related to 256fs rising edge ns ns
INPUT HOLD TIME tHD tHD hold time of inputs related to CLK24 note 1 rising edge hold time of inputs related to 256fs rising edge note 2 20 10 - - - - ns ns
Outputs LTDATA, LTDATAC, LTCNT1C, LTCNT0C, LTENC, LTCLKC, FDAF, FDAC Co td td output capacitance output delay time related to CLK24 rising edge output delay time related to 256fs rising edge CL = 25 pF; note 3 CL = 25 pF; note 4 - - - - - - 10 45 30 pF ns ns
3-state outputs tPHZ tPLZ tPZH tPZL Notes 1. Inputs FSYNC, SWS, LTCNT1, LTCNT0, LTENA, LTCLK, LTDATA, LTDATAC 2. Inputs FDAF, FDAC, SCL, SWS 3. Outputs LTDATA, LTDATAC, LTCNT1C, LTCNT0C, LTENC, LTCLK 4. Outputs FDAF, FDAC disable time HIGH-to-Z disable time LOW-to-Z enable time Z-to-HIGH enable time Z-to-LOW CL = 25 pF CL = 25 pF CL = 25 pF CL = 25 pF - - - - - - - - 65 65 65 65 ns ns ns ns
August 1993
25
Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
SAA2521
SOT205-1
c
y X
33 34
23 22 ZE
A
e E HE wM bp pin 1 index 44 1 11 ZD bp D HD wM B vM B 12 detail X L Lp A A2 A1 (A 3)
e
vM A
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.60 A1 0.25 0.05 A2 2.3 2.1 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 14.1 13.9 E (1) 14.1 13.9 e 1 HD 19.2 18.2 HE 19.2 18.2 L 2.35 Lp 2.0 1.2 v 0.3 w 0.15 y 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT205-1 REFERENCES IEC 133E01A JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
August 1993
26
Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA2521
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
August 1993
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Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG layer 1 audio compression applications
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA2521
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
August 1993
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