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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16307-3E
32-Bit RISC Microcontroller
CMOS
FR Family MB91110 Series
MB91110/MB91V110
s DESCRIPTION
The MB91110 series is a standard single-chip micro controller featuring various I/O resources and bus control mechanisms to incorporate the control with required for high performance high-speed CPU processes, having a 32-bit RISC CPU (FR30 series) in its core. Although external bus access is the basis for supporting a large address space accessible by a 32-bit CPU, a 1-KB instruction cache memory has been built-in to increase the instruction/ execution speed of the CPU. This unit features the optimal specifications for incorporating applications that require high performance CPU processing power such as navigation systems, high performance facsimile systems, printer control, etc.
s FEATURES
FR30CPU * 32-bit RISC, load / store architecture, 5-level pipeline * Operating frequency : external 25 MHz, internal 50 MHz * Multi-purpose register : 32 bits x 16 * 16-bit fixed length instructions (basic instruction) , 1 instruction per cycle * Instructions for barrel shift, bit processing and inter memory transfers : Instructions suited to loading purposes (Continued)
s PACKAGE
144-pin plastic LQFP
(FPT-144P-M08)
MB91110 Series
(Continued) * Function entry / exit instruction, multi load / store instruction of register details : Instruction capable of handling High level language instruction. * Register Interlock function : Simplification of assembler description * Branch instruction with delay slot : Reduction in overheads in case of branching * Multiplier is built-in / Supported at instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles * Interruption (saving PC and PS) : 6 cycles, 16 priority levels
Bus Interface * 24-bit address bus (16 MB space) * Operating frequency : 25 MHz * 16- / 8-bit data bus * Basic external bus cycle : 2 clock cycles * Chip select output that can be set to a minimum 64-Kbyte units * Interface support for various memories DRAM interface (areas 4, 5) * Automatic waiting cycle : Can be randomly set from 0 to 7 cycles per area * Unused data and address pins can be used as input/output ports. * Supports "little endian" mode (One area is selected from areas 1 to 5) DRAM Interface * 2-bank individual control (area 4, 5) * Normal mode / high speed page mode * Basic bus cycles : normally 5 cycles, 1 cycle access is possible in high-speed page mode. * Programmable waveform : 1 cycle waiting can be inserted automatically in RAS and CAS. * DRAM refresh CBR refresh (Interval is randomly set using the 6-bit timer.) Self refresh mode * Supports addresses for 8, 9, 10 and 12 columns * 2CAS/1WE or 2WE/1CAS can be selected. Cache Memory * 1 KB instruction cache * 2 way set associative * 32 blocks / way, 4 entries (4 words) / block * Lock function : Residing in the specified program codes at cache DMA Controller (DMAC) * 5 channels * External external 2.5 access cycles / transfer (if 2 clock cycles are defined as 1 access cycle) * Internal external 1.5 access cycles / transfer (if 2 clock cycles are defined as 1 access cycle) * Address register (inc, dec, or reload are possible) : 32 bits x 5 channels * Transfer count register (reload possible) : 16 bits x 5 channels * Transfer factors : external pin / built-in resources interruption request / software * Transfer sequence Step transfer / block transfer Burst / consecutive transfer * Transfer data length : 8-bit, 16-bit or 32-bit can be selected * Suspension is possible using NMI / interruption request 2
MB91110 Series
UART * Fully duplicated double buffer * Data length : 7 to 9 bits (without parity) , 6 to 8 bits (with parity) * Asynchronous (start-stop synchronization) or CLK synchronized communication can be selected. * Multiprocessor mode * Dedicated baud rate generator is built-in. * External clock can be used as the transfer clock * Baud rate clock can be output * Error detection : parity, frame, overrun PPG Timer * 16 bits, 6 channels (frequency setting register / duty setting register) * PWM function or one-shot function can be selected * Initiation : Software or external trigger can be selected A/D Converter (sequential conversion type) * 10-bit resolution, 8 channels * Sequential comparison conversion : 5.6 s in the case of 25 MHz * Sample & hold circuit is built-in. * Conversion mode : Single, scan or repeat conversion can be selected. * Initiation : Software, external trigger or built-in timer can be selected. Reloading Timer * 16-bit timer : 2 channels * Internal clock : 2 clock cycle resolutions, 2, 8 or 32 cycles can be selected. * Pin input : event counter input / gate function * Rectangular wave output Other Interval Timer * Watchdog timer : 1 channel Bit Search Module * Searches the first "1" / "0" change bit positions within 1 cycle from MSB in 1 word. Interruption Controller * External interruption input : Mask impossible interruption (NMI) , normal interruption x 8 (INT0 to INT7) * Internal interruption factors : UART, DMAC, A/D, reloading timer, PPG timer, delay interruption * Priority levels are programmable except for mask impossible interruption (16 levels) Reset Factors * Power-on reset / hardware standby / watchdog timer / software reset / external reset Low Power Consumption Mode * Sleep / stop mode Clock Control * Gear functions : Operating clock frequencies peripheral to the CPU can be set randomly and independently. Gear locks can be selected from 1/1, 1/2, 1/4 or 1/8 (or 1/2, 1/4, 1/8, or 1/16) . Others * Package : LQFP-144 * CMOS technology : 0.35 m * Power : 5.0 V 10%, 3.3 V 5% 3
MB91110 Series
s PRODUCT LINEUP
MB91V110 (For evaluation) I-RAM RAM ROM I-$ DSU3 evaluation function 16 Kbyte 5 Kbyte 1 Kbyte Mounted MB91110 (I-RAM mounted version) 16 Kbyte 5 Kbyte 1 Kbyte
4
MB91110 Series
s PIN ASSIGNMENT
(TOP VIEW)
TRG1, 4/PE2 TRG0, 3/PE1 ATG/PE0 VSS VCC5 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVSS AVRL AVRH AVCC (OPEN) (OPEN) (OPEN) (OPEN) (OPEN) (OPEN) (OPEN) (OPEN) (OPEN) VCC3 HST RST VSS X1 X0 VCC5 MD2 MD1 MD0 105 100 95 90 85 80 PE3/TRG2, 5 PF0/INT0 PF1/INT1 PF2/INT2 PF3/INT3 PF4/INT4 PF5/INT5 PF6/INT6 PF7/INT7 VSS PG0/DREQ0 PG1/DACK0 PG2/DEOP0 PG3/DREQ1 PG4/DACK1 PG5/DEOP1 VCC5 VCC3 PH0/DREQ2 PH1/DACK2 PH2/DEOP2 PH3/SI PH4/SO PH5/SCK PH6/TI0 PH7/TO0 VSS PI0/TI1 PI1/TO1 PI2/PPG0 PI3/PPG1 PI4/PPG2 PI5/PPG3 PI6/PPG4 PI7/PPG5 VSS 75
110 70
115 65
120 60
125 55
130 50
135 45
140
INDEX 40
10
15
20
25
30
P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 VSS D24 D25 D26 D27 D28 D29 D30 D31 VCC5 VSS A00 A01 A02 A03 A04 A05 A06 A07 VSS A08 A09 A10 A11 A12 A13 A14 A15
(FPT-144P-M08)
35
NMI DW1/PB7 CS1H/PB6 CS1L/PB5 RAS1/PB4 VSS VCC5 DW0/PB3 CS0H/PB2 CS0L/PB1 RAS0/PB0 CLK/PA6 CS5/PA5 CS4/PA4 CS3/PA3 CS2/PA2 CS1/PA1 CS0 VSS WR1/P85 WR0 RD BRQ/P82 BGRNT/P81 RDY/P80 VCC3 VCC5 A23/P67 A22/P66 A21/P65 A20/P64 A19/P63 A18/P62 A17/P61 A16/P60 VSS
1
5
5
MB91110 Series
s PIN DESCRIPTIONS
Pin no. 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 38 39 40 41 42 43 44 45 48 Pin name D16/P20 D17/P21 D18/P22 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 D24 D25 D26 D27 D28 D29 D30 D31 A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16/P60 A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66 A23/P67 RDY/P80 I/O* Circuit type Function
I/O
C
These pins use bits 16 to 23 of the external data bus. They can be used as a port (P20 to P27) if the external bus width is 8 bits.
I/O
C
These pins use bits 24 to 31 of the external data bus.
I/O
C
These pins use bits 00 to 07 of the external address bus.
I/O
C
These pins use bits 08 to 15 of the external address bus.
I/O
C
These pins use bits 16 to 23 of the external address bus.
I/O
C
This is for external ready input. "0" is input if the bus cycle being executed is incomplete. It can be used as a port when not otherwise used. This is the external bus open reception output. "L" is output if the external bus is opened. It can be used as a port when not otherwise used.
49
BGRNT/P81
I/O
H
(Continued)
6
MB91110 Series
Pin no. 50 51 52
Pin name BRQ/P82 RD WR0
I/O* I/O O O
Circuit type C G G
Function This is the external bus open request input. "1" is input if the external bus is to be opened. It can be used as a port when not otherwise used. This is the external bus read strobe. This is the external bus write strobe. 16-bit bus width 8-bit bus width WR0 (Port is possible) D31-24 D23-16 WR0 WR1
53
WR1/P85
I/O
H
55 56 57 58 59 60
CS0 CS1/PA1 CS2/PA2 CS3/PA3 CS4/PA4 CS5/PA5
O
G
Chip select 0 output (Low active) Chip select 1 output (Low active) Chip select 2 output (Low active) Chip select 3 output (Low active) Chip select 4 output (Low active) Chip select 5 output (Low active) They can be used as ports when not otherwise used. This is the system clock output. The same clock as the standard clock is output. This can be used as a port when not otherwise used. RAS output with DRAM bank 0. CASL output with DRAM bank 0. CASH output with DRAM bank 0. WE output with DRAM bank 0. (Low active) RAS output with DRAM bank 1. CASL output with DRAM bank 1. CASH output with DRAM bank 1. WE output with DRAM bank 1. (Low active) They can be used as ports when not otherwise used. Non Maskable Interrupt (NMI) input. (Low active) These are mode pins from 0 to 2. Basic MCU operation modes are set using these pins. They should be connected directly to VCC or VSS for use. Clock (oscillation) input. Clock (oscillation) output. This is the external reset input. (Low active) This is the hardware standby input. (Low active) Set this to OPEN. Set this to OPEN.
I/O
H
61
CLK/PA6
I/O
H
62 63 64 65 68 69 70 71 72 73 74 75 77 78 80 81 83 84 85 86
RAS0/PB0 CS0L/PB1 CS0H/PB2 DW0/PB3 RAS1/PB4 CS1L/PB5 CS1H/PB6 DW1/PB7 NMI MD0 MD1 MD2 X0 X1 RST HST (OPEN) (OPEN) (OPEN) (OPEN)
I/O
H
I I I O I I
E I
A B E
(Continued)
7
MB91110 Series
Pin no. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103
Pin name (OPEN) (OPEN) (OPEN) (OPEN) (OPEN) AVCC AVRH AVRL AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
I/O*
Circuit type
Function
Set this to OPEN.
Set this to OPEN. VCC power supply for the A/D converter. A/D converter reference voltage (high potential side). Be sure to turn on/off this pin with potential higher than AVRH applied to VCC. A/D converter reference voltage (low potential side). VSS power supply for the A/D converter.
I
D
[AN0 to 7] A/D converter analog input.
106
ATG/PE0
I/O
H
[ATG] This is the external trigger input for the A/D converter. This function is always used if selected as the initiation factor for A/D, so output by other functions should be stopped except when it is carried out intentionally. [PE0] This is a general-purpose input/output port. [TRG0 to 5] These are external trigger input pins of the PPG.
107 108 109 110 111 112 113 114 115 116 117
TRG0, 3/PE1 TRG1, 4/PE2 TRG2, 5/PE3 INT0/PF0 INT1/PF1 INT2/PF2 INT3/PF3 INT4/PF4 INT5/PF5 INT6/PF6 INT7/PF7
I/O
H
[PE1 to 3] These are general-purpose input/output ports. [INT0 to 7] These are external interruption request inputs. This input is always used while the corresponding external interruption is permitted, so output using other functions should be stopped except when carried out intentionally. [PF0 to 7] These are general-purpose input/output ports. [DREQ0] This is the DMA external transfer request input (ch 0) . This input is always used if selected as the transfer factor for DMAC, so outputs from other functions should be stopped except when carried out intentionally. [PG0] This is a multi-purpose input/output port.
I/O
F
119
DREQ0/PG0
I/O
H
(Continued)
8
MB91110 Series
Pin no.
Pin name
I/O*
Circuit type
Function [DACK0] This is the DMAC external transfer request reception output (ch 0) . This function is effective if the transfer request reception output specification of DMAC is permitted. [PG1] This is a multi-purpose input/output port. This function is effective if the transfer request reception output specification of DMAC is prohibited. [DEOP0] This is the DMA transfer end signal output (ch 0) . This function is effective if the transfer end signal output specification of DMAC is permitted. [PG2] This is a multi-purpose input/output port. This function is effective if the transfer end signal output specification of DMAC is prohibited. [DREQ1] This is the DMA external transfer request input (ch 1) . This input is always used if selected as the transfer factor of DMAC, so output using other functions should be stopped except when carried out intentionally. [PG3] This is a multi-purpose input/output port. [DACK1] This is the DMAC external transfer request reception output (ch 1) . This function is effective if the transfer request reception output specification of DMAC is permitted. [PG4] This is a multi-purpose input/output port. This function is effective if the transfer request reception output specification of DMAC is prohibited. [DEOP1] This is the DMA transfer end signal output (ch 1) . This function is effective if the transfer end signal output specification of DMAC is permitted. [PG5] This is a multi-purpose input/output port. This function is effective if the transfer end signal output specification of DMAC is prohibited. [DREQ2] This is the DMA external transfer request input (ch 2) . This input is always used if selected as the transfer factor of DMAC, so output using other functions should be stopped except when carried out intentionally. [PH0] This is a multi-purpose input/output port. [DACK2] This is the DMAC external transfer request reception output (ch 2) . This function is effective if the transfer request reception output specification of DMAC is permitted. [PH1] This is a multi-purpose input/output port. This function is effective if the transfer request reception output specification of DMAC is prohibited.
120
DACK0/PG1
I/O
C
121
DEOP0/PG2
I/O
C
122
DREQ1/PG3
I/O
H
123
DACK1/PG4
I/O
C
124
DEOP1/PG5
I/O
C
127
DREQ2/PH0
I/O
H
128
DACK2/PH1
I/O
C
(Continued)
9
MB91110 Series
Pin no.
Pin name
I/O*
Circuit type
Function [DEOP2] This is the DMA transfer end signal output (ch 2) . This function is effective if the transfer end signal output specification of DMAC is permitted. [PH2] This is a multi-purpose input/output port. This function is effective if the transfer end signal output specification of DMAC is prohibited. [SI] This is UART data input. This input is always used while UART inputs, so outputs from other functions should be stopped except when carried out intentionally. [PH3] This is a general-purpose input/output port. [SO] This is UART data output. This function is effective when UART data output specification is permitted.
129
DEOP2/PH2
I/O
C
130
SI/PH3
I/O
H
131
SO/PH4
I/O
C
[PH4] This is a general-purpose input/output port. This function is effective when UART data output specification is prohibited. [SCK] This is UART clock input/output. Clock output is effective when UART clock output specification is permitted.
132
SCK/PH5
I/O
H
[PH5] This is a general-purpose input/output port. This function is effective when UART clock output specification is prohibited. [TI0] This is reload timer 0 input. It is always used when reload timer input is permitted, so outputs from other functions should be stopped except when carried out intentionally. [PH6] This is a general-purpose input/output port. [TO0] This is reload timer 0 Output. This function is effective when reload timer specification is permitted. [PH7] This is a general-purpose input/output port. This function is effective when reload timer specification is prohibited. [TI1] This is reload timer 1 input. It is always used when reload timer input is permitted, so outputs from other functions should be stopped except when carried out intentionally. [PI0] This is a general-purpose input/output port. [T01] This is the reload timer 1 output. This function is effective if the output specification of the reload timer is permitted.
133
TI0/PH6
I/O
H
134
TO0/PH7
I/O
C
136
TI1/PI0
I/O
H
137
TO1/PI1
I/O
C
[PI1] This is a multi-purpose input/output port. This function is effective if the output specification of the reload timer is prohibited.
(Continued)
10
MB91110 Series
(Continued) Pin no. Pin name
138 139 140 141 142 143 18 46 66 76 104 125 47 82 126 9 19 28 37 54 67 79 105 118 135 144 PPG0/PI2 PPG1/PI3 PPG2/PI4 PPG3/PI5 PPG4/PI6 PPG5/PI7
I/O*
Circuit type
Function [PPG0 to 5] This is the PPG timer 1 output. This function is effective if the output specification of the PPG timer is permitted. [PI2 to 7] This is a multi-purpose input/output port. This function is effective if the output specification of the PPG timer is prohibited.
I/O
C
VCC5
This provides power for the 5 V digital circuit system.
VCC3
This provides power for the 3 V digital circuit system.
VSS
This is the earth level for digital circuits.
* : I/O shown above indicates input/output classification. Note : The I/O port and resource input/outputs for most of the above pins are multiplexed, i.e. Pxx/xxxx. In the event of both the port and resource outputs were to use the same pins, the resource is given priority.
11
MB91110 Series
s I/O CIRCUIT TYPE
Type
X1 Clock input
Circuit types
Remarks * Oscillation feedback resistance : approximately 1 M * 12.5 MHz oscillation
A
X0
STANDBY CONTROL
VCC P-channel type Tr
* CMOS level hysteresis input Without standby control With pull-up resistance
B
VSS
Digital input
Digital output
* CMOS level output CMOS level input With standby control
Digital output
C
Digital input STANDBY CONTROL
* A/D converter Analog input pin D
Analog input
(Continued)
12
MB91110 Series
(Continued) Type
Circuit types
Remarks * CMOS level hysteresis input Without standby control
E
Digital input
Digital output
* CMOS level output * CMOS level hysteresis input Without standby control
F
Digital output
Digital input
* CMOS level output
Digital output
G
Digital output
Digital output
* CMOS level output * CMOS level hysteresis input With standby control
Digital output
H
Digital input STANDBY CONTROL
* CMOS level input Without standby control
I
Digital input
13
MB91110 Series
s HANDLING DEVICES
* Preventing Latch-up The "Latch-up" phenomenon may be generated if a voltage in excess of VCC or lower than VSS is applied to the input/output pins, or if the voltage exceeds the rating between VCC and VSS. If latch-up is generated, the electrical current increases significantly and may destroy certain components due to the excessive heat, so great care must be taken to ensure that the maximum rating is not exceeded during use. * Handling Unused Input Pins Input pins that are not used should be pulled up or down as they may cause erroneous operations if they are left open. * External Reset Input "L" level should be input to the RST pin, which is required for at least five machine cycles to ensure the internal status is reset. * Using External Clocks If external clock is used, X0 pin should be provided, and X1 pin should be provided with reverse phase to X0 pin input. If the STOP mode (oscillation stop mode) is used simultaneously, the X1 pin is stopped with the "H" output. So, when STOP mode is specified, approximately 1 k of resistance should be added externally. An example of the external clock usage methods is shown in the following circuit. Example of External Clock Usage (normal case)
X0 X1 MB91110
Note : Resistance must be added to the X1 pin if the STOP mode (oscillation stop mode) is used. * Power Supply Pins In products with multiple Vcc or Vss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect Vcc and Vss pins via the lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between Vcc and Vss pins near the device. * Crystal Oscillator Circuits Noise around the X0 or X1 pins may cause erroneous operation. Make sure to provide bypass capacitors via shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure that lines of oscillation circuits not cross the lines of other circuit. A printed circuit board artwork surrounding the X0 and X1 pins with ground area for stabilizing the operation is highly recommended .
14
MB91110 Series
* N.C. Pins N.C. pins must be opened for use. * Mode Pins (MD0 to MD2) Those pins must be directly connected to VCC or VSS for use. Pattern length between VCC or VSS and each mode pin on the printed-circuit board should be arranged to be as short as possible to prevent the test mode being erroneously turned on due to noise, they should also be connected with low impedance. * In the Event that Power Is Turned on The RST pin must be started from "L" level when the power is turned on, and when the power is adjusted to the VCC level it should be changed to the "H" level after being left for at least five cycles of the internal operation clock. * Original Oscillation Input in the Event that Power Is Turned on The clock must be input until the waiting status for oscillation stability is reset in the event that power is turned on. * Hardware Standby in the Event that Power Is Turned on Standby is not set in the event that power is turned on while the HST pin is set at "L" level. The HST pin becomes effective after being reset, but it must first be returned to "H" level. * Power on Reset When power is turned on, "Power on reset" must be executed. If the power voltage falls below the guaranteed operating voltage, "Power on reset" must be executed by turning on power supply again. * Restrictions for Standby Programs to be set for stop and sleep must be placed address area of the external memory. If placed in the RAM address area on the I-bus, operation can not be guaranteed after returning. * Execution of Programs in I-RAM Areas In the event that programs in the I-RAM areas are executed, enter the I-RAM areas in accordance with the JMP system instruction. Conversely, when changing from programs in the I-RAM area to those in other areas, exit in accordance with the JMP system instructions. * Caution on Operation during PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
15
MB91110 Series
s BLOCK DIAGRAM
FR30 CPU
(16 bit)
Bit Search Module
Instruction RAM 16 KB
I-bus
DMAC (5 ch) DREQ0 DREQ1 DREQ2 DACK0 DACK1 DACK2 DEOP0 DEOP1 DEOP2 RAM 5 KB D-bus (32 bit)
Instruction Cache 1 KB
Harvard Prinston Bus Converter 50 MHz 25 MHz
50 MHz 25 MHz
PLL 50 MHz X0 X1 RST HST INT0 INT7 NMI AN0 AN7 ATG AVCC AVSS AVRH AVRL TI0 TI1 TO0 TO1
32 bit 16 bit Bus Converter
Bus Controller
D31 D16 A23 A00 RD WR0 WR 1 RDY CLK CS0 CS5 BRQ BGRNT RAS0 CS0L CS0H DW0 RAS1 CS1L CS1H DW1
Clock Control Unit
C-bus
DRAM Controller
Interrupt Control Unit
(32 bit)
Port 0 B
A/D Converter (8 ch)
Reload Timer (2 ch)
R-bus (16 bit)
UART
SI SO SCK PPG0 PPG5 TRG0 TRG5
Port E I
16 bit PPG Timer (6 ch)
Notes : * Pins are described per function. Some of the pins are multiplexed. * In the event that REALOS is used, an external interruption or built-in timer should be used to control the time.
16
MB91110 Series
s MEMORY SPACE
The FR30 series has 4 Gbytes (232 addresses) of logic address space which the CPU accesses linearly.
1. Memory Map
External ROM external bus modes 0000 0000H I/O 0000 0400H I/O 0000 0800H Access is prohibited 0000 1000H Built-in RAM 5 KB 0000 2400H Access is prohibited 0001 0000H External area 0008 0000H Access is prohibited 000B C000H I-RAM 16 KB 000C 0000H External area 0010 0000H External area FFFF FFFFH Direct addressing area (Refer to "I/O MAP")
Note : MB91110 series only supports external ROM external bus mode. * Direct addressing area The following areas of the address space are used for I/O. This area is called the "direct addressing area" and the address of the operand can be specified directly during instruction. The direct area differs depending on data size to be accessed. * Byte data access * Half-word data access * Word data access : 0-0FFH : 0-1FFH : 0-3FFH
17
MB91110 Series
2. Registers
There are two types of multi-purpose registers in the FR family. One is a dedicated purpose register that exists within the CPU and the other is a multi-purpose register that exists in the memory. * Dedicated Registers Program Counter (PC) Program Status (PS) Table Base Register (TBR) Return Pointer (RP) System Stuck Pointer (SSP) User Stuck Pointer (USP) Multiplication and Division Results Resister (MDH/MDL)
: 32-bit length; indicates instruction storage position. : 32-bit length; stores register pointers and condition codes. : Holds the starting address of the vector table to be used for Exception, Interruption and Trapping (EIT) . : Holds the address to which you will return to from the sub-routine. : Indicates the systems stuck position. : Indicates the user's stuck position. : 32-bit length; These are the registers for multiplication and division.
32 bit PC Program Counter
Initial values
XXXX XXXXH (Undecided)
PS
Program Status
TBR
Table Base Register
000F FC00H XXXX XXXXH (Undecided) 0000 0000H XXXX XXXXH (Undecided) XXXX XXXXH (Undecided) XXXX XXXXH (Undecided)
RP
Return Pointer
SSP
System Stuck Pointer
USP
User Stuck Pointer
MDH MDL
Multiplication and Division Results Resister
* Program Status (PS) PS is the register that holds the program status and is classified into three categories, namely, Condition Code Register (CCR) , System Condition Code Register (SCR) and Interruption Level Master Register (ILM) .
31 to 21 20 PS
19
18
17
16 15 to 11 10
9 D0 SCR
8 T
7
6
5 S
4 I
3 N
2 Z
1 V
0 C
ILM4 ILM3 ILM2 ILM1 ILM0 ILM
D1
CCR
18
MB91110 Series
* Condition Code Register (CCR) S flag : Specifies the stuck pointer to be used as R15. I flag : Controls permission and prohibition of user interruption requests. N flag : Indicates codes when the computation results are defined as integers that are expressed in complements of 2. Z flag : Indicates if arithmetic results were "0." Indicates when operands are used for computation and defined as integers expressed in comV flag : plements of 2, and indicates whether or not an overflow is generated as a result of the computation. C flag : Indicates whether carrying or borrowing is generated from the highest bit as a result of the computation. * System Condition Code Register (SCR) T flag : Specifies whether or not the step- trace- trap will be valid. * Interruption Level Mask Register (ILM) ILM4 to ILM0 : Holds the interruption level mask values, and those values that are held by the ILM are used for the level mask. Interruption requests can only be accepted when the interruption levels handled within the interruption requests to be input into the CPU are stronger than the levels shown by the ILM. ILM4 0 0 1 ILM3 0 1 1 ILM2 0 0 1 ILM1 0 0 1 ILM0 0 0 1 Interruption level 0 15 31 Weak Strength Strong
19
MB91110 Series
s MULTI-PURPOSE REGISTERS
The multi-purpose registers are CPU registers (R0 to R15) which are used as accumulators for various computations and memory access pointers (field that indicates the address) . * Register bank configuration
32-bit Initial value
R0 R1
XXXX XXXXH
R12 R13 R14 R15
AC (Accumulator) FP (Frame Pointer) SP (Stack Pointer)
XXXX XXXXH 0000 0000H
Special purposes are assumed for the following three registers out of the 16 registers. Thus, some instructions are emphasized. R13 : Virtual accumulator (AC) R14 : Frame Pointer (FP) R15 : Stack Pointer (SP) Initial values for R0 to R14 on resetting are unspecified. The initial value of R15 will be 0000 0000H (SSP value) .
20
MB91110 Series
s MODE SETTING
1. Pins
* Mode pins and set mode Mode pins Mode name MD2 MD1 MD0 0 0 0 0 1 0 0 1 1 0 1 0 1 External vector mode 0 External vector mode 1 Internal vector mode Reset vector access areas External External Internal External data bus width 8-bit 16-bit (Mode register) Bus modes
External ROM external bus mode Setting is prohibited Single chip mode* Usage is prohibited
* : MB91110 series is not supported single chip mode.
2. Register
* Mode register (MODR) and set mode Address 0000 07FFH Initial value Access XXXXXXXXB W
M1
M0
*
*
*
*
*
Bus mode set bit
*
W : Write only X : Undecided * : "0" should always be written for bits other than M1 and M0.
* Bus mode set bit and its functions M1 M0 0 0 1 1 0 1 0 1 Single chip mode
Functions
Remarks Not supported Not supported Setting is prohibited
Internal ROM external bus mode External ROM external bus mode
21
MB91110 Series
s I/O MAP
Address 000000H 000004H 000008H 00000CH 000010H 000014H 000018H 00001CH 000020H 000024H 000028H 00002CH 000030H 000034H ADCR 000038H TMRLR SSR (R/W) PDRG (R/W) PDRH (R/W) PDRB Register +0 (R/W) PDR2 PDR6 PDRA +1 (R/W) (R/W) (R/W) XXXXXXXX XXXXXXXX - XXXXXX PDRE PDRI (R/W) (R/W) PDRF (R/W) +2 PDR8 +3 (R/W) Port data register Internal resource
XXXXXXXX
- - X - - XXX
- - - - XXXX XXXXXXXX
XXXXXXXX Reserved Reserved
- - XXXXXX
XXXXXXXX
SIDR/SODR (R/W)
SCR
(R/W)
SMR
(R/W) UART
00001-00 TMRLR
XXXXXXXX CDCR (R/W) 0--11111 (W)
00000100 TMR TMCSR
00000-00
(R) (R/W) (R) (R/W) (R/W) Reload timer 1 Reload timer 0
XXXXXXXX XXXXXXXX (W)
XXXXXXXX XXXXXXXX - - - -0000 00000000 TMR TMCSR XXXXXXXX XXXXXXXX ----0000 00000000
XXXXXXXX XXXXXXXX (R)
ADCS
- - - - - - XX XXXXXXXX
00000000 00000000
A/D converter (Sequential comparison type) Reserved
00003CH
(Continued)
22
MB91110 Series
Address 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH 000060H 000064H 000068H 00006CH 000070H 000074H 000078H 00007CH 000080H
Register +0 +1 Access is prohibited PDUT (W) PCSR PCNH (R/W) PCNL (W) (R/W) (W) PCNL (R/W) (W) PCNL (R/W) (W) XXXXXXXX PCNL (R/W) (W) PCNL (R/W) (W) PCNL (R/W) 00000000 +2 +3
Internal resource Reserved
XXXXXXXX XXXXXXXX 0000000PCSR PCNH (R/W) 00000000
PPG0
XXXXXXXX XXXXXXXX Access is prohibited PDUT (W)
XXXXXXXX XXXXXXXX 0000000PCSR PCNH (R/W) 00000000
PPG1
XXXXXXXX XXXXXXXX Access is prohibited PDUT (W)
XXXXXXXX XXXXXXXX 0000000PCSR XXXXXXXX PCNH (R/W) 0000000PCSR PCNH (R/W) 00000000
PPG2
XXXXXXXX XXXXXXXX Access is prohibited PDUT (W)
PPG3
XXXXXXXX XXXXXXXX Access is prohibited PDUT (W)
XXXXXXXX XXXXXXXX 0000000PCSR PCNH (R/W) 00000000
PPG4
XXXXXXXX XXXXXXXX Access is prohibited PDUT (W)
XXXXXXXX XXXXXXXX 0000000 00000000
PPG5
XXXXXXXX XXXXXXXX
Reserved
(Continued)
23
MB91110 Series
Address 000084H 000088H 00008CH 000090H 000094H 000098H 00009CH 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H EIRR
Register +0 +1 +2 +3
Internal resource
Reserved (R/W) ENIR (R/W) Reserved External interruption/ NMI
00000000 ELVR
00000000 (R/W)
00000000 00000000
(Continued)
24
MB91110 Series
Address 0000C8H 0000CCH 0000D0H 0000D4H 0000D8H to 0000FCH 000100H to 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH DDRG
Register +0 +1 +2 +3
Internal resource
Reserved (W) DDRH (W) DDRE DDRI (W) (W) DDRF (W) Data direction register
----0000 00000000
00000000
--000000
00000000
Reserved
DMACS0 0-00-000 DMACC0 DMASA0 XXXXXXXX DMADA0 XXXXXXXX DMACS1 0-00-000 DMACC1 DMASA1 XXXXXXXX DMADA1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00 --0000 (R/W) XX - 0 0 0 0 0 - - - - XX - X (R/W) (R/W) XXXXXXXX (R/W) XXXXXXXX (R/W) 0 0 - - 0 0 0 0 XX - 0 0 0 0 0 - - - - XX - X (R/W) (R/W) XXXXXXXX (R/W) XXXXXXXX
Reserved
- - - - XXXX XXXX - XXX XXXXXXXX XXXXXXXX
DMA controller channel 0
- - - - XXXX XXXX - XXX XXXXXXXX XXXXXXXX
DMA controller channel 1
(Continued)
25
MB91110 Series
Address 000220H 000224H 000228H 00022CH 000230H 000234H 000238H 00023CH 000240H 000244H 000248H 00024CH 000250H 000254H 000258H 00025CH 000260H
Register +0 DMACS2 0-00-000 DMACC2 DMASA2 XXXXXXXX DMADA2 XXXXXXXX DMACS3 0-00-000 DMACC3 DMASA3 XXXXXXXX DMADA3 XXXXXXXX DMACS4 0-00-000 DMACC4 DMASA4 XXXXXXXX DMADA4 XXXXXXXX DMACR --------------00----- XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX +1 +2 (R/W) 0 0 - - 0 0 0 0 XX - 0 0 0 0 0 - - - - XX - X (R/W) (R/W) XXXXXXXX (R/W) XXXXXXXX (R/W) 0 0 - - 0 0 0 0 XX - 0 0 0 0 0 - - - - XX - X (R/W) (R/W) XXXXXXXX (R/W) XXXXXXXX (R/W) 0 0 - - 0 0 0 0 XX - 0 0 0 0 0 - - - - XX - X (R/W) (R/W) XXXXXXXX (R/W) XXXXXXXX (R/W) -------0 +3
Internal resource
- - - - XXXX XXXX - XXX XXXXXXXX XXXXXXXX
DMA controller channel 2
- - - - XXXX XXXX - XXX XXXXXXXX XXXXXXXX
DMA controller channel 3
- - - - XXXX XXXX - XXX XXXXXXXX XXXXXXXX
DMA controller channel 4
Overall DMA controller
Reserved
(Continued)
26
MB91110 Series
Address 000264H 000268H 00026CH 000270H 000274H 000278H to 0002FCH 000300H to 0003E0H 0003E4H 0003E8H 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H ICR00 ICR04
Register +0 +1 +2 +3
Internal resource
Reserved
BSD0 XXXXXXXX BSD1 XXXXXXXX BSDC XXXXXXXX BSRR XXXXXXXX (R/W) (R/W) ---11111 ---11111 XXXXXXXX (R/W) (R/W) ---11111 ICR05 ---11111 XXXXXXXX ICR02 ICR06 ---11111 (R/W) ---11111 ICR01 (R/W) XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX IRMC (W) XXXXXXXX (R/W) XXXXXXXX (W) XXXXXXXX (R) XXXXXXXX ICR03 ICR07 (R/W) (R/W) Interruption controller ---11111 ---11111 Bit search module (R/W) ICHCR (R/W)
--0 0 0 0 0 0
Instruction cache Reserved I-RAM control
-------0
(Continued)
27
MB91110 Series
Address 000408H 00040CH 000410H 000414H 000418H 00041CH 000420H 000424H 000428H 00042CH 000430H 000434H to 00047CH ICR08 ICR12 ICR16 ICR20 ICR24 ICR28 ICR32 ICR36 ICR40 ICR44 DICR
Register +0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ICR09 ICR13 ICR17 ICR21 ICR25 ICR29 ICR33 ICR37 ICR41 ICR45 HRCL ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 -------0 +1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ICR10 ICR14 ICR18 ICR22 ICR26 ICR30 ICR34 ICR38 ICR42 ICR46 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111
RSRR/WTCR (R/W)
+2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ICR11 ICR15 ICR19 ICR23 ICR27 ICR31 ICR35 ICR39 ICR43 ICR47 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111
+3 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111 ---11111
Internal resource
Interruption controller
Delay interruption
Reserved PDRR (R/W) CTBR (W) Clock control area
000480H 000484H 000488H 00048CH to 0005FCH
STCR WPR
(R/W) (W)
1 XXXX - 0 0 GCR PCTR (R/W) (R/W) 1 1 0 0 1 1-1 0 0--0---
0 0 0 1 1 1-XXXXXXXX
----0 0 0 0
XXXXXXXX
PLL control register
Reserved
(Continued)
28
MB91110 Series
(Continued)
Address 000600H 000604H 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H 00062CH 000630H to 0007F8H 0007FCH DDRB ASR1 00000000 ASR2 00000000 ASR3 00000000 ASR4 00000000 ASR5 00000000 AMD0 AMD5 (R/W) (R/W) ---00111 0--00000 EPCR0 ----1100 DMCR4 00000000 AMD1 DSCR (W) -1111111 (R/W) 0000000 LER (W) MODR (W) Register +0 (W) DDR2 DDR6 DDRA (W) 00000001 (W) 00000010 (W) 00000011 (W) 00000100 (W) 00000101 (R/W) (W) 0--00000 00000000 +1 (W) (W) (W) 00000000 00000000 -000000+2 AMR1 00000000 AMR2 00000000 AMR3 00000000 AMR4 00000000 AMR5 00000000 AMD32 (R/W) 00000000 RFCR - - XXXXXX EPCR1 -------DMCR5 00000000 AMD4 DDR8 (W) 00000000 (W) 00000000 (W) 00000000 (W) 00000000 (W) 00000000 (R/W) 0--00000 (R/W) 0---0000 (W) 11111111 (R/W) 0000000Reserved "Little endian" register Mode register External bus interface +3 (W) Data direction register Internal resource
00000000
--0--000
-----000
XXXXXXXX
Note : Do not execute RMW instructions to registers with write-only bits. RMW instruction (RMW : Read / Modify / Write) AND Rj, @Ri OR Rj, @Ri EOR ANDH Rj, @Ri ORH Rj, @Ri EORH ANDB Rj, @Ri ORB Rj, @Ri EORB BANDL #u4, @Ri BORL #u4, @Ri BEORL BANDH #u4, @Ri BORH #u4, @Ri BEORH Data in areas with " " or reserved ones is undecided.
Rj, @Ri Rj, @Ri Rj, @Ri #u4, @Ri #u4, @Ri
29
MB91110 Series
s INTERRUPTION VECTOR
Interruption factor and allocation of interruption vectors / interruption control registers are described in the interruption vector table. Interruption number Interruption vector Interruption address to TBR of Interruption source Offset Hexadecilevel *1 Decimal default *2 mal Reset System reservation System reservation System reservation System reservation System reservation System reservation Coprocessor absence trap Coprocessor error trap INTE instruction System reservation System reservation Step trace trap System reservation Exceptions to undefined instructions NMI request System reservation System reservation External interruption 0 External interruption 1 External interruption 2 External interruption 3 External interruption 4 External interruption 5 External interruption 6 External interruption 7 System reservation UART reception completion System reservation System reservation UART transmission completion System reservation 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 4 fixed 4 fixed 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H
(Continued)
30
MB91110 Series
Interruption number Interruption source System reservation DMAC0 (end, error) DMAC1 (end, error) DMAC2 (end, error) DMAC3 (end, error) DMAC4 (end, error) System reservation System reservation System reservation A/D sequential conversion type Reload timer 0 Reload timer 1 16-bit PPG timer 0 16-bit PPG timer 1 16-bit PPG timer 2 16-bit PPG timer 3 16-bit PPG timer 4 16-bit PPG timer 5 System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation Delay interruption factor bit System reservation (used under REALOS) *3 Decimal 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Hexadecimal 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40
Interruption level *1 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH
Interruption vector address to TBR of default *2 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH
(Continued)
31
MB91110 Series
(Continued)
Interruption number Interruption source System reservation (used under REALOS) *3 Used under INT instruction Decimal 65 66 to 255 Hexadecimal 41 42 to FF Interruption level *1 Offset Interruption vector address to TBR of default *2 000FFEF8H 000FFEF4H to 000FFD00H
2F8H 2F4H to 000H
*1 : ICR sets the interruption level for each interruption request using the register built into the interruption controller. ICR is prepared in accordance with each interruption request. *2 : TBR is the register that indicates the starting address of the vector table for EIT. Addresses with added offset values that are specified per TBR and EIT factor will be the vector addresses. *3 : REALOS OS/FR uses 0X40, 0X41 interruptions for system codes. Reference : The vector area for EIT is 1 KB in accordance with the address shown by TBR. The size per vector is 4 bytes, and the relationship between the vector numbers and their addresses is shown as follows. vctadr = TBR + vctofs = TBR + (3FCH - 4 x vct) vctadr : vector address vctofs : vector offset vct : vector number
32
MB91110 Series
s PERIPHERAL RESOURCES
1. I/O Port
MB91110 series can be used as the I/O port when settings for resources that handle each pin do not to use the pins for input/output. * Block diagram
Data Bus 0
Resource input
1 PDR read 0 PDR pin
Resource output
Resource output allowed DDR
1
PDR : Port Data Register DDR : Data Direction Register
* I/O Port Registers I/O port is composed of the Port Data Register (PDR) and Data Direction Register (DDR) . * In cases where the input mode is DDR = "0" For PDR reading : Level of external pins to be handled is read out. For PDR writing : Set value is written in PDR. * In cases where the output mode is DDR = "1" For PDR reading : PDR value is read out. For PDR writing : Set value is written in PDR and the PDR value is simultaneously output to the externally handled pin.
33
MB91110 Series
2. Port Data Register (PDR)
Port Data Register (PDR2-I) is the input/output data register for the I/O port. Input/output control is carried out by the handled data direction register (DDR2-I) . * Port Data Register (PDR) PDR2 Address : 000001H PDR6 Address : 000005H PDR8 Address : 00000BH PDRA Address : 000009H PDRB Address : 000008H PDRE Address : 000012H PDRF Address : 000013H PDRG Address : 000014H PDRH Address : 000015H PDRI Address : 000016H
7 P27 7 P67 7 7 7 PB7 7 7 PF7 7 7 PH7 7 PI7 6 P26 6 P66 6 6 PA6 6 PB6 6 6 PF6 6 6 PH6 6 PI6 5 P25 5 P65 5 P85 5 PA5 5 PB5 5 5 PF5 5 PG5 5 PH5 5 PI5 4 P24 4 P64 4 4 PA4 4 PB4 4 4 PF4 4 PG4 4 PH4 4 PI4 3 P23 3 P63 3 3 PA3 3 PB3 3 PE3 3 PF3 3 PG3 3 PH3 3 PI3 2 P22 2 P62 2 P82 2 PA2 2 PB2 2 PE2 2 PF2 2 PG2 2 PH2 2 PI2 1 P21 1 P61 1 P81 1 PA1 1 PB1 1 PE1 1 PF1 1 PG1 1 PH1 1 PI1 0 P20 0 P60 0 P80 0 0 PB0 0 PE0 0 PF0 0 PG0 0 PH0 0 PI0
Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value - - X- - XXXB Initial value - XXXXXX- B Initial value XXXXXXXXB Initial value - - - - XXXXB Initial value XXXXXXXXB Initial value - - XXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB
Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W
34
MB91110 Series
3. Data Direction Register (DDR)
The Data Direction Register (DDR2-I) controls the input/output direction of the I/O port per bit. 0 is used for input and 1 is used to execute output control. * Data Direction Register (DDR) DDR2 Address : 000601H DDR6 Address : 000605H DDR8 Address : 00060BH DDRA Address : 000609H DDRB Address : 000608H DDRE Address : 0000D2H DDRF Address : 0000D3H DDRG Address : 0000D4H DDRH Address : 0000D5H DDRI Address : 0000D6H
7 P27 7 P67 7 7 7 PB7 7 7 PF7 7 7 PH7 7 PI7 6 P26 6 P66 6 6 PA6 6 PB6 6 6 PF6 6 6 PH6 6 PI6 5 P25 5 P65 5 P85 5 PA5 5 PB5 5 5 PF5 5 PG5 5 PH5 5 PI5 4 P24 4 P64 4 4 PA4 4 PB4 4 4 PF4 4 PG4 4 PH4 4 PI4 3 P23 3 P63 3 3 PA3 3 PB3 3 PE3 3 PF3 3 PG3 3 PH3 3 PI3 2 P22 2 P62 2 P82 2 PA2 2 PB2 2 PE2 2 PF2 2 PG2 2 PH2 2 PI2 1 P21 1 P61 1 P81 1 PA1 1 PB1 1 PE1 1 PF1 1 PG1 1 PH1 1 PI1 0 P20 0 P60 0 P80 0 0 PB0 0 PE0 0 PF0 0 PG0 0 PH0 0 PI0
Initial value Access 00000000B W
Initial value Access 00000000B W
Initial value Access - - 0 - - 000B W
Initial value Access - 000000 -B W
Initial value Access 00000000B W
Initial value Access - - - - 0000B W
Initial value Access 00000000B W
Initial value Access - - 000000B W
Initial value Access 00000000B W
Initial value Access 00000000B W
35
MB91110 Series
4. Instruction Cache
The instruction cache is a temporary storage memory. In the event that the instruction codes are accessed from a low speed external memory, it holds the accessed codes internally, and is used to increase the access speed for all subsequent accesses. Direct read or write access can not be done by instruction cache or instruction cache tag using software. * Cacheable area of the instruction cache Instruction cache allows all space to become a cacheable area. * Even though details of the external memory are updated by DMA transfer, it is not coherent with the cache details. In this case, coherency should be established by flushing the cache. * * * * Instruction cache configuration Basic instruction length of FR series : 2 bytes Block layout : 2-way set associative type Block 1 way is configured of 32 blocks. 1 block is 16 bytes ( = 4 sub blocks) 1 sub block is 4 bytes ( = 1 bus access unit)
The instruction cache configuration is shown in the following figure. Instruction Cache Configuration
4 bytes 4 bytes I3 I2 I1 I0 4 bytes 4 bytes 4 bytes
Way 1 Cache tag 32 blocks Sub lock 3 Sub lock 2 Sub lock 1 Sub lock 0 Block 0
Cache tag
Sub lock 3
Sub lock 2
Sub lock 1
Sub lock 0
Block 31
Way 2 Cache tag Sub lock 3 Sub lock 2 Sub lock 1 Sub lock 0 Block 0
32 blocks Cache tag Sub lock 3 Sub lock 2 Sub lock 1 Sub lock 0 Block 31
36
MB91110 Series
5. Instruction Cache Control Register (ICHCR)
The Instruction Cache Control Register (ICHCR) controls the operation of the instruction cache. Writing to ICHCR may effect the cache operation of instructions to be retrieved within the next three cycles. * Instruction Cache Control Register (ICHCR) Instruction Cache Control Register (ICHCR) is shared for use by ways 1 and 2. Initial value Access - - 000000 R/W
07
06
05 GBLK
04 ALFL
03 EOLK
02 ELKR
01 FLSH
00 ENAB
Address : 0000 03E7H
Global lock Auto lock fail Entry auto lock Entry lock release Flush Enable
37
MB91110 Series
6. Clock Generator (Low power consumption mechanism)
The clock generation area is a module with the following functions. * CPU clock generation (including gear function) * Peripheral clock generation (including gear function) * Reset generation and holding factors * Standby function (including hardware standby) * Restraining DMA request * PLL (Phase Locked Loop) is built in * Register list Address 000480H 000481H 000482H 000483H 000484H 000485H 000488H
GCR PCTR 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Initial value Access
1XXXX- 00B 000111 - - B - - - - 0000B XXXXXXXXB 110011- 1B XXXXXXXXB 00 - - 0 - - - B
RSRR/WTCR PDRR
STCR CTBR WPR
R/W R/W R/W W R/W W R/W
38
MB91110 Series
* Block diagram
[ Gear control area ]
R | B U S
GCR register CPU gear CPU clock Peripheral gear PCTR register Internal clock generation circuit Selection circuit Internal bus clock External bus clock Peripheral DMA clock Internal peripheral clock
X0 X1
Oscillation circuit
PLL 1/2
Internal interruption Internal reset
[ Stop/sleep control area ]
STCR register STOP status CPU hold Permission HST pin Status transfer control circuit SLEEP status CPU hold request Reset generation F/F Internal reset
DMA request
[ DMA blocking circuit ] PDRR register
[ Reset factor circuit ] Power on cell RST pin RSRR register [ Watchdog control area ] WPP register Watchdog F/F CTBR register Time base timer Count clock
39
MB91110 Series
7. Bus Interface Outline
The bus interface controls the interface with external memory and external I/O. * Bus Interface Characteristics * 24-bit (16 MB) address output * 6 individual banks using chip selection function Random positional setting is possible on the logical address space at minimum 64-KB units. Total 16 MB x 6 areas can be set using the address pin and chip selection pin. * 16/8-bit bus width can be set per chip selection area. * Insertion of programmable "automatic memory wait" (maximum of 7 cycles) * Supports DRAM interface 3 types of DRAM interface Double CAS DRAM (Normal DRAM I/F) Single CAS DRAM Hyper DRAM 2-bank individual control (control signal i.e. RAS and CAS) DRAM can be selected from 2CAS/1WE or 1CAS/2WE. Supports high-speed page mode Supports CBR / self refresh Programmable corrugation * Unused addresses / data pins can be used as I/O ports. * Supports "little endian" mode * Using clock doubler : Internal 50 MHz, external bus 25 MHz operation * Chip Selection Area A total of six types of chip selection areas are prepared for the bus interface. The position of each area can be randomly arranged per 64 KB at least using area selection registers (ASR1 to 5) and area mask registers (AMR1 to 5) in an area of 4 GB. In the event that access to an external bus is attempted in areas that are specified by those registers, the supported chip selection signals (CS0 to CS5) become activated to "L". Such pins other than CS0 are deactivated to "H" when reset. Note : The area 0 is allocated to space outside the area specified by ASR1 to ASR5. External areas other than 0001 0000H to 0005 FFFFH are deemed area 0 on resetting.
40
MB91110 Series
* Interface The bus interface has the following interface types. * Normal bus interface * DRAM interface These interfaces can only be used in predetermined areas. The following table shows each chip selection area and the usable interface functions.Which interface is to be used is selected in the Area Mode Register (AMD) . If no selection is made, it defaults to the normal bus interface. Chip Selection Area and Selectable Bus Interfaces Selectable bus interface Normal bus Time division DRAM
Areas 0 1 2 3 4 5 * Block Diagram
Remarks On resetting
ADDRESS BUS DATA BUS 32 32
A-OUT EXTERNAL DATA BUS write buffer switch MUX
read buffer
switch
DATA BLOCK ADDRESS BLOCK
+1or+2 inpage address buffer shifter
EXTERNAL ADDRESS BUS
ASR AMR comparator
CS0 CS5
DRAM control DMCR underflow refresh counter from TBT
RAS0, RAS1 CS0L, CS1L CS0H, CS1H DW0, DW1
External pin control area Controls all blocks registers & control
RD WR0, WR1 BRQ BGRNT CLK RDY
41
MB91110 Series
* Register List
Address 00060CH 00060EH 000610H 000612H 000614H 000616H 000618H 00061AH 00061CH 00061EH 000620H 000622H 000624H 000626H 000628H 00062AH 00062CH 00062EH
31
24 23 ASR1 (Area Select Reg. 1) ASR2 (Area Select Reg. 2) ASR3 (Area Select Reg. 3) ASR4 (Area Select Reg. 4) ASR5 (Area Select Reg. 5) AMD0 *1 AMD5 *1 AMD1 *1 DSCR *2
16 15
87 AMR1 (Area Mode Reg. 1) AMR2 (Area Mode Reg. 2) AMR3 (Area Mode Reg. 3) AMR4 (Area Mode Reg. 4) AMR5 (Area Mode Reg. 5) AMD32 *1 AMD4 *1
0
Initial value 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 - - - 00111 00000000 0- - 00000 - -XXXXXX - - - - 1100 -------00000000 00000000 00000001 B 00000000 B 00000010 B 00000000 B 00000011 B 00000000 B 00000100 B 00000000 B 00000101 B 00000000 B 0- - 00000 B 0- - 00000 B 00000000 B 0- - - 0000 B - 0000000 B 11111111 B 0000000- B 0000000- B
Access W W W W W W W W W W R/W R/W R/W R/W W W R/W R/W
RFCR (Refresh Control Register) EPCR1 (External Pin Control 1) DMCR5 (DRAM Control Reg. 5)
EPCR0 (External Pin Control 0) DMCR4 (DRAM Control Reg. 4)
0007FCH
LER *3
*1 : AMD (Area MoDe register) *2 : DSCR (DRAM Signal Control Register) *3 : LER (Little Endian Register) *4 : MODR (MODe Register)
MODR *4
- - - - - - 00
XXXXXXXX B
W
42
MB91110 Series
8. 16-bit Reload Timer
The 16-bit timer is composed of a 16-bit down counter, 16-bit reload register, a pre-scalar for internal count clock preparation and a control register. Selection of the input clock can be made from three types of internal clock (machine clocks with 2, 8 and 32 cycles) and an external clock are selectable for input clock. * Characteristics of the 16-bit reload timer The Pin Output (TO) outputs a toggle waveform whenever underflow is generated in reload mode, and outputs rectangular waves indicating that it is counting in the case of one shot mode. Pin Input (TI) can be used for event input in the case of external event count mode, trigger input or gate input for internal clock mode. If the external event count function is used as the reload mode, it can be used as the cycle device for the external clock. In this type, a 2-channel timer is built-in. Channel 0 of the reload timer can start up DMA transfer using the interruption request signal. The DMA controller clears the interruption flag of the reload timer at the same time as receiving the transfer request. The TO output from channel 0 for the reload timer is connected to the A/D converter inside the LSI. Thus, A/D conversion can be started on a cycle set at the reload register.
43
MB91110 Series
* Block Diagram
16 16-bit reload register R | B U S
8
Reload RELD 16-bit down counter UF OUTE OUTL 2 GATE CSL1 Clock selector CSL0 Retrigger IN CTL. EXCK
3
16 OUT CTL. 2
INTE UF CNTE TRG IRQ
2
Port (TI) Port (TO)
2
5
21 2
Pre-scalar Clear
3 MOD2 MOD1
Internal clock
MOD0
3
* Register List * Control status register (TMCSR) Address 15 14 13
000036H
12 4 RELD
11 CSL1 3 INTE
10 CSL0 2 UF
9 MOD2 1 CNTE
8 MOD1 0 TRG
Initial value
- - - - 0000B
Access
R/W
7
6 OUTE
5 OUTL
000037H
MOD0
00000000B
R/W
* 16-bit timer register (TMR) Address 15
00002AH 000032H
0
Initial value
XXXXXXXX XXXXXXXX XXXXXXXXB XXXXXXXXB
Access
W
* 16-bit reload register (TMRLR) Address 15
000028H 000030H
0
Initial value
XXXXXXXX XXXXXXXX XXXXXXXXB XXXXXXXXB
Access
W
44
MB91110 Series
9. PPG Timer
The PPG timer can output pulses that are synchronized with soft triggers or externally. Also, the cycle and duty of the output pulses can be changed randomly by replacing the two 16-bit register values. In this type, there are 6 built-in channels with this function. * PPG timer function The PPG timer has two functions as follows. * PWM function This can be synchronized to the trigger and is programmable to output pulses while rewriting the above register values. It can also be used as a D/A converter by using an additional circuit. * One-shot function This detects the edge of the trigger input and outputs a single pulse. * Block Diagram
PCSR
PDUT
Pre-scalar /2 /8 / 32 / 128
ck 16-bit Down counter Start
Load
cmp
Borrow
PPG mask S Q
PPG output
R
Reverse bit Enable TRG input (only channels 0 to 2) Edge detection Soft trigger
Interruption selection
IRQ
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MB91110 Series
* Register List * Cycle setting register (PCSR) Address
000046H 00004EH 000056H 00005EH 000066H 00006EH
bit 15
87 0
Initial value
Access
XXXXXXXX
XXXXXXXXB
W
* Duty setting register (PDUT) Address
000048H 000050H 000058H 000060H 000068H 000070H
bit 15
87 0
Initial value
Access
XXXXXXXX
XXXXXXXXB
W
* Control/status register (PCNH/PCNL) Address
00004AH 000052H 00005AH 000062H 00006AH 000072H
bit 15
87 0
Initial value
Access
0000000 -
00000000B
R/W
46
MB91110 Series
10. External Interruption/NMI Control Area
The external interruption / NMI control area controls the external interruption requests to be input to the NMI and INT0 to INT7. "H" or "L" and "rising edge" or "falling edge" can be selected as the requested detection level (except for NMI) . Also, four requests from INT0 to INT3 can be used as the DMA request. * Block diagram
R BUS 8 Interruption permission register 9 Gate 8 Factor F/F 9 INT0 INT7 NMI
Interruption requests
Edge detection circuit
Interruption factor register
8 Request level setting register
* Register list * External interruption permission register (ENIR) Address bit 7 6 5 4 000095H
EN7 EN6 EN5 EN4
3 EN3
2 EN2
1 EN1
0 EN0
Initial value Access 00000000B R/W
* External interruption factors register (EIRR) Address bit 15 14 13 12 000094H
ER7 ER6 ER5 ER4
11 ER3
10 ER2
9 ER1
8 ER0
00000000B
R/W
* Request level setting register (ELVR) Address bit 15 14 13 000098H bit 000099H
LB7 7 LB3 LA7 6 LA3 LB6 5 LB2
12 LA6 4 LA2
11 LB5 3 LB1
10 LA5 2 LA1
9 LB4 1 LB0
8 LA4 0 LA0
00000000B
R/W
00000000B
R/W
47
MB91110 Series
11. Delay Interruption Modules
This is a module to generate interruptions to switch tasks. This module can be used with software to generate/ cancel interruption requests to the CPU. * Block diagram
WRITE Resource request ICR CMP DICR ICR ILM IL CMP
Delay interruption
Interruption controller
CPU
* Register list Address 000430H
bit 7 6 5 4 3 2 1 0 DLYI
Initial value - - - - - - - 0B
Access R/W
48
MB91110 Series
12. Interruption Controller
The interruption controller carries out interruption reception and arbitration. * Hardware configuration of the interruption controller This module is configured for the following items. * ICR register * Interruption priority judgement circuit * Interruption level, interruption number (vector) generation area * Cancellation request generation area for HOLD request * Major interruption controller functions This module has the following functions. * Detection of NMI request / interruption request * Priority grade judgement (depending on the level and number) * Transferring interruption level of factors for the judgement results (to CPU) * Transferring interruption number of factors for the judgement results (to CPU) * Recovery instruction from stop mode by generating NMI / interruption * Cancellation of HOLD request to the bus master
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MB91110 Series
* Block Diagram
INT0*2
IM
Priority grade judgement
OR NMI
NMI processing
4
5
Cancellation request for holding
LEVEL 40
LEVEL judgement
ICR00 RI00 6
Generation of LEVEL VECTOR
HLDCAN*3
VECTOR judgement
ICR47
VCT5 0
RI47 (DLYIRQ) DLYI*1
R-BUS
*1 : DLYI indicates delay interruption. (Refer to the chapter on delay interruption module for details.) *2 : INTO is the wake-up signal to the clock control area in case of sleep or stop. *3 : HLDCAN is the bus vacation request signal to bus masters other than the CPU.
50
MB91110 Series
* Register list
Address 000400H 000401H 000402H 000403H 000404H 000405H 000406H 000407H 000408H 000409H 00040AH 00040BH 00040CH 00040DH 00040EH 00040FH 000410H 000411H 000412H 000413H 000414H 000415H 000416H 000417H 000418H 000419H 00041AH 00041BH 00041CH 00041DH 00041EH 00041FH 000420H 000421H 000422H 000423H 000424H 000425H 000426H 000427H 000428H 000429H 00042AH 00042BH 00042CH 00042DH 00042EH 00042FH 000431H bit 7 6 5 4 3 2 1 0 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 HRCL Initial value - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 - - - 11111 Acces R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 ICR4 ICR3 ICR2 ICR1 ICR0 R R R/W R/W R/W R/W R/W R/W R/W R/W LVL4 LVL3 LVL2 LVL1 LVL0
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MB91110 Series
13. Interruption Control Register (ICR)
This function is set up per interruption input and sets the interruption level of interruption requests to be handled. * Register list
bit 7 6 5 4 ICR4 R 3 ICR3 R/W 2 ICR2 R/W 1 ICR1 R/W 0 ICR0 R/W
[bit 4 to 0] ICR4 to 0 The interruption level of the interruption requests that are handled is specified by the interruption level setting bit. In cases where the interruption level that is set in this register is the same as or more than the level mask value that is set (has been set) in the ILM register of the CPU, the interruption request is masked at the CPU side. It is initialized to 11111B on resetting. The settable interruption level setting bit and interruption level are shown in following Table. Interruption Level Setting Bit and Interruption Level ICR2 ICR1 ICR0 Interruption level 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (Low) Interruption is prohibited NMI Maximum settable level (High) System reservation
ICR4 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ICR3 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Note: ICR 4 is fixed as "1" and can not be written as "0".
52
MB91110 Series
14. 10-bit A/D Converter
The A/D converter is the module that converts analog input voltages to a digital value. * * * * * Characteristics of A/D Converter Minimum converting time : 5.6 s/channel Sample & hold circuit is built-in. Resolution : 10 bits Selection can be made for analog input from 8 channels. Single conversion mode : 1 channel is selected for conversion Scan conversion mode : Converts multiple number of consecutive channels. Maximum 8 channels are programmable. Consecutive conversion mode : Repeatedly converts the specified channel. Suspension / conversion mode : Suspends after converting 1 channel and waits until the next one is started up (synchronization for starting conversion is possible)
* Initiation of DMA transfer by interruption is possible. * Initiation factor can be selected from software, external trigger (falling edge) or reload timer (rising edge) . * Block Diagram
AVCC AVR AVSS
Internal voltage generator MPX AN0 AN1 Input circuit AN2 AN3 AN4 AN5 AN6 AN7 Sample & hold circuit Sequential comparison register Comparator R | B U S
Data register Decoder ADCR
A/D control register 1 ATG Starting up External trigger Starting up timer Operation clock ADCS
TIM0 (Internal connection) (Reload timer channel 0)
(Peripheral system clock)
Pre-scalar
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MB91110 Series
* Register List * Control Status Register (ADCS) bit Address
15 14 INT 13 INTE 12 PAUS 11 STS1 10 STS0 9 STRT 8
Initial value Access
00000000B R/W
00003AH
BUSY
bit
7 6 MD0 5 ANS2 4 ANS1 3 ANS0 2 ANE2 1 ANE1 0 ANE0
00003BH
MD1
00000000B
R/W
* Data Register (ADCR) bit Address
15 14 13 12 11 10 9 9 8 8
Initial value Access
000038H
- - - - - - XXB
R
bit
7 6 6 5 5 4 4 3 3 2 2 1 1 0 0
000039H
7
XXXXXXXXB
R
54
MB91110 Series
15. UART
UART is the serial I/O port for carrying out asynchronous (start-stop synchronization) or CLK synchronous communication. * * * * * * * * * Characteristics of UART FDX double buffer Asynchronous (start-stop synchronization) and CLK synchronous communication are possible. Supports multi processor mode Dedicated baud rate generator is built-in. Free baud rate can be set using an external clock. Error detection function (parity, framing, overrun) Transfer signal is NRZ code Initiation of DMA transfer is possible by interruption.
55
MB91110 Series
* Block Diagram
Control signal Dedicated baud rate generator 16-bit reload timer (internal connection) Clock selection circuit External clock Reception control circuit SI Start bit detection circuit Reception bit counter Reception parity counter Transmission control circuit Transmission starting circuit Transmission bit counter Transmission parity counter SO Reception clock Transmission clock Reception interruption (to CPU) SCK Transmission interruption (to CPU)
Reception status judgement circuit
Shifter for reception
Shifter for transmission Start transmission SODR
End of reception SIDR Reception error generation signal for DMA (to DMAC)
R - BUS
SMR register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR register
PEN P SBL CL A/D REC RXE TXE
SSR register
PE ORE FRE RDRF TDRE RIE TIE
Control signal
56
MB91110 Series
* Register List
* Serial Mode Register (SMR) Address bit 7 6 000023H
MD1 MD0
5 CS2
4 CS1
3 CS0
2
1 SCKE
0 SOE
Initial value Access 00000 - 00B R/W
* Serial Control Register (SCR) bit 15 14 000022H
PEN P
13 SBL
12 CL
11 A/D
10 REC
9 RXE
8 TXE
Initial value 00000100B
Access R/W
* Serial Input Data Register/Serial Output Data Register (SIDR/SODR) bit 7 6 5 4 3 2 1 000021H
D7 D6 D5 D4 D3 D2 D1
0 D0
Initial value XXXXXXXXB
Access R/W
* Serial Status Register (SSR) bit 15 14 000020H
PE ORE
13 FRE
12 RDRF
11 TDRE
10
9 RIE
8 TIE
Initial value Access 00001 - 00B R/W
* Communication Pre-scalar Control Register (CDCR) bit 7 6 5 4 3 000025H
MD DIV4 DIV3
2 DIV2
1 DIV1
0 DIV0
Initial value Access 0 - - 11111B R/W
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MB91110 Series
16. DMA Controller (DMAC)
The DMA controller is the module to realize Direct Memory Access (DMA) transfers with FR 30 series devices. DMA transfers controlled by this module enable quick and direct transfer of all data without using the CPU and thus system performance is increased. * Hardware Configuration of DMA Controller This module is mainly configured of the following items. * Internal I/O access control circuit * 32-bit address counters (possible reload specification : 10) * 16-bit transfer number counters (possible reload specification : 5) * External transfer request input pin : DREQ0, DREQ1, DREQ2 * External transfer request reception output pin : DACK0, DACK1, DACK2 (external bus synchronization) * External transfer termination output pin : DEOP0, DEOP1, DEOP2 (external bus synchronization) * Major Function of DMA Controller There are the following functions for data transfer using this module. * Independent data transfer of a number of channels is possible (5 ch) * Priority ranking amongst channels Fixed ranking (ch.0 > ch.1 > ch.2 > ch.3 > ch.4) Ranking between channel 0 and 1 can be reversed. * Transfer request Dedicated external pin input (Edge detection / level detection selection are possible for channels 0 to 2 only.) Built-in peripheral request (interruption requests are shared. External interruption is included.) Software request (register writing) * Transfer sequence Consecutive / burst transfer Step transfer / block transfer (Maximum 16 words are settable.) * Addressing mode : 32-bit full address specification (increase / decrease / fix) * Data types : Byte, half word, word length * Single shot or reload can be selected.
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MB91110 Series
* Block Diagram
DREQ0 DREQ1 DREQ2 Peripheral interruption request Peripheral interruption request External transfer request input Detection / processing External transfer request Transfer request processing Each channel request Controls arbitration of requests, priority judgement and decision on transferring channels Transfer start request Hold control Hold request DACK0 DACK1 DACK2 DEOP0 DEOP1 DEOP2 Control counting address / the number of times Counter of the number of transfer times Interruption control Data control Channel instruction External input setting Each channel request setting Each channel transfer mode setting Input setting register Request setting register Mode setting register Address control register Each channel address generation control
Address counter Address Address registers
End
No. of times
Transfer state machine (bus control)
No. of times registers D-BUS
ACK.
Data buffer
FR30 CPU
59
MB91110 Series
* Register List Address
000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H 00022CH 000230H 000234H 000238H 00023CH 000240H 000244H 000248H 00024CH 000250H
bit 31
ch.0 Control/status register ch.0 Addressing/transfer counting register ch.0 Transfer originator address register ch.0 Destination address register ch.1 Control/status register ch.1 Addressing/transfer counting register ch.1 Transfer originator address register ch.1 Destination address register ch.2 Control/status register ch.2 Addressing/transfer counting register ch.2 Transfer originator address register ch.2 Destination address register ch.3 Control/status register ch.3 Addressing/transfer counting register ch.3 Transfer originator address register ch.3 Destination address register ch.4 Control/status register ch.4 Addressing/transfer counting register ch.4 Transfer originator address register ch.4 Destination address register DMACS0
0
Initial value
0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0B XX - 0 0 0 0 0 - - - - XX - XB - - - - XXXX XXXX - XXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB 0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0B XX - 0 0 0 0 0 - - - - XX - XB - - - - XXXX XXXX - XXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB 0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0B XX - 0 0 0 0 0 - - - - XX - XB - - - - XXXX XXXX - XXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB 0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0B XX - 0 0 0 0 0 - - - - XX - XB - - - - XXXX XXXX - XXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB 0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0B XX - 0 0 0 0 0 - - - - XX - XB - - - - XXXX XXXX - XXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB - - - - - - - - - - - - - - - -B 0 0 - - - - - - - - - - - - - 0B
Access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMACC0 DMASA0 DMADA0 DMACS1 DMACC1 DMASA1 DMADA1 DMACS2 DMACC2 DMASA2 DMADA2 DMACS3 DMACC3 DMASA3 DMADA3 DMACS4 DMACC4 DMASA4 DMADA4 DMACR
Overall control register
*: Shaded areas indicate where nothing exists.
60
MB91110 Series
17. Bit Search Module
Bit search module searches for 0, 1 or change points on data that has been written in the input register, and returns the detected bit position. * Block Diagram
D-BUS Input latch
Address decoder
Detection mode
Changing to 1 detection data
Bit search circuit
Detection results
* Registers List Address
0003F0H 0003F4H 0003F8H 0003FCH 31 0
Initial value
XXXXXXXX XXXXXXXB XXXXXXXX XXXXXXXB XXXXXXXX XXXXXXXB XXXXXXXX XXXXXXXB XXXXXXXX XXXXXXXB XXXXXXXX XXXXXXXB XXXXXXXX XXXXXXXB XXXXXXXX XXXXXXXB
Access
W R/W W R
Data register for 0 detection(BSD0) Data register for 1 detection(BSD1) Data Register for Change Point Detection(BSDC) Detection Results Register(BSRR)
18. I-RAM
This type has 16 KB of built-in I-RAM. Efficient processing becomes possible by pre-arranging interruption processing programs and such like in this area. Writing on I-RAM is possible via the data bus and is available as RAM for data. * Register List IRMC Address : 0003EFH
7 6 5 4 3 2 1 0 IRMD
Initial value Access -------0 R/W
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MB91110 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating Min VCC3 - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 0 -55 Max VSS + 6.0 VSS + 3.6 VSS + 3.6 VSS + 3.6 VCC5 + 0.3 AVCC + 0.3 VCC5 + 0.3 10 4 100 50 -10 -4 -50 -20 650 +70 +150 (VSS = AVSS = AVRL = 0 V) Symbol VCC5 VCC3 AVCC AVRH, AVRL VI VIA VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg Unit V V V V V V V mA mA mA mA mA mA mA mA mW C C *5 *5 *3 *4 *3 *4 Remarks *1 *1 *2 *2
Parameter Power voltage Analog power voltage Standard analog voltage Input voltage Analog pin input voltage Output voltage Maximum "L" level output current Average "L" level output current Maximum total "L" level output current Average "L" level total output current Maximum "H" level output current Average "H" level output current Maximum total "H" level output current Average "H" level total output current Electricity consumption Operating temperature Storage temperature
*1 : VCC3/VCC5 must not be lower than VSS - 0.3 V. *2 : Care must be taken that AVCC, AVRH and AVRL do not exceed VCC + 0.3 V when the power is turned on. Also care must be taken that AVRH and AVRL do not exceed AVCC, and keep AVRH AVRL. *3 : Peak value of the pin concerned is regulated as the maximum output current. *4 : Average current within 100 ms flowing in the pin concerned is regulated as the average output current. *5 : Average current within 100 ms flowing in all pins concerned is regulated as the average total output current. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB91110 Series
2. Recommended Operating Conditions
Value Min 4.5 3.135 VSS - 3.0 AVSS 0 Max 5.5 3.465 VSS + 3.465 AVCC +70 V V V C
(VSS = AVSS = AVRL = 0 V) Unit Remarks Keeping RAM status in the case of normal operations / stopping
Parameter
Symbol VCC5
Power voltage Analog power voltage Standard analog voltage Operating temperature
VCC3 AVCC AVRH TA
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB91110 Series
3. DC Characteristics
Sym bol VIH
(VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Conditions VCC5 = 4.5 V IOH = -4.0 mA VCC5 = 4.5 V IOL = 4.0 mA VCC5 = 5.5 V 0.45 V < VI < VCC5 VCC5 = 5.5 V VI = 0.45 V fC = 12.5 MHz VCC5 = 5.5 V VCC3 = 3.465 V fC = 12.5 MHz VCC5 = 5.5 V VCC3 = 3.465 V TA = 25 C VCC5 = 5.5 V VCC3 = 3.465 V Value Min 0.65 x VCC3 0.8 x VCC3 VSS - 0.3 VSS - 0.3 VCC5 - 0.5 Typ Max VCC5 + 0.3 VCC5 + 0.3 0.25 x VCC3 0.2 x VCC3 0.4 Unit V V V V V V Hysteresis input Hysteresis input Remarks
Parameter
Pin name Input excluding following
"H" level input voltage
VIHS Refer to * VIL Input excluding following
"L" level input voltage "H" level output voltage "L" level output voltage Input leak current (Hi-Z output leak current) Pull-up resistance value
VILS Refer to * VOH VOL
ILI
-5
+5
A
RPULL
RST VCC5
25
50 50 100 20 50 10 200 10
200 70 150 30 70 20 900
k mA mA mA mA A A pF (4 times) in case of 50 MHz operation In case of sleeping In case of stopping
ICC
VCC3 VCC5
Power current
ICCS
VCC3 VCC5
ICCH
VCC3 Other than VCC, AVCC, AVSS and VSS
Input capacity
CIN
* : Hysteresis input pins : RST, HST, NMI, PE0/ATG, PE1/TRG0, 3, PE2/TRG1, 4, PE3/TRG2, 5, PF0/INT0 to PF7/INT7, PG0/DREQ0, PG3/DREQ1, PH0/DREQ2, PH3/SI, PH5/SCK, PH6/TI0, PI0/TI1, BGRNT/P81, WR1/P85, CS1/PA0 to CLK/PA6, RAS0/PB0 to DW1/PB7
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MB91110 Series
4. AC Characteristics
Measurement Conditions The following conditions are applied to items without particular specifications. * Alternating current standard measurement condition VCC5 : 5.0 V 10%
Input Output VIH VIL VOH VOL
* Load condition
Output pin C = 50 pF
VCC5
0V
VIH VIL
2.4 V 0.8 V
VOH VOL
2.4 V 0.8 V
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MB91110 Series
(1) Clock Timing
(VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Symbol fC tC fC fC tC PWH PWL PWH Pin Conditions Name X0 X1 X0 X1 X0 X1 X0 X1 X0 X1 X0 X1 X0 X0 X1 Value Min 10.0 80 10 10 40 10 25 0.625*1 0.625*1 0.625*1 20 40* 40
2
Parameter Clock frequency (1) Clock cycle time Clock frequency (2) Clock frequency (3) Clock cycle time
Max 12.5 100 25 25 100 8 50 25*2 25 1600* 1600*
1 1
Unit MHz ns MHz MHz ns ns ns ns
Remarks Self oscillation 12.5 MHz Internal 50 MHz operation (via PLL, 4 times) Self oscillation (1/2 cycle input) External clock (1/2 cycle input)
Input clock pulse width
Clock is input to X0/X1 Clock is input to X0 only (tCR + tCF) CPU system
Input clock rising/falling time Internal operation clock frequency
tCR tCF fCP fCPB fCPP tCP
MHz Bus system Peripheral system CPU system ns Bus system Peripheral system
Internal operation clock cycle time
tCPB tCPP
1600*1
*1 : This is the value when 10 MHz, which is the minimum value of the clock frequency, is input to X0 and 1/2 cycle of the oscillation circuit and gearing of 1/8 are used. *2 : This is the value when doubler is used with a 50 MHz CPU.
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MB91110 Series
* Clock timing standard measurement conditions
tC 0.8 VCC5 0.2 VCC5 PWH tCF PWL tCR
* Guaranteed operating area
5.5 VCC5 Power voltage 4.5
Guaranteed operating area (TA = 0 +70 C) fCPP is the shaded area.
3.465 VCC3 3.135 fCP / fCPP (MHz)
0 0.625
25 Internal clock
50
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MB91110 Series
* External/internal clock settable area
fCP / fCPP (MHz) fCP 50 CPU 40
Internal clock settable limit
PLL system
(12.5 MHz / 4 times)
fCPP 25 20 12.5 5 0 0 10 12.5 25 fC (MHz)
Peripheral
1/2 cycle system
External clock
Original oscillation input clock
self oscillation Notes: * 10.0 MHz to 12.5 MHz must be input for external clock input when PLL is used. * PLL oscillation stabilization time should be larger than 100 s. * Internal clock gear should be set within the above range.
68
MB91110 Series
(2) Clock Output Timing
(VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Symbol Pin Name Conditions Value Min tCP Max ns ns ns Unit *1 In case of using doubler *2 *3 Remarks
Parameter
Cycle time CLK CLK CLK CLK
tCYC tCHCL tCLCH
CLK CLK CLK
2 x tCP
1 / 2 x tCYC - 10 1 / 2 x tCYC + 10 1 / 2 x tCYC - 10 1 / 2 x tCYC + 10
tCYC tCHCL tCLCH VOH VOL
CLK
VOH
*1 : tCYC is frequency of 1 clock cycle including the gear cycle. *2 : This standard value is in the case where the gear cycle is 1. If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing n with 1/2, 1/4 or 1/8. * Minimum : (1 - n / 2) x tCYC - 10 * Maximum : (1 - n / 2) x tCYC + 10 Gear cycle of 1 should be taken when using a doubler. *3 : This standard value is in the case where the gear cycle is 1. If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing n with 1/2, 1/4 or 1/8. * Minimum : n / 2 x tCYC - 10 * Maximum : n / 2 x tCYC + 10 Gear cycle of 1 should be taken when using a doubler.
69
MB91110 Series
The relationship between the CLK pin set using CHC/CCK1/CCK0 bit of the "Gear Control Register" (GCR) and original oscillation input is as follows. However, original oscillation input indicates "X0 input clock" in this figure. (When using doubler) * PLL system (CHC bit of GCR : "0"setting)
Original oscillation input
tCYC
(a) Gear x 1 CLK pin
CCK1/0 : "00" SLCT1, 0 : 01
or
CCK1, 0 : 01 SLCT1, 0 : 1X
* 2 cycles system (CHC bit of GCR : "1"setting)
Original oscillation input
tCYC
(a) Gear x 1 CLK pin CCK1/0: "00"
tCYC
(b) Gear x 1/2 CLK pins CCK1/0: "01"
tCYC
(c) Gear x 1/4 CLK pins CCK1/0: "10"
tCYC
(d) Gear x 1/8 CLK pins CCK1/0: "11"
70
MB91110 Series
(3) Reset / Hardware Standby Input (VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Parameter Reset input time Hardware standby input time Symbol tRSTL tHSTL Pin Name RST HST Conditions Value Min tCP x 5 tCP x 5 Max Unit ns ns Remarks
tRSTL, tHSTL
RST HST
0.2 VCC5
71
MB91110 Series
(4) Power On Reset
(VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Symbol Pin Name Conditions VCC5 = 5 V Value Min Max 30 18 ms Unit Remarks VCC is less than 0.2 V before power is turned on. Repeated operation
Parameter
Power startup time
tR
VCC5
VCC3 = 3.3 V
Power cut time
tOFF
VCC3
1
ms
tR 0.9 x VCC3 0.2 VCC3
VCC3
tOFF * Other Points to Note (1) Sudden changes in the power supply voltage may cause a power-on reset .To change the power supply voltage while the device is in operation, it is recommended to rise the voltage smoothly to suppress fluctuations as shown below.
VCC3
It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
VSS
(2) When power is turned on, it must be started while the RST pin is set to "L" level, after which wait for tRSTL and change the level to "H" once the Vcc power level is reached.
VCC5 VCC3
VCC3 / AVCC / AVRH should be supplied after supplying VCC5. AVCC / AVRH should be supplied at the same time after supplying VCC3.
RST
tRSTL
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MB91110 Series
(5) Normal Bus Access Read/Write Operation (VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Parameter CS0 to CS5 delay time CS0 to CS5 delay time Address delay time Data delay time (write) RD delay time RD delay time WR0 to WR1 delay time WR0 to WR1 delay time Valid address Valid data input time RD Valid data input time Data setup RD time RD Data holding time Symbol tCHCSL tCHCSH tCHAV tCHDV tCLRL tCLRH tCLWL tCLWH tAVDV tRLDV Read tDSRH tRHDX RD D31 to D16 Pin Name CLK CS0 to CS5 CLK A23 to A00 CLK D31 to D16 CLK RD CLK WR0 to WR1 A23 to A00 D31 to D16 Conditions Value Min 25 0 Max 15 15 15 15 10 10 10 10 3 / 2 x tCYC - 40 tCYC - 25 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 *1
*1 : Time (tCYC x number of cycles extended) needs to be added to this standard if the bus is extended by automatic waiting insertion and RDY input. *2 : Values of this standard are in case of gear cycle x 1. If the gear cycle is set to 1/2, 1/4 or 1/8, calculations should be made using the following formula and replacing n with 1/2, 1/4 or 1/8. * Calculation formula : (2 - n / 2) x tCYC - 40
73
MB91110 Series
tCYC BA1 BA2 2.4 V 0.8 V 0.8 V 2.4 V 0.8 V
CLK
2.4 V
tCHCSL
tCHCSH 2.4 V
CS0 to CS5
0.8 V
tCHAV
A23 to A00
2.4 V 0.8 V
2.4 V 0.8 V
tCLRL
tCLRH 2.4 V
RD
0.8 V tRLDV
tRHDX tAVDV 2.4 V 0.8 V 2.4 V 0.8 V tDSRH tCLWL
D31 to D16
Read
WR0 to WR1
0.8 V
2.4 V tCLWH
tCHDV
D31 to D16
2.4 V 0.8 V
Write
2.4 V 0.8 V
74
MB91110 Series
(6) Ready Input Timing
(VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Symbol tRDYS tRDYH Pin Name Conditions RDY CLK RDY CLK Value Min 20 0 ns Max Unit ns Remarks
Parameter RDY setup time CLK CLK RDY holding time
tCYC
CLK
2.4 V
0.8 V
2.4 V tRDYH
0.8 V tRDYH
tRDYS
tRDYS 2.4 V
RDY (If "wait" is executed)
0.8 V
RDY (If "wait" is not executed)
2.4 V
0.8 V
75
MB91110 Series
(7) Holding timing
(VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Symbol tCHBGL tCHBGH tXHAL BGRNT tHAHV tCYC - 10 tCYC + 10 ns Pin Name CLK BGRNT Conditions Value Min tCYC - 10 Max 10 10 tCYC + 10 Unit ns ns ns Remarks
Parameter BGRNT delay time BGRNT delay time Pin floating BGRNT time BGRNT Pin valid time
Note : It takes at least one cycle from loading the BRQ to when BGRNT is changed.
tCYC
CLK
2.4 V
2.4 V
2.4 V
2.4 V
BRQ
tCHBGL
tCHBGH 2.4 V
BGRNT
tXHAL
0.8 V
tHAHV
Each pin
High impedance
76
MB91110 Series
(8) Read/Write Cycle of the Normal DRAM Mode (VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Parameter RAS delay time RAS delay time CAS delay time CAS delay time ROW address delay time COLUMN address delay time DW delay time DW delay time Output data delay time RAS valid data input time CAS valid data input time CAS data holding time Symbol tCLRAH tCHRAL tCLCASL tCLCASH tCHRAV tCHCAV tCHDWL tCHDWH tCHDV1 tRLDV tCLDV tCADH Pin Name CLK RAS CLK CAS CLK A23 to A00 CLK DW CLK D31 to D16 RAS D31 to D16 CAS D31 to D16 Conditions Value Min 0 Max 10 10 10 10 15 15 15 15 15 5/2x tCYC - 20 tCYC - 17 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 *1
*1 : If either the Q1 or A4 cycle is extended for one cycle, the tCYC time needs to be added to this standard. *2 : Values of this standard are in case of gear cycle x 1. If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing n with 1/2, 1/4 or 1/8. * Calculation formula : (3 - n / 2) x tCYC - 20
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MB91110 Series
tCYC Q1 2.4 V 0.8 V Q2 Q3 2.4 V 0.8 V 0.8 V Q4 Q5 2.4 V
CLK
RAS
tCLRAH
2.4 V
0.8 V tCHRAL tCLCASL tCLCASH 2.4 V
CAS
0.8 V
tCHRAV
tCHCAV 2.4 V 0.8 V 2.4 V 2.4 V COLUMN address 0.8 V 0.8 V tRLDV tCLDV tCADH Read 2.4 V 0.8 V
A23 to A00
2.4 V 0.8 V
ROW address
D31 to D16
2.4 V 0.8 V
DW
2.4 V 0.8 V tCHDWL tCHDWH
D31 to D16
2.4 V 0.8 V tCHDV1
Write
2.4 V 0.8 V
78
MB91110 Series
(9) High Speed Page Read/Write Cycle of the Normal DRAM Mode (VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Parameter RAS delay time CAS delay time CAS delay time COLUMN address delay time DW delay time Output data delay time CAS valid data input time CAS data holding time Symbol tCLRAH tCLCASL tCLCASH tCHCAV tCHDWH tCHDV1 tCLDV tCADH Pin Name CLK, RAS CLK CAS CLK A23 to A00 CLK, DW CLK D31 to D16 CAS D31 to D16 Conditions Value Min 0 Max 10 10 10 15 15 15 tCYC - 17 Unit ns ns ns ns ns ns ns ns * Remarks
* : When Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
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MB91110 Series
Q5
Q4 2.4 V 0.8 V
Q5 0.8 V
Q4
Q5 2.4 V 0.8 V
CLK
tCLRAH
RAS
2.4 V
tCLCASL
tCLCASH 2.4 V
CAS
0.8 V
tCHCAV
A23 to A00
COLUMN address
2.4 V 0.8 V
COLUMN address
2.4 V 0.8 V
COLUMN address
tCLDV 2.4 V 0.8 V
tCADH 2.4 V 0.8 V
D31 to D16
Read
Read
Read
tCHDWH
DW
2.4 V
tCHDV1
D31 to D16
2.4 V 0.8 V
Write
2.4 V 0.8 V
2.4 V 0.8 V
Write
80
MB91110 Series
(10) Single DRAM Timing
(VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Symbol tCLRAH2 tCHRAL2 tCHCASL2 tCHCASH2 tCHRAV2 tCHCAV2 tCHDWL2 tCHDWH2 tCHDV2 tCLDV2 tCADH2 Pin Name CLK RAS CLK CAS CLK A23 to A00 CLK DW CLK D31 to D16 CAS D31 to D16 Conditions Value Min 0 Max 10 10 n / 2 x tCYC +8 10 15 15 15 15 15 (1 - n / 2) x tCYC - 17 Unit ns ns ns ns ns ns ns ns ns ns ns Remarks
Parameter RAS delay time RAS delay time CAS delay time CAS delay time ROW address delay time COLUMN address delay time DW delay time DW delay time Output data delay time CAS valid data input time CAS data holding time
81
MB91110 Series
tCYC Q1 Q2 2.4 V 2.4 V Q3 2.4 V 2.4 V
*1
Q4S 2.4 V Q4S Q4S 2.4 V
CLK
0.8 V
RAS
2.4 V tCLRAH2
0.8 V tCHRAL2 tCHCASL2
tCHCASH2
CAS
2.4 V 0.8 V
2.4 V
2.4 V
A23 to A00
2.4 V 0.8 V
ROW address
2.4 V 0.8 V
COLUMN-0 0.8 V tCHCAV2
COLUMN-1
COLUMN-2 tCADH2
tCHRAV2
tCLDV2
D31 to D16 (Read)
Read-0
2.4 V 0.8 V Read-1
2.4 V 0.8 V
Read-2
DW (Write)
0.8 V tCHDWL2 tCHDWH2
2.4 V
*2
D31 to D16 (Write)
2.4 V 0.8 V tCHDV2
2.4 V 2.4 V 0.8 V
2.4 V
Write-0
2.4 V 0.8 V tCHDV2
Write-1
0.8 V 0.8 V
Write-2
*1 : Q4S cycle indicates the Q4SR (read) or Q4SW (write) cycle of the Single DRAM cycle. *2 : indicates when a bus cycle is started from the high-speed page mode.
82
MB91110 Series
(11) Hyper DRAM Timing
(VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Symbol tCLRAH3 tCHRAL3 tCHCASL3 tCHCASH3 tCHRAV3 tCHCAV3 tCHRL3 tCHRH3 tCLRL3 tCHDWL3 tCHDWH3 tCHDV3 tCLDV3 tCADH3 CLK DW CLK D31 to D16 CAS D31 to D16 CLK RD Pin Name CLK RAS CLK CAS CLK A23 to A00 Conditions Value Min 0 Max 10 10 n / 2 x tCYC +8 10 15 15 15 15 15 15 15 15 tCYC - 20 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter RAS delay time RAS delay time CAS delay time CAS delay time ROW address delay time COLUMN address delay time RD delay time RD delay time RD delay time DW delay time DW delay time Output data delay time CAS valid data input time CAS data holding time
83
MB91110 Series
tCYC Q1 Q2 2.4 V Q3 2.4 V 2.4 V
*1
Q4H 0.8 V 2.4 V Q4H Q4H 2.4 V
CLK
0.8 V
RAS
2.4 V tCLRAH3
0.8 V tCHRAL3 tCHCASL3
tCHCASH3
CAS
0.8 V
2.4 V 0.8 V
0.8 V
2.4 V
A23 to A00
2.4 V ROW address 2.4 V 0.8 V 0.8 V tCHRAV3 tCHCAV3
COLUMN-0 0.8 V
COLUMN-1
COLUMN-2
*2
RD (Read)
0.8 V tCHRL3 0.8 V tCLRL3 tCLDV3 2.4 V Read-0 0.8 V tCHRH3
2.4 V
tCADV3
D31 to D16 (Read)
Read-1
2.4 V 0.8 V
DW (Write)
0.8 V tCHDWL3 tCHDWH3
2.4 V
*2
D31 to D16 (Write)
2.4 V 0.8 V tCHDV3
2.4 V 2.4 V 0.8 V
2.4 V
Write-0
2.4 V 0.8 V tCHDV3
Write-1
0.8 V 0.8 V
Write-2
*1 : Q4H cycle indicates the Q4HR (read) or Q4HW (write) cycle of the Hyper DRAM cycle. *2 : indicates when a bus cycle is started from the high-speed page mode.
84
MB91110 Series
(12) CBR Refresh
(VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Symbol tCLRAH tCHRAL tCLCASL tCLCASH Pin Name CLK RAS CLK CAS Conditions Value Min Max 10 10 10 10 Unit ns ns ns ns Remarks
Parameter RAS delay time RAS delay time CAS delay time CAS delay time
tCYC R1
R2 2.4 V 0.8 V
R3
R4 0.8 V
CLK
2.4 V 0.8 V
RAS
2.4 V tCLRAH
0.8 V tCHRAL
CAS
0.8 V tCLCASL
2.4 V tCLCASH
DW
85
MB91110 Series
(13) Self Refresh
(VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Symbol tCLRAH tCHRAL tCLCASL tCLCASH Pin Name CLK RAS CLK CAS Conditions Value Min Max 10 10 10 10 Unit ns ns ns ns Remarks
Parameter RAS delay time RAS delay time CAS delay time CAS delay time
tCYC SR1
SR2 2.4 V 0.8 V 2.4 V
SR3
SR3 0.8 V tCLRAH 2.4 V
CLK
2.4 V
tCHRAL
RAS
0.8 V
CAS
0.8 V tCHCASL tCLCASH
2.4 V
86
MB91110 Series
(14) UART Timing
(VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Symbol Pin Name tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX External shift clock mode Internal shift clock mode Conditions Value Min 8 tCYCP -80 100 60 4 tCYCP 4 tCYCP 60 60 Max 80 150 Unit ns ns ns ns ns ns ns ns ns Remarks
Parameter Serial clock cycle time SCLK SOUT Delay time Valid SIN SCLK SCLK Valid SIN holding lock Serial clock "H" pulse width Serial clock "L" pulse width SCLK SOUT Delay time Valid SIN SCLK SCLK Valid SIN holding lock
Notes : * This is the AC standard in the case of CLK synchronous mode. * tCYCP is the cycle time of the peripheral system clock.
87
MB91110 Series
* Internal shift clock mode
tSCYC
SCLK
VOL tSLOV VOH
VOH VOL
SOUT
VOL tIVSH VIH VIL tSHIX VIH VIL
SIN
* External shift clock mode
tSLSH tSHSL VIH VIL tSLOV VOH VIL VIH
SCLK
SOUT
VOL tIVSH VIH VIL tSHIX VIH VIL
SIN
88
MB91110 Series
(15) Trigger System Input Timing (VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Parameter A/D initiation trigger input time PPG initiation trigger input time tTRG SymPin Name bol ATG TRG0 to TRG5 5 tCYCP Conditions Value Min Max Unit ns ns Remarks
Note : tCYCP is the cycle time of the peripheral system clock.
tTRG
ATG TRG0 to TRG5
VIL VIL
89
MB91110 Series
(16) DMA Controller Timing (VCC5 = 5 V 10%, VCC3 = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Parameter DREQ input pulse width DACK delay time (Normal bus) (Normal DRAM) EOP delay time (Normal bus) (Normal DRAM) DACK delay time (Single DRAM) (Hyper DRAM) EOP delay time (Single DRAM) (Hyper DRAM) Symbol Pin Name Conditions Value Min 2 tCYC Max 6 6 6 6 n / 2 x tCYC 6 n / 2 x tCYC 6 Unit ns ns ns ns ns ns ns ns ns Remarks
tDRWH DREQ0 to DREQ2 tCLDL tCLDH tCLEL tCLEH tCHDL tCHDH tCHEL tCHEH CLK DACK0 to DACK2 CLK DEOP0 to DEOP2 CLK DACK0 to DACK2 CLK DEOP0 to DEOP2
tCYC
CLK
2.4 V 0.8 V
2.4 V 0.8 V
DACK0 to DACK2 DEOP0 to DEOP2
tCLDL tCLEL 0.8 V
tCLDH tCLEH 2.4 V
DACK0 to DACK2 DEOP0 to DEOP2 (Single DRAM) (Hyper DRAM)
tCHDL tCHEL
0.8 V
2.4 V
tCHDH
tDRWH
DREQ0 to DREQ2
2.4 V
2.4 V
90
MB91110 Series
5. A/D Converter Electrical Characteristics
Symbol VOT VFST IAIN VAIN IA IAH IR IRH
(VCC5 = 5 V 10%, VCC3 = AVCC = AVRH = 3.3 V 5%, VSS = AVSS = AVRL = 0 V, TA = 0 C to +70 C) Pin Name AN0 to AN7 AN0 to AN7 AN0 to AN7 AN0 to AN7 AVRH AVCC AVRH AN0 to AN7 Value Min -1.5 AVRH - 4.5 5.6* AVSS AVSS
1
Parameter Resolution Conversion error Linearity error Differential linearity error Zero transition error Full-scale transition error Conversion time Analog port input current Analog input voltage Standard voltage Power supply current Standard voltage current supplied Tolerance between channels
Typ 10 +0.5 AVRH - 1.5 0.1 4 110
Max 10 3.0 2.5 1.9 +2.5 AVRH + 0.5 10 AVRH AVCC 5*2 5* 4
2
Unit BIT LSB LSB LSB LSB LSB s A V V mA A A A LSB
*1 : In case of VCC3 = AVCC = 3.3 V 5%, machine clock 25 MHz *2 : This is the current in the case that the A/D converter is not activated and the CPU is stopped (in case of VCC3 = AVCC = AVRH = 3.465 V) Notes : * As the AVRH becomes smaller, the tolerance becomes relatively larger. * Output impedance of external circuits other than analog input must be used under the following condition. Output impedance of external circuits < 7 k If the output impedance of the external circuits is too high, the sampling time for the analog voltage may be insufficient.
Analog input
Sample holding circuit C0 Comparator RON1 RON2 RON3 RON4 C1
RON1 : 5 k RON2 : 620 RON3 : 620 RON4 : 620 C0 : 2 pF C1 : 2 pF
Note : Figures described above should be considered as standard. 91
MB91110 Series
Definition of A/D Converter Terms * Resolution Analog changes that can be identified by A/D converter * Linearity error Difference between the straight line linking the zero transition point (00 0000 0000 00 0000 0001) to the full-scale transition point (11 1111 1110 11 1111 1111) and actual conversion characteristics. * Differential linearity error Difference compared to the ideal input voltage value required to change the output code 1LSB
[Linearity error]
3FF 3FE {1 LSB x (N - 1) + VOT} 3FD VFST (Actual measured value) 004 003 002 Ideal characteristics 001 VOT (Actual measured value) AVRL Analog input AVRH N-2 VNT (Actual measured value) Actual conversion characteristics N Actual conversion characteristics N+1
[Differential linearity error]
Ideal characteristics
Actual conversion characteristics
Digital output
Digital output
N-1
V(N + 1)T (Actual measured value) VNT (Actual measured value) Actual conversion characteristics AVRH
AVRL
Analog input
Linearity error of digital output N Differential linearity error of digital output N 1 LSB = VFST - VOT 1022 [V] [V]
= =
VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N + 1) T - VNT 1 LSB -1
[LSB] [LSB]
1 LSB (Ideal value) =
AVRH - AVRL 1024
VOT : Voltage with digital output transferred from (000) H to (001) H VFST : Voltage with digital output transferred from (3FE) H to (3FF) H VNT : Voltage with digital output transferred from (N - 1) H to N
92
MB91110 Series
* Total error This indicates the difference between the actual and theoretical values and includes zero transition, full-scale transition and linearity error.
[Total error]
3FF 1.5 LSB 3FE 3FD {1 LSB x (N - 1) + 0.5 LSB} Digital output Actual conversion characteristics
004 003 002 001 0.5 LSB AVRL Analog input AVRH VNT (Actual measured value) Actual conversion characteristics Ideal characteristics
Total tolerance of digital output N =
VNT - {1 LSB x (N - 1) + 0.5 LSB} [LSB] 1 LSB VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH - 1.5 LSB [V] VNT : Voltage with digital output transferred from (N - 1) H to N
93
MB91110 Series
s EXAMPLE CHARACTERISTICS
VOL
300 250 VOL [mV] 200 VOH [V] 150 100 50 0 3 4 4.5 5 5.5 VCC [V] 6 7 IOL = 4.0 mA, TA = 25 C 6 5.5 5 4.5 4 3.5 3 3 4 4.5 5 5.5 VCC [V] 6 7
VOH
IOH = - 4.0 mA, TA = 25 C
ICC3
100
ICC3
100 90 80 70 60 50 40 30 20 10 0
f = 50.0 MHz, TA = 25 C
VCC = 3.3 V, TA = 25 C
ICC3 [mA]
50
0
3 VCC [V]
3.5
ICC3 [mV]
1
10 Frequency [MHz]
100
ICC5
40 35 30
ICC5
40 35 30
f = 25.0 MHz, TA = 25 C
VCC = 5.0 V, TA = 25 C
ICC5 [mA]
25 20 15 10 5 0 3.5 4 4.5 5 5.5 6 6.5
ICC5 [mA]
25 20 15 10 5 0
1
VCC [V]
10 Frequency [MHz]
100
Pull-up resistance
125 100 75 50 25 0 4 5 6
TA = 25 C
Resistor value (k)
VCC [V]
94
MB91110 Series
MB91110 Linearity error
VCC = 3.0 V, AVCC = 3.0 V, TA = 25C
3 2
Linearity error [LSB]
1 0 -1 -2 -3 00 1FF
CODE
MB91110 Differential linearity error
Differential Linearity error [LSB]
3 2 1 0 -1 -2 -3 00 1FF
VCC = 3.0 V, AVCC = 3.0 V, TA = 25C
CODE
MB91110 Total error
VCC = 3.0 V, AVCC = 3.0 V, TA = 25C
3
Total error [LSB]
2 1 0 -1 -2 -3 00 1FF
CODE
95
MB91110 Series
s ORDERING INFORMATION
Part number MB91110PMT2 MB91V110CR Package 144-pin plastic LQFP (FPT-144P-M08) PGA-299C-A01 Remarks
96
MB91110 Series
s PACKAGE DIMENSION
144-pin plastic LQFP (FPT-144P-M08)
22.000.20(.866.008)SQ 20.000.10(.787.004)SQ
108 73
0.1450.055 (.006.002)
109
72
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
0~8
0.100.10 (.004.004) (Stand off)
144
37
"A" LEAD No.
1 36
0.50(.020)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.25(.010)
0.220.05 (.009.002)
0.08(.003)
M
C
2000 FUJITSU LIMITED F144019S-c-2-4
Dimensions in mm (inches) .
97
MB91110 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0204 (c) FUJITSU LIMITED Printed in Japan

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