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M61527FP
6ch ELECTRONIC VOLUME WITH 10 INPUT SELECTOR
REJ03F0036-0100Z Rev.1.0 Sep.19.2003
Feature
FUNCTION Electric Volume Input Selector Multi Channel Input REC Output Input ATT Input Gain Control Output Gain Control Balance Out FEATURE 6 channel independent with High Voltage Transistor. (0 to -99dB/ 1dBstep, -dB) Front L/R channel 10 Input Selector. All channel 2 Input Selector. 4 Lines REC Output (Both L and R channels) Input ATT (for ADC:0/-6/-12/-18dB) Input Gain Control (0/+6/+12/+18dB) Output Gain Control (0/+6/+12/+18dB) Built-in Balance out (for ADC)
Recommended Operating Condition
Rated Supply Voltage ......AVCC=7.0V(typ), AVEE=-7.0V(typ), DVDD=3.3V(typ)
Application
Receiver, AV Amp, Mini Stereo etc.
Rev.1.0, Sep.19.2003, page 1 of 17
M61527FP
System Block Diagram
CLOCK
Multi FRin Multi FLin DVDD AVEE AVCC DGND
REC OUTL
1 2 3 4 Lch 5 6 7 8 9 10 1 2 3 4 Rch 5 6 7 8 9 10 REC OUTR Balance Output R channel Input ATT (for ADC) Balance Output L channel Multi SLin Multi SRin Input ATT (for ADC) Multi Cin Multi SWin
Input Gain Control
MCU I/F
Input Gain Control Output Gain Control
LATCH DATA
Rev.1.0, Sep.19.2003, page 2 of 17
10 Input selector 10 Input selector
Lout
Input Gain Control Output Gain Control
Rout
Output Gain Control Input Gain Control Output Gain Control Input Gain Control Output Gain Control
SLout
SRout
Cout
Input Gain Control Output Gain Control
SWout
GND
M61527FP
Block Diagram and Pin Configuration (Top View)
33 SWSELOUT 39 SLSELOUT 38 CSELOUT
35 SWOUT
27 CLOCK
29 LATCH
34 SWVIN
Cch
SWch
Output Gain Control
SLOUT 41
SLch
GND AVCC DVDD
25 SWIN2
26 DGND
40 SLVIN
30 DVDD
36 COUT
31 AVCC
28 DATA
37 CVIN
32 GND
SROUT 42 SRch SRVIN 43 SRSELOUT 44 RSELOUT 45 RVIN 46 ROUT 47 NC 48 NC 49 NC 50 NC 51 NC 52 NC 53 LOUT 54 LVIN 55 LSELOUT 56 GND 57 RECL1 58 RECR1 59 RECL2 60 RECR261 RECL3 62 RECR3 63 GND 64
GND Lch
Rch
Output Gain Control
24 CIN2 23 SLIN2 22 SRIN2 21 RIN2 20 LIN2
GND Rch
Cch VOL
SWch VOL
MCU I/F
LATCH DATA CLK
SLchVOL
Output Gain Control Input Gain Control Input Gain Control
Multi Input Selector
SWch Cch
Multi Input Selector
19 GND 18 BALANCE R/17 BALANCE R/+ 16 GND 15 BALANCE L/ 14 BALANCE L/+ 13 GND 12 RIN1 11 LIN1 10 SLIN1
Output Gain Control
SLch
Multi Input Selector
SRchVOL Rch VOL
Output Gain Control
Input Gain Control Input Gain Control Input Gain Control
SRch
Multi Input Selector FL/FR VOL Input
GND Lch
Rch
FL/FR VOL Input
Input Gain Control
Lch
GND
Output Gain Control
Lch VOL
Lch Input ATT
9 SRIN1 8 SWIN1 7 CIN1
Rch
Input ATT
GND
6 GND 5 INR1 4 INL1
Lch
Rch
3 INR2 2 INL2 1 INR3
AVEE
GND
INL10/RECL4 65
INR10/RECR466
AVEE 67
INR7 73
INL9 68
INR9 69
INL8 70
INR8 71
INL7 72
INL6 74
INIR6 75
INL5 76
INR5 77
INL4 78
INR4 79
Rev.1.0, Sep.19.2003, page 3 of 17
INL3 80
M61527FP
Pin Description
PIN No. 5,3,1,79,77,75,73, 71,69 4,2,80,78,76,74,72, 70,68 6,13,16,19,32,57,64 7,24 8,25 9,22 10,23 11,20 12,21 14,15 17,18 26 27,28,29 30 31 33 34 35 36 37 38 39 40 41 48,49,50,51,52,53 42 43 44 45 46 47 54 55 56 58,60,62 /59,61,63 65 66 67 Name INR1,2,3,4,5,6,7,8,9 INL1,2,3,4,5,6,7,8,9 GND CIN1/CIN2 SWIN1/SWIN2 SRIN1/SRIN2 SLIN1/SLIN2 LIN1/LIN2 RIN1/RIN2 BALANCE L/+,L/BALANCE R/+,R/DGND CLOCK,DATA,LATCH DVDD AVCC SWSELOUT SWVIN SWOUT COUT CVIN CSELOUT SLSELOUT SLVIN SLOUT NC SROUT SRVIN SRSELOUT RSELOUT RVIN ROUT LOUT LVIN LSELOUT REC L1,L2,L3 /REC R1,R2,R3 INL10/REC L4 INR10/REC R4 AVEE Function Input pin of R channel (Input Selector) Input pin of L channel (Input Selector) Analog Ground Input pin of C channel (2 Input Selector) Input pin of SW channel (2 Input Selector) Input pin of SR channel (2 Input Selector) Input pin of SL channel (2 Input Selector) Input pin of L channel (2 Input Selector) Input pin of R channel (2 Input Selector) Output pin of L channel Balance Output(+/-) Output pin of R channel Balance Output(+/-) Ground of internal logic circuit Input pin of Control clock /data/ trigger Power supply to internal logic circuit Positive power supply to internal analog circuit Output pin of SW channel volume input selector Input pin of SW channel volume Output pin of SW channel Output pin of C channel Input pin of C channel volume Output pin of C channel volume input selector Output pin of SL channel volume input selector Input pin of SL channel volume Output pin of SL channel Non-connection terminal Output pin of SR channel Input pin of SR channel volume Output pin of SR channel volume input selector Output pin of R channel volume input selector Input pin of R channel volume Output pin of R channel Output pin of L channel Input pin of L channel volume Output pin of L channel volume input selector Output pin of REC (Lch and Rch) Input pin of L channel (Input Selector) / Output pin of REC (Lch) Input pin of R channel (Input Selector) / Output pin of REC (Rch) Negative power supply to internal analog circuit
Rev.1.0, Sep.19.2003, page 4 of 17
M61527FP
Absolute Maximum Ratings
Symbol Supply voltage Pd K Topr Tstg Parameter Power supply Power dissipation Thermal derating Operating temperature Storage temperature Condition AVCC-AVEE DVDD-GND Ta25C Ta>25C Ratings 8.0 6.0 1250 12.5 -20 to +55 -40 to +125 mW mW/C C C Unit V
THERMAL DERATINGS (MAXIMUM RATING) 1.5
POWER DISSIPATION pd (W)
1.0
0.5
0 0
55
25 50 75 100 125 150 AMBIENT TEMPERATURE Ta (C)
Recommended Operating Conditions
(Ta=25C, unless otherwise noted)
Parameter Analog supply voltage (Positive) Analog supply voltage (Negative) Digital supply voltage Logic "H" level input voltage Logic "L" level input voltage Note: AVEEDGNDDGND reference DGND reference
Rev.1.0, Sep.19.2003, page 5 of 17
M61527FP
Relationship between Data and Clock
H
LATCH SIGNAL D0 D1 D21 D22 D23 D0
DATA
L H
CLOCK
L H
LATCH
L
DATA signal is read at the rising edge of CLOCK. Serial data (D0 -D23) is loaded at the rising edge of the LATCH signal.
Clock and Data Timings
tcr
75%
tSC
CLOCK
25% 25%
tr tWHC
tf tWLC
75% 25%
DATA
tr
tf tSD tHD tSL tr
tWHC tf
75% 25%
LATCH
Rev.1.0, Sep.19.2003, page 6 of 17
M61527FP
Timing Definition of Digital Block
Limits Symbol tcr tWHC tWLC tr tf tSD tHD tSL tWHL tSC Parameter Clock cycle time Clock pulse width ("H" level) Clock pulse width ("L" level) Rising time of clock,data and latch Falling time of clock,data and latch Data setup time Data hold time Latch setup time Latch pulse width Clock setup time Min 4 1.6 1.6 -- -- 0.8 0.8 1 1.6 4 typ -- -- -- -- -- -- -- -- -- -- Max -- -- -- 0.4 0.4 -- -- -- -- -- Unit sec
Rev.1.0, Sep.19.2003, page 7 of 17
M61527FP
Data Control Specification
Initialize all data of the 3 formats when Digital Power supply (DVDD) turn on.
Rev.1.0, Sep.19.2003, page 8 of 17
REC REC REC REC
D0a D1a D2a D3a D4a D5a D6a D7a D8a D9a D10a D11a D12a D13a D14a D15a D16a D17a D18a D19a D20a D21a D22 D23
Slot0
Input ATT Output OutputOutput Output
1 2 3 4
Input Selector
Multi FL/FR Input VOL Selector Input
Input Gain Output Gain INS10 All Ch Control /REC4 Output Control
Multi Input Selector Mute Mute
0
0
0
1
0
D0b D1b D2b D3b D4b D5b D6b D7b D8b D9b D10b D11b D12b D13b D14b D15b D16b D17b D18b D19b D20b D21b D22 D23
Slot1
Lch Volume Rch Volume
Cch Volume
0
0
0
D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14c D15c D16c D17c D18c D19c D20c D21c D22 D23
Slot2
SLch Volume
SRch Volume
SWch Volume
0
0
1
M61527FP
Setting Code
(1)Input Selector Setting ALL OFF IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 (2)Input ATT Setting 0dB -6dB -12dB -18dB D4a 0 0 1 1 D5a 0 1 0 1 D0a 0 0 0 0 0 0 0 0 1 1 1 D1a 0 0 0 0 1 1 1 1 0 0 0 D2a 0 0 1 1 0 0 1 1 0 0 1 D3a 0 1 0 1 0 1 0 1 0 1 0 (4)Multi Input Selector Setting Multi IN1 Multi IN2 D10a 0 1
(5)FL/FR VOL Input Setting Bypass Multi Input D11a 0 1
(6)Input Gain Control Setting 0dB +6dB +12dB +18dB D12a D13a 0 0 1 1 0 1 0 1
(7)Output Gain Control Setting (3)REC Output REC Output REC1 REC2 REC3 REC4 Setting OFF ON D6a 0 1 D7a 0 1 D8a 0 1 D9a 0 1 0dB +6dB +12dB +18dB D14a D15a 0 0 1 1 0 1 0 1
(10)All Ch Output Mute Setting Mute off Mute on D17a 0 1
(8)IN10/REC4 Selector Setting IN10 REC4 D16a 0 1
(11)Multi Input Mute(Except for L/R) Setting Mute off
Depend on (4) Multi Input
D18a 0 1 It's initial setting when power is turned on.
Mute on
Note : Please don't input except specification data.
Rev.1.0, Sep.19.2003, page 9 of 17
M61527FP
(9)6 channel Volume Lch D0b D1b D2b D3b D4b D5b D6b SLch D0c D1c D2c D3c D4c D5c D6c Rch D7b D8b D9b D10bD11bD12bD13b SRch D7c D8c D9c D10cD11cD12cD13c Cch D14bD15bD16bD17bD18bD19bD20b SWch D14cD15cD16cD17cD18cD19cD20c 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB -16dB -17dB -18dB -19dB -20dB -21dB -22dB -23dB -24dB -25dB -26dB -27dB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Lch D0b D1b D2b D3b D4b D5b D6b SLch D0c D1c D2c D3c D4c D5c D6c Rch D7b D8b D9b D10bD11bD12bD13b SRch D7c D8c D9c D10cD11cD12cD13c Cch D14bD15bD16bD17bD18bD19bD20b SWch D14cD15cD16cD17cD18cD19cD20c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
ATT
ATT
-28dB -29dB -30dB -31dB -32dB -33dB -34dB -35dB -36dB -37dB -38dB -39dB -40dB -41dB -42dB -43dB -44dB -45dB -46dB -47dB -48dB -49dB -50dB -51dB -52dB -53dB -54dB -55dB
Rev.1.0, Sep.19.2003, page 10 of 17
M61527FP
Lch D0b D1b D2b D3b D4b D5b D6b SLch D0c D1c D2c D3c D4c D5c D6c Rch D7b D8b D9b D10bD11bD12bD13b SRch D7c D8c D9c D10cD11cD12cD13c Cch D14bD15bD16bD17bD18bD19bD20b SWch D14cD15cD16cD17cD18cD19cD20c 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Lch D0b D1b D2b D3b D4b D5b D6b SLch D0c D1c D2c D3c D4c D5c D6c Rch D7b D8b D9b D10bD11bD12bD13b SRch D7c D8c D9c D10cD11cD12cD13c Cch D14bD15bD16bD17bD18bD19bD20b SWch D14cD15cD16cD17cD18cD19cD20c 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
ATT
ATT
-56dB -57dB -58dB -59dB -60dB -61dB -62dB -63dB -64dB -65dB -66dB -67dB -68dB -69dB -70dB -71dB -72dB -73dB -74dB -75dB -76dB -77dB -78dB -79dB -80dB -81dB -82dB
-83dB -84dB -85dB -86dB -87dB -88dB -89dB -90dB -91dB -92dB -93dB -94dB -95dB -96dB -97dB -98dB -99dB
- dB
Note : Please don't input except specification data.
Rev.1.0, Sep.19.2003, page 11 of 17
M61527FP
Electrical Characteristics
Unless otherwise noted, Ta=25C, AVCC=7V, AVEE=-7V, DVDD=3.3V, f=1kHz, Volume=0dB, Input Selector=IN1, Input ATT=0dB, Input Gain Control=0dB, Output Gain Control=0dB, FL/FR Volume Input=Bypass, Multi Input Selector=Multi IN1 setting (1) Power supply characteristics
Limits Symbol Analog positive power circuit current Analog negative power Circuit current Digital power circuit current Parameter AIcc Test condition With AVCC=7V and AVEE=-7V Pin31 pin current, when no signal is provided With AVCC=7V and AVEE=-7V Pin67 pin current, when no signal is provided With DVDD=3.3V, Pin30 pin current, when no signal is provided min -- typ 50 max 70 Unit mA
AIee
-70
-50
--
mA
DIdd
--
3
6
mA
Rev.1.0, Sep.19.2003, page 12 of 17
M61527FP (2) Input/Output characteristics (OVER ALL)
Limits Symbol Input resistance Parameter Rin Test condition 1 to 5,65,66,68 to 80pin When each selector chooses a terminal concerned. (4,5,7,8,9,10)pin input, (54,47,36,35,42,41)pin output, THD=1%, RL=10k Output Gain Control=+12dB setting (4,5,7,8,9,10)pin input, (54,47,36,35,42,41)pin output, Vi=0.3Vrms,FLAT (4,5,7,8,9,10)pin input, (54,47,36,35,42,41)pin output, BW:400Hz to 30kHz, f=1kHz, Vo=0.3Vrms, RL=10k (4,5,7,8,9,10)pin input,(54,47,36,35,42,41)pin output, BW: 400Hz to 30kHz, f=1kHz, Vo=2Vrms, RL=10k (4,5)pin input, (54,47)pin output, Vi=0.3Vrms, JIS-A JIS-A, Output Gain (4,5,7,8,9,10)pin: Control=0dB Rg=0, Output Gain (54,47,36,35,42, Control=+12dB 41)pin output, Volume=-dB setting JIS-A, Output Gain (4,5,7,8,9,10)pin: Control=0dB Rg=0, Output Gain (54,47,36,35,42, Control=+12dB 41)pin output, Volume=0dB setting JIS-A, (4,5)pin:Rg=0, (14,15,17,18)pin output < Input selector > (54,47)pin output, Vo=1Vrms, Rg=0, RL=10k, JIS-A < Multi channel selector > (35,36,41,42,47,54)pin output, Vo=1Vrms, Rg=0, RL=10k, JISA, FL/FR VOL Input=Multi input min 35 typ 47 max 65 Unit k
Maximum output voltage
VOM
3.6
4.2
--
Vrms
Pass gain
Gv
-2.0
0
2.0
dB
Distortion
THD1
--
0.005
0.05
%
THD2
--
0.03
0.1
%
Channels balance Output noise voltage
CBAL Vono (VOL=-dB)
-0.5 -- --
0 1.5 9
0.5 6 20
dB Vrms Vrms
Vono (VOL=0dB)
-- --
2.5 12
8 25
Vrms Vrms
Input/Multi selector channel separation
Vonobal (Balance out) CS1
-- --
5 -90
10 -70
Vrms dB
CS2
--
-90
-70
dB
Rev.1.0, Sep.19.2003, page 13 of 17
M61527FP
Limits Symbol Cross talk between channels Parameter CT1 (FL/FR) Test condition (4,5)pin input, (47,54)pin output, Vo=1Vrms, Rg=0, RL=10k, JISA (7,8,9,10,11,12)pin input, (35,36,41,42,47,54)pin output, Vo=1Vrms, Rg=0, RL=10k, JISA, FL/FR VOL Input=Multi input min -- typ -90 max -70 Unit dB
CT2 (Multi Input)
--
-90
-70
dB
(3) 6 channel Volume characteristics
Limits Symbol Maximum attenuation Volume gain Between channels Parameter ATTmax Dvol Test condition (35,36,41,42,47,54)pin output, Vi=2Vrms,JIS-A,VOL=- 35,36,41,42,47,54)pin output, Volume=0dB setting min -- -0.5 typ -100 0 max -95 +0.5 Unit dB dB
Rev.1.0, Sep.19.2003, page 14 of 17
M61527FP
RECL1 RECL2 RECL3
Lch Balance out
Rch Balance out
GND
15 + 14
30 31 67
DVDD AVCC AVEE -7V DGND +3.3.0V +7V 26
58 60 62 16 18 + 17 47k 47k 47k
Internal Block Diagram
CLOCK
27 28 29
65 6 13 19 32 57 Input ATT 0/-6/-12/-18dB
47k
REC SW
GND GND GND GND GND
68
47k
MCU I/F
DATA LATCH
47k
RECR1 RECR2 RECR3
Rev.1.0, Sep.19.2003, page 15 of 17
47k
GND
64
FL/FR VOL Input
70 72 74
47k
47k 47k 47k 47k 47k 47k 47k
Input Gain Control
47k
76 78 80
47k
56
0/+6/+12/+18 dB
55 54
0~-99dB,mute
47k
LIN2 20 LIN1 11
23
INL10 /RECL4 INL9 INL8 INL7 INL6 INL5 INL4 INL3 INL2 INL1
Lch VOL 39
dB Input Gain 0/+6/+12/+18 Control
2 4
47k
LOUT
Output Gain Control 0/+6/+12/+18 dB
Input Selector
SLIN2 SLIN1 10 SRIN2 22 SRIN1 9
Multi Input Selector
40 SLch VOL 44 43
0~-99dB,mute
41
SLOUT
Output Gain Control 0/+6/+12/+18 dB
59 61 63
47k 47k 47k
47k 47k
Input Selector REC SW
SWIN2 25 SWIN1 8
dB Input Gain 0/+6/+12/+18 Control
SRch VOL 33
0/+6/+12/+18 dB 0~-99dB,mute
42
SROUT
Output Gain Control 0/+6/+12/+18 dB
66
47k
47k
47k
Input Gain Control
34 SWch VOL
35
SWOUT CIN2 24 CIN1 7
47k
Input Gain Control 0~-99dB,mute
69 71 Input ATT 0/-6/-12/-18dB
47k
38
0/+6/+12/+18 dB
Output Gain Control 0/+6/+12/+18 dB
47k
73 75
47k
47k
37 Cch VOL
0~-99dB,mute
36
COUT RIN2 21 RIN1 12
47k
47k
45
0/+6/+12/+18 dB FL/FR VOL Input Input Gain Control
Output Gain Control 0/+6/+12/+18 dB
47k
77 79 1
47k
46 Rch VOL
0~-99dB,mute
47
ROUT
Output Gain Control 0/+6/+12/+18 dB
47k
INR10 /RECR4 INR9 INR8 INR7 INR6 INR5 INR4 INR3 INR2 INR1
3 5
47k
NC NC NC NC NC NC
48 49 50 51 52 53
M61527FP
Application Example
C SW
AVCC DVDD 7V 3.3V
0.1u 0.1u 4.7u 4.7u 4.7u 4.7u 4.7u 100u
SWIN2 MCU
2.2u
100u
DGND
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
4.7u
Cch
SWch
Output Gain Control
4.7u
SL SR
41
SLch
GND AVCC DVDD
25
Output Gain Control
24 23 22 21
2.2u 2.2u 2.2u 2.2u 2.2u
CIN2 SLIN2 SRIN2 RIN2 LIN2
42 SRch 43 44 45 46 47 48 49 50 51 52
Rch
Cch VOL
SWch VOL
MCU I/F
LATCH DATA CLK
4.7u
SLchVOL
Output Gain Control Input Gain Control Input Gain Control
Multi Input Selector
4.7u
SWch Cch
Multi Input Selector
20
GND Rch
4.7u
19 18 17
R
Output Gain Control
-
SLch
Multi Input Selector
SRchVOL Rch VOL
Output Gain Control
Input Gain Control Input Gain Control Input Gain Control
+
ADC
SRch
Multi Input Selector FL/FR VOL Input
GND Lch
16 15 14
-
Rch
FL/FR VOL Input
+
4.7u
53 54 55
Lch
Output Gain Control
Input Gain Control
Lch
GND
13 12 11
2.2u 2.2u 2.2u 2.2u 2.2u 2.2u
RIN1 LIN1 SLIN1 SRIN1 SWIN2 CIN1
L
4.7u
Lch VOL
10
Lch Input ATT
56 57 58 59 60 61 62 63 64
AVEE
GND
9 8 7
GND
4.7u
RECL1 RECR1 RECL2 RECR2 RECL3 RECR3
4.7u
Rch
Input ATT
GND
4.7u
6 5 4
2.2u 2.2u 2.2u 2.2u 2.2u
INR1 INL1 INR2 INL2 INR3
4.7u
4.7u
Lch
Rch
4.7u
3 2 1
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
2.2u
2.2u
INL10 /RECL4
2.2u
INR10 /RECR4
AVEE -7V
2.2u
2.2u
2.2u
2.2u
2.2u
2.2u
2.2u
2.2u
2.2u
2.2u
2.2u
INR9
INR6
INL9
INR8
INR7
INR5
INR4
INL6
INL8
INL7
INL5
0.1u 100u
Rev.1.0, Sep.19.2003, page 16 of 17
INL4
INL3
80
2.2u
M61527FP
80P6N-A
JEDEC Code -- MD Weight(g) 1.58 Lead Material Alloy 42
MMP
Plastic 80pin 1420mm body QFP
EIAJ Package Code QFP80-P-1420-0.80
e
Package Dimensions
HD D
65 64
E
24 41
25
40
HE
A2
c
x
M
A1
Rev.1.0, Sep.19.2003, page 17 of 17
1
b2
I2 Recommended Mount Pad Symbol
A L1
A A1 A2 b c D E e HD HE L L1 x y L
Detail F
F e
b
y
b2 I2 MD ME
Dimension in Millimeters Min Nom Max -- -- 3.05 0.1 0.2 0 2.8 -- -- 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.8 -- -- 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 -- -- -- -- 0.2 0.1 -- -- 0 10 -- 0.5 -- -- 1.3 -- -- 14.6 -- -- -- -- 20.6
ME
80
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